JPH0348468B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for testing integrated circuits.

[Technical background of the invention and its problems]

To simplify testing of integrated circuits (hereinafter referred to as ICs), test circuits are usually provided within the IC. For example, with a one-chip CPU, the operation differs depending on the user's software program, and it is impossible to test it in the normal operation (NORMAL) state.To make testing easier, test terminals (external lead-out terminals) are provided, or It is designed to be in test mode depending on the combination of input terminals. However, providing the above test terminal is wasteful in normal use and results in a loss of one terminal. Furthermore, if the test mode is set by a combination of the several input terminals mentioned above, in order to maintain the normal state, input data must be input so as not to result in a combination that will result in the test mode. In other words, when using a combination of several input terminals, it is necessary to input data to the input terminals to avoid a test state. Therefore, it has the disadvantage that it cannot be used with random input data.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an integrated circuit testing method that eliminates the need for test terminals and eliminates the need to consider combinations of input terminals.

[Summary of the invention]

In order to achieve the above object of the invention, an external lead-out terminal for oscillation of the IC is used to enable switching between test and normal (normal operation).

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example using an oscillation circuit using a crystal oscillation element (LC), and FIG. 2 shows an example using a CR oscillation circuit. In FIG. 1, 1 indicates an IC. The crystal oscillation circuit 2 includes a crystal oscillation element 3, external capacitors 4 and 5, oscillation terminals (external terminals) X _IN and X _OUT , an inverter 6, and a resistor 7. Inverter 8,
9. Inverters 10 and 11 are for waveform shaping,
The shift registers 12 and 13 constitute, for example, a signal detection circuit in the preceding stage of the test circuit. In addition, in FIG. 2, an external resistor 21, a built-in capacitor 22, inverters 23 to 25, and a resistor 26 are connected to the CR oscillation circuit 27.
Configure.

As can be seen from FIGS. 1 and 2, a test circuit using X _IN and X _OUT of a clock oscillation circuit for IC operation is provided. Normally, in normal conditions, the reference clock is supplied by crystal oscillation as shown in Figure 1 or CR oscillation as shown in Figure 2. In the oscillation condition, _the operating waveforms of X _IN and Good.

FIG. 3 shows the timing in a normal state using crystal oscillation as shown in FIG. As shown in Fig. 3, in normal oscillation (normal state), the internal signal (reset signal) R is the internal signal (reference clock signal).
Since the CP always goes to the "H" (high) level once during one cycle, the shift registers 12 and 13 are reset, and the internal test signal remains at the "L" (low) level, entering the test mode. It won't be. Second
In the case of CR oscillation in the figure, the contents are the same as in the case of FIG. 1 above, and the test mode is not entered.
Also, even if the clock is supplied from an external crystal oscillation circuit or CR oscillation circuit, the clock on the X _IN side will
Since the X _OUT side also changes, it does not become a test mode, and therefore the normal state is maintained.

On the other hand, when performing a test, the terminal X _IN is fixed at the "L" level, the reset signal R is set at the "L" level, and the clock is forcibly output from the terminal X _OUT , as shown in the timing waveform in Figure 4. The test mode can be set by inputting a signal and setting the internal test signal Q _A to the "H" level by the signal detection circuit consisting of shift registers 12 and 13.

Therefore, according to this embodiment, since the terminals X _IN and X _OUT for clock supply are used for testing, external lead-out terminals dedicated to testing can be omitted, and switching between the test state and the normal state can be simplified. It can be done. In addition, when the crystal oscillation element 3 etc. is attached to perform normal oscillation _{and the device is used in normal use, the oscillation waveforms of the terminals X IN and} It never happens.

Note that the present invention is not limited to the above embodiments, and can be applied in various ways. For example, although the case where the shift register has two stages has been described, the number of stages may be further increased. Further, in the present invention, for example, the first
In Figure 2, input a signal that causes a reset when the reset signal R is "1" from the terminal X _IN , and then
This also includes cases in which normal operation is performed by inputting a clock signal only from X _OUT .

〔Effect of the invention〕

As described above, according to the present invention, the external lead-out terminal dedicated for testing can be omitted, so the number of terminals can be reduced, and switching between the test state and the normal state can be performed simply. Furthermore, since a shift register is used in the present invention, a transition to a test state can be made by applying a logic signal to an external lead-out terminal for oscillation. Further, since the shift register of the present invention has a reset terminal, it does not affect the normal oscillation operation.
Furthermore, since it has data input/output terminals, it can remember that it is in test mode and can continue to supply internal test signals.

[Brief explanation of drawings]

1 and 2 are circuit diagrams used in an embodiment of the present invention, and FIGS. 3 and 4 are timing waveform diagrams thereof. 1... Integrated circuit, 2... Crystal oscillation circuit, 12, 13
...Shift register, 27...CR oscillation circuit, X _IN ,
X _OUT ...Oscillation terminal (external lead-out terminal).

Claims (1)

[Claims] 1. A signal for setting the integrated circuit test circuit to test mode is applied to the first oscillation external lead-out terminal, a reference clock signal is applied to the second oscillation external lead-out terminal, and at least a data input/output terminal, A test detection shift register having a reset terminal is provided, and when the logic signal from the first oscillation external lead-out terminal is applied to the reset terminal and the shift register detects the start of the test, the internal test signal is output from the shift register. A method for testing an integrated circuit characterized by outputting .