JPH0348543B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a channel device, and relates to a channel device that converts data sent from an I/O (input/output device) in units of n bytes (for example, n=1) into n×m bytes ( For example m=4)
The present invention relates to a control method for checking errors in data to be transmitted when the data is assembled into a computer and transmitted to another device (for example, a main storage device).

[Prior art of the invention and its problems]

Generally, when data sent from I/O in 1-byte units is assembled into 4 bytes by a channel and transferred to an MSU (main storage unit) or SCU (storage control unit) via a 4-byte wide data bus, the 4-byte data is Transfer is performed with a byte mark indicating the position of a valid data byte within the byte. The byte mark generally only needs to be 1 bit for 1 byte, so
In this example, it is 4 bits.

On the other hand, the channel checks whether there is a parity error in the 4-byte data to be sent, and if there is an error, the parity is corrected to appear correct and transferred to the MSU or SCU.
The MSU or SCU apparently operates normally, and the channel reports it to the CPU (central processing unit) as a channel data check signal when a series of store processing is completed, such as at the time of an I/O interrupt.

If the store data from I/O is less than 4 bytes, or even if it is more than 4 bytes, but the store address is not on the 4-byte boundary, the 4-byte data sent to the MSU or SCU is There will be unnecessary bytes. For this reason, it is necessary to indicate whether each byte is valid or invalid using a byte mark. Even if an error occurs in an invalid byte position, there is no need to report it as a channel data check, and in order to do so, conventionally it was not necessary to provide a buffer register to assemble the data into 4 bytes. After initializing it to the correct parity, I/O
1 byte data from 1 byte was sequentially written to a predetermined byte position.

These buffer registers may be used for purposes other than the above store processing, and if a parity error occurs at that time, a report to that effect is sent to the CPU.
However, if data from the I/O is written to the register where the parity error occurs, and by chance there is no writing to the byte where the error occurs, the transfer to the MSU or SCU The parity error data still remains in the data, so when storing (MSU or
(When sending to SCU), an error is detected again. In consideration of such cases, the above-mentioned initialization has conventionally been performed.

In this way, it is a considerable burden on the channel to initialize the register each time for transfer of store processing. Especially 1
As the number of bytes transferred or the capacity of the buffer register increases, the time for initialization increases (in the case of sequential initialization) or the amount of hardware for initialization increases (in the case of initializing all bits at once). ).

[Purpose of the invention]

The present invention is to eliminate the need to initialize the buffer register and reduce the load on the channel.

[Embodiments of the invention]

The figure shows a block diagram of an embodiment of the present invention,
CH, CPU, MSU, and SCU are the same devices as described above.DBR0-3 are each 4-byte wide data buffer registers, BMR0-3 are 4-bit wide byte mark registers, and PC0-PC3 are 1-byte data buffer registers each. Parity checker G0 to G3 are two-input AND gates, and CD is a channel data check control section.

When a channel CH receives a store request from I/O, a control unit (not shown) determines the relationship between the first store address and the 4-byte boundary.
One byte at a time is written one after another from the desired byte position in DBR0. When DBR0 becomes full, its contents are shifted to DBR1, and subsequent bytes are written to DBR0. BMR corresponding to the byte position of DBR0 that was written in parallel with this.
A byte mark is written to 0. The location of the byte mark can be determined from the relationship between the first store address and the 4-byte boundary, as well as from the relationship with the data length to be transferred, and 0 or 1 is stored for four byte marks at a time. do. The contents of BMR0 are also changed in synchronization with the shift from DRR0 to DBR1.
Shifted to BMR1.

Furthermore, when DBR0 becomes full, the contents of DBR1 are
Shift to DBR2, shift the contents of DBR0 to DBR1, and sequentially pack up to a maximum of 16 bytes.
The same applies to BMR0-3.

For SCU, 4 byte data from DBR3,
Also, a 4-bit byte mark is sent from BMR3. The data of each byte is checked by PC0 to PC3 at the time of transmission as in the conventional case, but in the present invention, each check result is ANDed by each bit of BMR3 by gates G0 to G3, and the channel data is processed. Give to check control unit CDC. The CDC encodes the given error information and transmits the error information to the CPU.
At the time of this transfer, it may be possible to transfer whether or not there is an error at which byte position, or only the fact that there is an error may be transferred. If you want to transfer only the information that there is an error, change the output from the AND gate to
Record it on a latch etc. set up in the CDC,
After an appropriate time, the latched error information is read from the maintenance device of the service processor, etc. (the CPU notifies the service processor that there is an error), and error analysis is performed.

Therefore, even if an error occurs at a byte position without a byte mark, the error is not reported to the CPU. Therefore, there is no need to initialize DBR0 to DBR3 prior to transfer processing at the time of storage.

If a parity error is detected during the parity check, the parity will be corrected regardless of whether the bite mark is in the position or not.
Sending to MSU or SCU is exactly the same as before. Therefore, no changes are required on the MSU or SCU side. If a part of the byte mark is not set, it is a so-called partial write in the MSU or SCU, and 4 bytes including the byte to be stored are read from the MSU, and only the position where the byte mark is set is read from the channel CH. data is replaced and rewritten. Therefore, data at a position without a byte mark is not actually written to the MSU, so even if there is an error in the data and only the parity is forcibly corrected, there is no problem.

〔Effect of the invention〕

As described above, according to the present invention, it is not necessary to initialize the register every time store processing is performed, and therefore the load on the channel can be reduced, processing speed can be increased, and hardware can be reduced.

[Brief explanation of drawings]

The figure is a block diagram of an embodiment of the present invention.
DBR0-3 are 4-byte wide data buffer registers, BMR0-3 are 4-bit wide byte mark registers, PC0-3 are parity checkers in 1-byte units, G0-G3 are AND gates, CDC is channel data checker control section , SCU is the storage control unit, and MSU is the main memory control unit.

Claims (1)

[Claims] 1. Data sent from I/O in units of n bytes (n is an integer of 1 or more) is written to a desired position in the data buffer register, and the data buffer register is used to n×m bytes (m is 2
or above), set a byte mark corresponding to the position of the written data in the m-bit byte mark register, and send out each n byte of data in the data buffer register with the byte mark attached. In the channel device, the channel device includes a channel data check control unit that notifies a higher-level device of failure information of the transmitted data, and the channel device has a channel data check control unit that notifies a higher-level device of failure information of the data to be sent, and the channel device has a channel data check control unit that notifies a higher-level device of failure information of the transmitted data. an error check means for performing an error check on each n byte and indicating the presence or absence of an error for each n byte;
Means for detecting only the error presence/absence information corresponding to each n byte corresponding to the part where the byte mark stands based on the error presence/absence of each byte, and outputting this to the channel data check control section. A channel device comprising: