JPH0348596B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a row decoder circuit for a semiconductor memory, and particularly for an electrically writable non-volatile memory using read-system potentials and write-system potentials.

(Technical Background of the Invention) This type of memory, for example, the ultraviolet erase type
PROM (Programmable Read Only Memory)
In EPROM, the read potential V _cc (usually 5 V) is used for reading, and the write potential V _pp is used for writing.
(e.g. 12.5V) is applied to the selected word line from the row decoder circuit. The address signal given to this row decoder circuit is a _Vcc system signal both at the time of reading and writing, so the decoder circuit receives a _Vcc system input signal depending on whether it is a _Vcc system or a _Vpp system signal at the time of reading or writing. Means are provided for converting the signal into an output signal of the system.

FIG. 3 shows a conventional row decoder circuit in a CMOS type EPROM. In addition, FIG. 4 shows that the address signal input is divided into a plurality of groups and decoded in advance for each group to generate _Vcc system decoder selection signals g _i and _Vcc .
A pre-decoder circuit is shown for generating complementary word line selection signals _fi , _i of the system and supplying them to the decoder circuit, where 41 and 42
are a NAND circuit and an inverter circuit, respectively, which are operated by a _Vcc power supply.

The row decoder circuit, which receives as inputs the plurality of decoder selection signals g _i to g _j and a pair of complementary word line selection signals _fi , _i obtained by the predecoder, receives all address signals as inputs. The configuration is simplified by the row decoder circuit. That is, in the row decoder circuit shown in Figure 3, _Vcc is the power supply potential of the read system, and SW is
This is the power supply potential that switches to V _cc and V _pp (writing system power supply potential). 1 is a NAND circuit that operates under the _Vcc power supply to which the decoder selection signals g _i to g _j are input; 3
is the output node 2 of the NAND circuit 1 and the drive circuit 1
This is a transfer gate consisting of an N-channel FET (field effect transistor) inserted in series between input node 4 of 0, and the word line selection signal f _i is applied to its gate electrode. Reference numeral 5 denotes an N-channel transistor inserted between the input node 4 and the _Vcc potential, and the word line selection signal _i is applied to its gate. Note that the transfer gate 3 and the N-channel transistor 5 constitute a selection circuit 11. 6
is also a P-channel transistor inserted between the input node 4 and the SW potential, and the output potential of the drive circuit 10 is applied to its gate. The drive circuit 10 is a CMOS inverter consisting of a P-channel transistor 7 whose source is connected to SW potential and an N-channel transistor 8 whose source is connected to ground potential, and whose output node 9 is connected to a word line. There is. Note that a voltage conversion circuit 12 is configured by the P channel transistor 6 and the drive circuit 10.

In the above row decoder circuit, (a) When a word line changes from a non-selected state to a selected state, the inputs g _i to _{g j}
This is the case when all of the f i inputs are at high level (“1”), the f _i inputs are at “1”, and _{the i} inputs are at low level (“0”). In this case, the output node 2 of the NAND circuit 1 becomes "0", the transfer gate 3 is turned on, and the input node 4 of the drive circuit 10 falls toward "0". At this time, the initial state of the word line is "0" and the P channel transistor 6 is in the on state. However, as the potential of the input node 4 decreases, the output of the drive circuit 10 is inverted and the potential of the output node 9 rises toward the SW potential.
The conductance of the P-channel transistor 6 decreases, and the potential of the output node 9 eventually reaches SW−V _THP.
(threshold voltage of P channel transistor 6) or higher, transistor 6 is completely turned off,
Input node 4 becomes "0", output node 9 becomes SW potential, and becomes stable.

On the other hand, (b) when a word line changes from a selected state to a non-selected state, there are two ways (a) and (b) below.

(a) When the f _i input is “1”, _{the i} input is “0”, and any of the inputs g _i to g _j becomes “0”, the output of the NAND circuit 1 becomes “1”, and the transfer gate 3 to the input node 4 of the drive circuit 10 through
is charged to “1”. When the potential of this input node 4 reaches the threshold voltage of the drive circuit 10, its output is inverted and the potential of the output node 9 falls toward "0". The potential of this output node 9 is SW
-V _THP or less, the P-channel transistor 6 begins to turn on, the potential of the input node 4 rises toward SW, and eventually the output node 9 becomes completely "0" and the input node 4 reaches the SW potential. It becomes stable over time.

(b) When the inputs g _i to g _j are all “1” and the f _i input is “0” and _{the i} input is “1”, the transfer gate 3 is turned off and the N-channel transistor 5 is turned on. become a state. At that time, the input node 4 is charged to "1", and as in the case of the previous section (a), feedback is applied from the output node 9 of the drive circuit 10 to the P channel transistor 6, and the input node 4 is at the SW potential, and the output Node 9 becomes "0" and becomes stable.

(Problems with Background Art) By the way, the conventional row decoder circuit as described above has the following problems.

(b) When a word line changes from a non-selected state to a selected state.

At the time when the decoder selection signals g _i to g _j or the word line selection signals _fi , f _i are switched, the output node 9 is "0" and the P channel transistor 6 is in the on state. Therefore, in order to lower the input node 4 toward "0" to a level sufficient for the drive circuit 10 to invert, each of the P channel transistor 6, the transfer gate 3, and the N channel transistor in the NAND circuit 1 must be It is necessary to consider the conductance balance,
The margin in circuit pattern design becomes narrower.

(b) When a word line changes from a selected state to an unselected state.

At the time when the decoder selection signals g _i to g _j or the word line selection signals f _i to _i are switched, the input node 4 is in the initial state "0", so the transfer gate 3 or the N channel transistor 5
is charged via. In this case, both the transfer gate 3 and the N-channel transistor 5 are enhancement type FETs, and the influence of deep implantation to suppress the short channel effect that accompanies miniaturization is large, and the reference bias effect (well-known (The explanation is omitted here) is large. The following two problems arise due to the influence of this substrate bias effect.

(1) The input node 4 is charged by the transfer gate 3 or the N-channel transistor 5, and as the potential of the input node 4 increases, the conductance of the transfer gate 3 or the N-channel transistor 5 rapidly increases. decreases to Therefore, the rise of the input node 4 is delayed, and the drive circuit 10
is inverted and feedback is generated to the P-channel transistor 6, which lengthens the time it takes for the input node 4 to charge up to the SW potential and settle into a stable state (decoding operation time), which has a large effect on the memory access time.

(2) Transfer gate 3 or N-channel transistor 5, which is an N-channel enhancement type FET, has a strong back gate bias effect, so the potential of input node 4 is V _cc -
It only goes up to V _TH . This is explained in the previous section.
As mentioned in (1), not only is the rise of the input node 4 delayed, but if the _Vcc potential is lowered, the potential of the input node 4 does not reach a potential sufficient to invert the drive circuit 10, and the row decoder circuit may not function properly. In other words, the minimum allowable value of the EPROM read-out system potential V _cc is defined by the row decoder circuit, so there is a risk that the V _cc margin will be narrowed.

(Objective of the Invention) The present invention was made to eliminate each of the drawbacks of the conventional example described above, and provides a row decoder circuit for a non-volatile memory that has a wide circuit pattern design margin, can operate at high speed, and has a wide power supply margin. This is what we provide.

(Summary of the Invention) That is, the present invention provides a nonvolatile memory row decoder circuit that outputs a _Vcc potential and _{a Vpp} potential as word line selection potentials in response to reading and writing. The multiple decoder selection signals of the V _cc system obtained by decoding are input to the V _cc system AND circuit, and the V _cc system output of this AND circuit is input to the voltage conversion circuit to correspond to reading and writing. to convert the voltage to _Vcc system and _Vpp system output,
The output of this voltage conversion circuit is input to a selection circuit, and this selection circuit is controlled by a complementary word line selection signal obtained through pre-decoding of a part of the address signal, and the output of the voltage conversion circuit is input to the word line. This feature is characterized in that the word line is transmitted or the word line is set to a non-selected state.

By providing a voltage conversion circuit between the AND circuit and the selection circuit in this way, it is possible to reliably convert the V _cc system decoder selection signal input into V _cc system and V _pp system signals.
A circuit configuration that allows high-speed conversion and a wide V _cc margin becomes possible.

(Embodiment of the Invention) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Figure 1 shows, for example, a CMOS type EPROM
shows one row decoder circuit of g _i ~g _j
is the _Vcc system decoder selection signal input from the predecoder circuit as described above, and f _i ′ and _i ′ are SW
Complementary word line selection signal for the system, V _cc is the read system potential, SW is V _cc , depending on the read and write times.
This is the potential that switches to _Vpp (writing system potential).
20 is a decoder circuit selection NAND circuit which operates under the _Vcc power supply and receives the signals g _i to g _j ; 21 is a decoder circuit selection circuit when reading out the output signal ( _Vcc system) of the NAND circuit 20;
Depending on the writing time, _Vcc system and _Vpp system signals, that is,
Voltage conversion circuit that converts voltage into SW potential signal, 2
Reference numeral ₂ designates a selection circuit that transmits the output voltage of the voltage conversion circuit 21 to the word _line or sets the word line to a non-selected state by lowering the word line to the ground potential according to the word line selection signals f i ′, i ′. .

In the voltage conversion circuit 21, the input node 2
3 is connected to one end of a transfer gate 24 consisting of an N-channel enhancement type FET, and _{a Vcc} potential is applied to the gate electrode of this gate. 25 is a CMOS inverter circuit,
The drains of a P-channel transistor 26 to which a SW potential is applied to the source and an N-channel transistor 27 whose source is connected to a ground potential are connected to each other.
The gate of the P channel transistor 26 is connected to the input node 23, and the gate of the P channel transistor 26 is connected to the other end (node 28) of the transfer gate 24. Further, a P channel transistor 29 is connected between the node 28 and the SW potential, and its gate is the output node of the inverter circuit 25 (which is the output node of the voltage conversion circuit 21).
30.

On the other hand, the selection circuit 22 includes a parallel circuit (CMOS transfer gate) of a P channel transistor 31 and an N channel transistor 32 inserted between the output node 30 of the voltage conversion circuit 21 and the word line, and the word line. and an N-channel transistor 33 connected to the ground potential. In order to transmit the SW system signal input from the voltage conversion circuit 21 to the word line by the CMOS transfer gate, SW system word line selection signals f _i ′, _i ′ are applied as gate control inputs of the CMOS transfer gate. A SW potential-based word line selection signal _i ' is also applied to the gate of the N-channel transistor 33.

Next, the operation of the row decoder circuit will be explained.
Voltage conversion circuit 21 is applied to input node 23
It has the function of inverting the _Vcc system signal and outputting it as a SW system signal. That is, when the input node 23 is "1", the N-channel transistor 27 of the inverter circuit 25 is on, the output node 30 is at the ground potential, and the P-channel transistor 29, which is feedback-controlled by the potential of the output node 30, is on. , the node 28 is pulled up to the SW potential, and at this time, the transfer gate 2
4 is the SW potential of the above node 28 and the input node 23
It is separated from the _Vcc system potential. On the contrary,
When the input node 23 is “0”, the transfer gate 24 is turned on and the N of the inverter circuit 25 is turned on.
Channel transistor 27 is turned off, P-channel transistor 26 is turned on, and output node 30 is turned off.
The potential is set to SW, and the P channel transistor 29 is turned off.

On the other hand, in the selection circuit 22, the f _i ′ input is SW
potential, _i ' When the input is at ground potential, transistors 31 and 32 are on, respectively, and transistor 3 is on.
3 is turned off, and the potential of the output node 30 of the inverter circuit 25 is directly transmitted to the word line. If the output node 30 is at SW potential, the word line is in a selected state, and if the output node 30 is at ground potential, the word line is in a non-selected state. It becomes selected state. Furthermore, when the fi' input is at ground potential and _{the i} ' input is at SW potential, transistors 31 and 32 are turned off and transistor 33 is turned on, so the word line potential is lowered to ground potential and the word line is unselected. become a state.

This configuration eliminates the influence of the substrate bias effect of the N-channel enhancement type transistor, which was a problem in the conventional example, provides a wide margin for circuit pattern design, and enables high-speed operation.
CMOS type EPROM with wide V _cc margin
row decoder circuit. The reason for this will be explained in detail below.

(a) When the output node 30 rises from ground potential to SW potential.

In the initial state, the output node 30 is at ground potential,
Let us consider the case where the input node 23 is set to _Vcc and then all the decoder selection signal inputs g _i to g _j are switched to "1". At this time, the input node 23 is quickly set to "0" by the NAND circuit 20,
This "0" potential is applied to the N-channel transistor 27 of the inverter circuit 25, and this transistor 27 is completely turned off. On the other hand, the node 28 begins to be lowered to "0" via the transfer gate 24, and the potential of the node 28 increases.
When SW-V _THP is reached, the P-channel transistor 26 of the inverter circuit 25 is turned on, and the potential of the output node 30 rises toward the SW potential. The potential of this output node 30 is fed back to the P channel transistor 29, the conductance of this transistor 29 becomes low, the node 28 is at the "0" level, and the output node 3
0 becomes the SW potential and becomes stable. That is, in the above circuit, the N-channel transistor 27 of the inverter circuit 25 is completely turned off by applying the potential "0" of the input node 23 directly to the gate regardless of the potential of the node 28, and further 28 drops to SW-V _THP , the P channel transistor 26 of the inverter circuit 25
is completely turned on, making it possible to invert the potential of the output node 30. Therefore, there is no need to delicately balance the conductance of each transistor to ensure this output inversion, and the margin for circuit pattern design is reduced compared to conventional methods. It will be wider than the example.

(b) When the output node 30 falls from the SW potential to the ground potential.

In the initial state, the output node 30 is at the SW potential and the input node 23 is at "0", and then a case will be considered in which one of the decoder selection signals g _i to g _j is switched to "0". At this time, the input node 23 is N
Since it is directly connected to the gate of channel transistor 27, this transistor 27 is turned on and the potential of output node 30 begins to fall. On the other hand, the node 28 is the transfer gate 2
Output level “1” of NAND circuit 20 via 4
is conveyed. Also, the output node 30 is SW−V _THP
Since the P-channel transistor 29 is turned on when the potential of the node 28 drops to
It rises towards the SW potential. As a result, the P channel transistor 2 of the inverter circuit 25
6 is turned off, and the output node 30 becomes the ground potential and becomes stable. That is, in the above circuit, regardless of the potential of the node 28, the N of the inverter circuit 25
The channel transistor 27 is completely turned on by applying the potential "1" of the input node 23 directly to its gate, and the potential of the output node 30 becomes SW-.
When it drops to V _THP , the P channel transistor 29
quickly turns on and the inverter circuit 2
No. 5 P channel transistor 26 is immediately turned off. Therefore, if the rise of the potential at the node 28 is delayed due to the influence of the substrate bias effect of the N-channel enhancement type transistor constituting the transfer gate 24, or if the _Vcc potential is lowered, the inverter circuit 2
There is no problem that the potential does not drop to a level sufficient to invert the output of 5, and compared to the conventional example, high-speed operation is possible and the V _cc margin is widened.

By the way, the CMOS type EPROM row decoder circuit according to the present invention has a configuration in which a voltage conversion circuit 21 is provided between a NAND circuit 20 and a selection circuit 22. In other words, by adopting this configuration, the CMOS type EPROM has the effect of widening the circuit pattern design margin as described above, enabling high-speed operation, and widening the _Vcc margin.
row decoder circuit.
That is, connecting the input node 23 to the gate of the N-channel transistor 27 is one component for obtaining the above effect, but the selection circuit 2 is connected between the NAND circuit 20 and the voltage conversion circuit 21.
2, the input node 23 is connected to the N-channel transistor 27 via the selection circuit 22.
must be connected to the gate. this is,
In reality, this is not preferable because it causes the wiring pattern to be significantly complicated, which causes disadvantages that outweigh the advantages of the present invention.

Note that in the past, one voltage conversion circuit 12 was required for one selection circuit 11;
In the present invention, since voltage conversion is performed in advance, there is an effect that it is sufficient to provide one voltage conversion circuit 21 for several selection circuits 22.

In addition, in the above embodiment, the word line selection signals fi', ' of the SW potential system are the output signals f _i , _i of the V _CC predecoder circuit similar to the conventional example, as shown in FIG. 2, respectively. , the voltage conversion circuit 21
This can be obtained by converting into the SW potential system using voltage conversion circuits 21' and 21'' similar to the above.
Here, the operation of the voltage conversion circuits 21', 21'' when using SW potential-based word line selection signals fi', ' is the same as the operation of the voltage conversion circuit 21 shown in FIG. 1. However, During writing, when the voltage conversion circuit 21 outputs a _VPP system potential as a SW system signal, the complementary word line selection signals fi','
SW converted by voltage conversion circuit 21', 21''
The V _PP system potential must be used as the system signal. Also, at the time of reading, the voltage conversion circuit 21
When a V _CC system potential is output as a SW system signal from
The potential of the V _CC system must be used as the SW system signal.

(Effects of the Invention) As described above, according to the row decoder circuit for a nonvolatile memory of the present invention, effects such as a wide circuit pattern design margin, high-speed operation, and a wide power supply margin can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a row decoder circuit of a nonvolatile memory according to the present invention, and FIG.
The word line selection signal f _i ′ to be given to the circuit shown in the figure,
A circuit diagram showing a predecoder circuit for creating _i ′,
FIG. 3 is a circuit diagram showing a conventional EPROM row decoder circuit, and FIG. 4 is a circuit diagram showing part of a predecoder circuit for generating the decoder selection signal and word line selection signal to be provided to the circuit in FIG. 3. It is. 20... NAND circuit, 21... Voltage conversion circuit,
22...Selection circuit, 23...Input node, 24...
... Transfer gate, 25 ... Inverter circuit, 26, 29, 31 ... P channel transistor, 27, 32, 33 ... N channel transistor, 30 ... Output node, g _i - g _j ... Decoder selection signal, f _i ′, _i ′...Word line selection signal.

Claims (1)

[Claims] 1. In a row decoder circuit of a nonvolatile memory that outputs a V _PP system potential as a word line selection potential during writing and outputs a V _CC system potential as a word line selection potential during reading, Multiple decoder selection signals of V _CC system obtained by some pre-decoding are input,
A V _CC system AND circuit outputs the V _CC system potential, and the V _CC system output of this AND circuit is input, and during writing, the V _CC system output is converted to the V _PP system potential and output. and a voltage conversion circuit that converts the output _of the V _CC system to a potential of _{the V CC system} and outputs it at the time of _reading ; Whether or not to output the output of the V _PP system of the voltage conversion circuit as a word line selection potential is controlled by the complementary word line selection signal of the V _CC system during reading. A row decoder circuit for a nonvolatile memory, comprising a selection circuit that controls whether or not the output of the V _CC system of the voltage conversion circuit is output as a word line selection potential. 2. The voltage conversion circuit includes an N-channel transistor whose gate is connected to an input node and whose source is grounded, and whose drain is connected to the drain of the N-channel transistor, and when reading to the source,
an inverter circuit consisting of a P channel transistor to which V _CC system and V _PP system potentials are applied in response to writing, and an N channel enhancement type transistor connected between the gate of the P channel transistor and the input node. Become,
A transfer gate to which a potential of the V _CC system is applied, a gate of the P channel transistor, and a V _{CC voltage} at the time of reading and writing.
A P channel transistor connected between a V system and a potential terminal to which a potential of a V _PP system is applied, and a P channel transistor whose gate is applied with a potential of an output node of the inverter circuit. A row decoder circuit for a nonvolatile memory according to item 1. 3. The selection circuit is inserted between the output node of the voltage conversion circuit and the word line, and has a CMOS transfer gate in which a P-channel transistor and an N-channel transistor are connected in parallel, and a connection between the word line and a ground potential terminal. A complementary word line selection signal of the V _PP system is applied to each gate of the CMOS transfer gate during writing, and a complementary word line selection signal of the V _CC system is applied during reading. is applied to each gate of the CMOS transfer gate, and an N-channel transistor between the word line and the ground potential terminal is connected to the word line so that it turns on and off in inverse correspondence to the on and off states of the CMOS transfer gate. 2. A row decoder circuit for a nonvolatile memory according to claim 1, wherein said row decoder circuit is controlled by one of the selection signals. 4 The complementary word line selection signals are V _CC -based complementary word line selection signals obtained by pre-decoding a part of the address signal, and are converted to V _CC by a voltage conversion circuit similar to the voltage conversion circuit. 2. The row decoder circuit for a non-volatile memory according to claim 1, wherein the row decoder circuit is converted into a VPP system signal or a _VPP system signal. 5. The complementary word line selection signal is a V _CC type word line selection signal obtained by pre-decoding a part of the address signal, which is converted into a V _CC type or V _PP type word line selection signal by a voltage conversion circuit similar to the voltage conversion circuit. 2. A row decoder circuit for a non-volatile memory according to claim 1, wherein the row decoder circuit is converted into a complementary signal of a non-volatile memory.