JPH0348701B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system selection circuit for a duplex configuration system suitable for a highly reliable device that generates a reference clock signal for a communication device or an information processing device.

[Conventional technology]

The system selection circuit of a duplex configuration system operates two signal sources simultaneously and selects and uses one of them, but if a failure occurs in the selected signal source, it automatically switches to the other signal source. Can be switched to select signal source.

Such a system selection circuit is provided in an exchange, for example, as shown in FIG. 5, and selects the outputs of the 0-system reference clock generation circuit and the 1-system reference clock generation circuit, and selects the output from the 0-system reference clock generation circuit and the 1-system reference clock generation circuit to select the output from the communication line equipment, etc. It is given to

FIG. 3 is a block diagram of a conventional system selection circuit, and FIG. 4 is a time chart showing an example of the operation of each part thereof.

The currently selected signal source (temporarily assume SG ₀ )
When a fault occurs, the signal source fault monitoring device AL ₀
outputs "1", the output AL of the selection circuit _SL1 becomes "1", and the output of the RS flip-flop circuit _F2 in the reset state (hereinafter referred to as _F2 ()).
is "1", so the output of AND circuit A ₁ is A _1put
becomes "1", and the output Q of the JK flip-flop circuit F ₁ (hereinafter referred to as F ₁ (Q)) is inverted and input to the selection signal input terminal SS to switch the signal source.

That is, the signal source is selected by the selection circuits SL ₀ and SL ₁ according to the output of the JK flip-flop circuit F ₁ ,
For example, if F ₁ (Q) is "1", the signal source SG ₁ is selected, and if F ₁ (Q) is "0", the signal source SG ₀ is selected.

[Problem that the invention seeks to solve]

However, when the selected signal source is forcibly switched in such a system selection circuit due to maintenance reasons, the other newly selected signal source may be faulty or the unit may not be connected. be. In conventional system selection circuits, when such switching is performed, there is a problem in that a state in which a selection signal is not sent to the input of the system selection circuit continues, that is, the faulty signal source remains selected. This point will be explained below.

As an initial state, it is assumed that the selection state selects the signal source SG ₀ side, while the signal source SG ₁ has a fault and the signal source fault monitoring device AL ₁ is outputting "1".
In this state, when trying to forcefully switch from signal source SG ₀ to signal source SG ₁ , the selection control signal input terminal CS
When a positive pulse is applied to and the selection control signal CS becomes "1", "1" is input to the preset input _Pr of the JK flip-flop circuit _F1 , and _F1 (Q) becomes "1" (is the time Chart transition order number (the same applies hereafter), "1" to the selection signal input terminal SS
is input, selects input terminal X ₁ , and switches to signal source SG ₁ . On the other hand, RS flip-flop circuit F ₂
Since the reset input R of F2 becomes "1", F ₂ ()
becomes "1". Since the output of the signal source fault monitoring device AL ₁ is "1", the output AL of the selection circuit SL ₁
becomes "1". The input of the AND circuit A ₁ is the output AL and F ₂ () of the selection circuit SL ₁ are both “1”.
Therefore, the output A _1put becomes "1".
However, since the selection control signal CS is "1",
Preset input P _r of JK flip-flop circuit F ₁
Since remains "1", F ₁ () is not inverted.

The pulse of the selection control signal CS falls and becomes “0”
Then, the output of OR circuit B becomes "0",
On the other hand, the output AL "1" of the selection circuit SL ₁ is input to the set input S of the RS flip-flop circuit F ₂ after passing through the delay circuit D, so that the output signal F ₂ is inputted after a time delay.
() becomes "0". Therefore, since one of the inputs of the AND circuit _A1 becomes "0", its output _A1put becomes "0". The JK flip-flop circuit _F1 remains unchanged, and the selection circuit SL continues to select the signal source _SG1 having no output signal.

The present invention has been made by focusing on such conventional problems, and provides a system selection circuit that enables automatic recovery when a selection control signal selects a faulty system. With the goal.

[Means for solving problems]

The present invention makes it possible to reverse a once-selected faulty system to a normal system by prohibiting fault display when a selection control signal is input from the outside.

That is, a first selection circuit receives the output signals of two signal sources and selects one of them; two signal source failure monitoring circuits are connected to each of these two signal sources and display a failure; and a second selection circuit that receives the output signal of the monitoring circuit and selects one of the output signals in conjunction with the first selection circuit;
It holds a selection control signal from the outside and gives a selection signal to the above two selection circuits according to the selection control signal, and when a signal indicating a fault appears at the output of the second selection circuit, the selection is made. In a system selection circuit equipped with a holding circuit for inverting a signal, when the selection signal is inverted by the selection control signal from the outside and a signal indicating a failure appears at the output of the second selection circuit, The present invention is characterized by comprising logic circuit means for automatically inverting the selection signal again.

Preferably, the logic circuit means is an AND gate circuit that is inserted into the output path of the second selection circuit and uses an inverted signal of the selection control signal from the outside as a gate signal.

[Effect]

The present invention includes a circuit that prohibits failure indication when a selection control signal from an external source is input, so that after the selection signal holding circuit once holds the failure system selection signal, the selection signal is inverted by the failure indication signal. Therefore, the signal source of the normal system can be automatically reselected.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a system selection circuit showing one embodiment of the present invention, and FIG. 2 is a time chart showing an example of the operation of each part. The signal source SG ₀ is connected to the input terminal X ₀ of the selection circuit SL ₀ and to the input terminal X ₀ of the selection circuit SL ₁ through a signal source fault monitoring device AL ₀ which monitors the output signal of the signal source SG ₀ . ₁ is the input terminal X ₁ of the selection circuit SL ₀ and the signal source fault monitoring device
Through AL ₁ , it is connected to the input terminal X ₁ of the selection circuit SL ₁ . Signal source fault monitoring devices AL ₀ and AL ₁
outputs “1” when a failure is detected in the signal source SG. The selection circuits SL ₀ and SL ₁ select the input terminal X ₀ or X ₁ and output the input signal to the output terminal X according to whether the signal input to the selection signal input terminal SS is "0" or "1". The output from the output terminal X of the selection circuit SL ₀ is input to an information processing device or the like.

The output from the output terminal X of the selection circuit SL ₁ is connected to one input of the AND circuit A ₀ , and its output is connected to one input of the AND circuit A ₁ . The selection control signals CS and CR from the selection control signal input terminals CS and CR are input to the OR circuit B, the output of which is input to the reset input R of the RS flip-flop circuit _F2 and the inversion circuit I, and this output is Connected to the other input of AND circuit A ₀ .

The set input S of the RS flip-flop circuit _F2 is
It is connected to the output of the AND circuit _A0 through a delay circuit D. The output F ₂ ( ) of the RS flip-flop circuit F ₂ is connected to the other input of the AND circuit A ₁ . In addition, the selection control signals CS and CR are
Preset input P _r of JK flip-flop circuit F ₁
and clear input _C1 respectively. The output of the AND circuit A ₁ is the JK flip-flop circuit F ₁
rising edge trigger clock input terminal C
Enter. Output of JK flip-flop circuit F ₁
QF ₁ (Q) is connected to selection signal input terminals SS of selection circuits SL ₀ and SL ₁ . Both J and K inputs of JK flip-flop circuit _F1 are logic “1”
is being entered.

Here, the operations of the inverting circuit I and the AND circuit _A0 , which are the features of this embodiment, will be explained. With these two circuits, when the selection control signal CS is input, the output F ₁ (Q) of the JK flip-flop circuit F ₁ is inverted, and when the selection circuit SL is switched, the fault output "1" is output from the selection circuit SL ₁ . Even if it is output, the output of "1" from the AND circuit _A1 is prohibited during the period when the selection control signal CS is "1". Then, when the selection control signal CS falls and becomes "0", "1" is output from the AND circuit _A1 and the output _F1 of the JK flip-flop circuit _F1 .
(Q) is reversed to restore the signal source to the normal system.
This is because in the conventional device, when the selection control signal CS is in the "1" state, the AND circuit _A1 output becomes "1", and after the selection control signal CS falls,
This is to prevent the output of the AND circuit _A1 from becoming "0" and the output from the JK flip-flop circuit _F1 not being inverted and returning to the normal system.

Next, the operation of this embodiment will be explained in detail.

The currently selected signal source (temporarily assume SG ₀ )
When a failure occurs, the signal source failure monitoring device
AL ₀ outputs “1” and selection circuit SL ₁ output AL
becomes "1", and one input of the AND circuit _A0 becomes "1". When there is no selection control signal from the outside, the other input of the AND circuit A ₀ is "1", so the output A _0put of the AND circuit A ₀ becomes "1".
Since F ₂ () in the reset state is "1", the output A _1put of AND circuit A ₁ becomes "1", and F ₁
(Q) is inverted to switch the signal source.

Next, when _both signal sources SG ₀ and SG ₁ are _normal and input terminal When this is applied, the output Q of the JK flip-flop circuit _F1 becomes "1", "1" is input to the selection signal input terminal SS, the input terminal _X1 is selected, and the signal source _SG1 is switched. Signal sources SG ₀ and SG ₁
are both normal, so the output of selection circuit SL ₁
AL is “0”, so the AND circuit A ₀ ,
Further, the output of _A1 becomes "0", and the output Q of the JK flip-flop circuit _F1 does not change, and the signal source _SG1 remains selected.

Now, a case will be explained in which the destination to which the switch is made is causing a failure. As an initial state, it is assumed that the selection state selects the signal source SG ₀ side, while the signal source SG ₁ has a fault and the signal source fault monitoring device AL ₁ is outputting "1". In this state, in an attempt to forcibly switch from signal source SG ₀ to signal source SG ₁ , a positive pulse is applied to the selection control signal input terminal CS, and when the selection control signal CS becomes "1", the JK flip-flop circuit F ₁ ``1'' is input to the preset input P <sub>r</sub> of , F <sub>1</sub> (Q) becomes ``1'', and ``1'' is input to the selection signal input terminal SS, switching to the signal source SG ₁ side. On the other hand, since the reset input R of the RS flip-flop circuit F ₂ becomes "1", F ₂ (Q) becomes "1".
becomes. Since the output of the signal source fault monitoring device AL ₁ is "1", the output AL of the selection circuit SL ₁ is "1".

Further, since the output of the OR circuit B is "1", it becomes "0" in the inverting circuit I, and therefore the output A _0put of the AND circuit A ₀ is "0". On the other hand, the input of the AND circuit A ₁ is the output A _0put of the AND circuit A ₀
and F ₂ (Q), so its output is "0",
No change is made to F ₁ (Q).

The pulse of the selection control signal CS falls and becomes “0”
Then, the output of OR circuit B becomes "0",
Changed to "1" by inverting circuit I, output of selection circuit SL ₁
Since AL is “1”, the output of AND circuit A ₀
A _0put becomes "1". Then, AND circuit A ₁
Since F ₂ () is "1" at the input of
A _1put becomes "1".

On the other hand, the change of the output A _lput of the AND circuit A ₁ from "0" to "1" becomes the clock input of the JK flip-flop circuit F ₁ , and F ₁ (Q) is inverted from "1" to "0". . After that, the selection circuit SL ₁ reselects the normal signal source SG ₀ , so the selection circuit SL ₁
The output AL becomes “0”, and the AND circuit
The output A _0put of A ₀ also becomes "0".

On the other hand, the output A _0put "1" of the AND circuit A ₀ is input to the set input S of the RS flip-flop circuit F ₂ via the delay circuit D, so F ₂
() becomes "0", and the output A 1put of AND circuit A ₁ becomes " _{1 "} at the timing when either of the previous output A _0put of AND circuit A 0 and F ₂ () becomes "0" to "0". Then, the JK flip-flop circuit _F1 is in an unchanged state, and the selection circuit SL
The signal source SG ₀ remains selected.

According to this sequence, when a positive pulse is applied to the selection control signal CS, the output F ₁ (Q) of the JK flip-flop circuit F ₁ becomes "1" once, but then becomes "0" again and the normal signal source SG ₀ is turned off. You will have to choose. In this operation, by providing the AND circuit _A0 , automatic switching is performed by the failure indication AL after the switching operation by the selection control signal from the outside is completed.

Note that the selection control signal CR is a signal that forcibly switches the signal source from signal source SG ₁ to signal source SG ₀ , contrary to the selection control signal CS, and the point at which the JK flip-flop circuit F ₁ is reset is the selection control signal CS. different from. Therefore, the only difference from the selection control signal CS is the logic of the output of the selection signal input terminal SS, ie, F ₁ (Q), and the other time charts are the same as the selection control signal CS.

The above is a case where the flip-flop circuit causes a state change at the rising edge of the input clock pulse, but even in the case of a rising edge trigger, it is possible to configure various circuits that execute the same logic other than those shown in the above example. The present invention can be carried out in the same manner using these.

〔Effect of the invention〕

As explained above, the present invention is equipped with a circuit that prohibits fault indication when receiving a selection control signal from the outside, so that the signal source can be quickly restored to normal after switching to a faulty signal source by the selection control signal. There is an effect that the selection state is returned to the system, that is, the signal source of the normal system can be automatically selected.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system selection circuit showing one embodiment of the present invention. FIG. 2 is a time chart showing an example of the operation of each part of a circuit according to an embodiment of the present invention. Third
The figure is a block diagram of a conventional system selection circuit. FIG. 4 is a time chart showing an example of the operation of each part of the conventional circuit. FIG. 5 is a diagram showing an example in which a system selection circuit is used. SG ₀ , SG ₁ ... signal source, SL ₀ , SL ₁ ... selection circuit,
SS...Selection signal input terminal, AL ₀ , AL ₁ ...Signal source failure monitoring device, A ₀ , A ₁ ...AND circuit, B...OR circuit, D...delay circuit, I...inverting circuit, F ₁ ...JK flip-flop Circuit, F ₂ ...RS flip-flop circuit, CS, CR...selection control signal, AL...fault indication signal, A _0put , A _1put ...AND circuit output signal, F ₁ (Q)
...JK flip-flop circuit output Q, F ₂ ()...
Output of RS flip-flop circuit.

Claims (1)

[Claims] 1. A first selection circuit SL ₁ that receives output signals from two signal sources SG ₀ and SG ₁ and selects one of them; Two signal source failure monitoring circuits AL ₀ ,
AL ₁ , a second selection circuit SL ₁ which receives the output signal of this fault monitoring circuit as input and selects one of them in conjunction with the first selection circuit, and holds external selection control signals CS and CR. A selection signal SS is given to the above two selection circuits in accordance with the selection control signal, and when a signal indicating a fault appears at the output of the second selection circuit _SL1 , the selection signal (SS) is applied. Reversing holding circuit
In a system selection circuit comprising F ₁ , F ₂ , A ₁ , B, and D, when the selection signal (SS) is inverted by the selection control signals CS and CR from the outside, the second selection circuit A system selection circuit comprising logic circuit means for automatically inverting the selection signal SS again when a signal indicating a failure appears at the output of SL ₁ . 2 The logic circuit means is the second selection circuit.
The system selection circuit according to claim 1, which is an AND gate circuit A ₀ inserted into the output path of SL ₀ and using an inverted signal of the selection control signal from the outside as a gate signal.