JPH0348710B2 - - Google Patents

Description

[Detailed description of the invention] [Field of application of the invention]

The present invention relates to a television signal processing circuit, and more particularly, to a signal processing circuit suitable for converting a television signal into a television signal that provides better image quality without causing eye fatigue.

[Background of the invention]

Current standard television systems employ interlaced scanning to reduce the required frequency band. As a result, flickering appears in parts of the screen that change rapidly vertically. The reason why flickering occurs will be explained using FIG. In FIG. 1, scanning line group 1 of the first field
are sequentially scanned, and then scanning line group 2 of the second field located in the middle of scanning line group 1 is sequentially scanned,
Further, scanning is performed such that the scanning line group 1 of the first field is scanned. Therefore, if the screen changes abruptly in the vertical direction, for example from black at the top to white at the bottom, as shown in Figure 1, the transition from black in the first field to white. The locations of the change 3 from black to white in the second field and the change 4 from black to white in the second field are shifted by one scanning line interval. Therefore, the location of the change in black and white moves up and down with the frame period, which causes a flicker to appear in areas of the screen where there is a sudden vertical change. The above flickering does not bother you much on normal screens, but on screens where many horizontal lines are arranged regularly or near-horizontal lines are concentrated at one point,
I'm very curious. It also causes eye fatigue when viewing television images for a long time.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to realize television signal processing using a simple circuit to obtain a flickering-free television signal from a television signal employing interlaced scanning.

[Summary of the invention]

In order to achieve the above object, the present invention provides a television that converts an interlaced input television signal in which one frame consists of two fields into a line sequential scanning signal whose frame frequency is twice the frame frequency of the input television signal. In the signal processing circuit, a first delay circuit that delays the input television signal by one field, a second delay circuit that delays the input television signal by two fields, and an output signal of the first delay circuit is in the first field. outputs the input television signal and the output signal of the first delay circuit as a first television signal and a second television signal, respectively, and when the output signal of the first delay circuit is in the second field, the output signal of the first delay circuit is a first switch circuit that outputs the output signal and the output signal of the second delay circuit as the first television signal and the second television signal, respectively; and a storage capacity of at least half the pixels of one scanning line of the first television signal. a first memory circuit capable of making write speed and read speed independent; a second memory circuit having a storage capacity of half the pixels of at least one scanning line of the second television signal and capable of making write speed and read speed independent; A second switch circuit is provided which alternately switches the output signals of the first memory circuit and the second memory circuit on a scanning line basis and converts them into the line sequential scanning signal. In the following embodiments, a 2:1 interlacing case, which is currently commonly used, will be described, but the present invention can also be realized in an n (an integer greater than or equal to n2):1 case.

[Embodiments of the invention]

FIG. 2 is a block diagram showing the configuration of a portion that converts a line-sequentially scanned image signal, which is the output of a transmitting-side imaging device, into a 2:1 interlaced television signal in the television signal processing system according to the present invention. It is. Three primary color signals 101, 102, and 103 from an imaging device that does not perform interlaced scanning, that is, scans the frame sequentially from top to bottom, are processed by a generally known matrix circuit 104 into a luminance signal 105, two color signals 106, and 107. Signals 105, 106 and 107 are sent to buffer memory circuits 108, 10 with a capacity for one field.
9 and 110, respectively. Buffer memory circuits 108, 109 and 110 are
Timing generation circuit 112 by synchronization signal 111
Every other scanning line is read out to outputs 114, 115, and 116 according to a timing signal 113 generated from the scanning line 113, and is converted into an interlaced scanning signal. Outputs 115 and 116 corresponding to two color signals
is applied to a generally known modulation circuit 117 and converted into a carrier color signal 118. The output 114 corresponding to the luminance signal and the carrier color signal 118 are summed by a summing circuit 119 to form a composite color television signal 120. That is, 525 sequentially scanned signals every 1/30 seconds are sent to the buffer memory circuit, 108, 1
09,110, and since every other scanning line is read out, 262.5 signals are read out in 1/60 second to obtain an image signal for 1 field, and then the next 1/60th of a second is recorded.
The remaining 262.5 lines are read out in 60 seconds and converted into one field of signals. By repeating this process, an interlaced signal similar to a normal television signal is obtained. In FIG. 2, even if the order of the matrix circuit 104 and the one-field buffer memory circuits 108, 109, and 110 is reversed, the prescribed operation will still occur, but since the band of the three buffer memory circuits must be made the same as that of the luminance signal, the circuit The scale becomes larger. FIG. 3 shows a color television signal generated by the conversion circuit shown in FIG. 2, which is subjected to interlaced scanning, and which is separated into a luminance signal and a chrominance signal by a known luminance and chrominance signal separation circuit, and then is not subjected to interlaced scanning. 1 is a diagram illustrating an embodiment of a conversion circuit of the present invention for conversion to a (progressive scan) signal; FIG. In FIG. 3, the input signal 201 consists of two 1
By field delay circuits 202 and 203,
A signal 204 is delayed by one field, and a signal 205 is delayed by two fields. The input signal 201 and the signal 204 delayed by one field are sent to the switch circuit 2.
06, and the signal 204 delayed by 1 field and the signal 2 delayed by 2 fields.
05 are two inputs of the switch circuit 207. Switch circuits 206 and 207 are controlled by a vertical synchronization signal 208, and when the one-field delayed signal is present in the first field, the input signals 201 and one-field delayed signal 204 are output to outputs 209 and 210, respectively. Connecting. Further, when the signal 204 delayed by one field is present in the second field, the signal 204 delayed by one field and the signal 205 delayed by two fields are outputted to outputs 209 and 210, respectively. Therefore, the signals of the second field and the first field of the same frame always appear at the outputs 209 and 210. Outputs 209 and 210 are the scanning line buffer memory circuit 2.
13 and 215 and a switch circuit 224, it is converted into a signal that does not undergo interlaced scanning. The signal conversion operation of the receiving section will be explained using the signal conversion circuit shown in FIG. 4 and the waveform diagram shown in FIG. 5. FIG. 4 shows the switch 20 in FIG. 2 for convenience of explanation.
6,207 switch is in the upper position. (Things that are the same as those in Figure 2 are given the same numbers). As mentioned above, the signals 209 and 210 are generated from the second field and the first field in the same frame, respectively, and depending on the relationship between the number of scanning lines and the field period, these are as shown in FIG.
With a phase difference of 180 degrees, adjacent scanning lines exist at the same time. Both of the buffer memory circuits 213 and 215 are memory circuits that have a memory capacity of half the pixels of one scanning line, and are capable of independent writing speed and reading speed.
It consists of semiconductor random access memory integrated circuits, magnetic core random access memory devices, etc. The reason why a storage capacity of 0.5 scanning lines is sufficient is that after reading, the remaining portions can be read sequentially. Therefore, if a storage capacity for one scanning line is provided, there is no need to write after reading, and the control circuit for the buffer storage circuits 213 and 215 becomes simpler. In order to drive these buffer memory circuits 213, 215 and switch circuit 224, the television signal 2
A synchronization signal separation circuit 226 separates a horizontal synchronization signal 227 from the horizontal synchronization signal 227, and a clock generation circuit 228 generates a clock signal 2 synchronized with the horizontal synchronization signal.
29 and performs write control. Also, reading is performed at twice the speed of the clock signal. Further, a multiplier 230 generates a synchronization signal 231 having half the period of the horizontal synchronization signal from the separated horizontal synchronization signal, and controls the switch circuit 224. Therefore, the television signals 201 and 204
0.5 The scanning line buffer memory circuits 213 and 215 are loaded to the center of the scanning line, and the waveform 21 in FIG. 5 is output to the outputs 213' and 215', respectively.
3' (broken line) and 215' (solid line) at twice the speed, and using the switch circuit 224, the outputs 213' and 21 are read at half the horizontal period.
If 5' is alternately switched and output, the waveform 225
As shown in FIG. 2, a converted television signal 225 is obtained without performing interlaced scanning in which one field is treated as one new frame. Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above embodiments, and may be applied only to the luminance component of a television signal or the low frequency portion of the luminance component, as long as image quality permits. are also included in the present invention. Further, although the embodiments have been described with respect to a 2:1 interlaced television signal, the present invention generally also applies to n:1 interlaced television signals. In this case, in the conversion circuit on the transmitting side, (n-
1) Requires a buffer memory circuit for each field,
On the receiving side, 2(n-1) field delay circuits are required. Furthermore, although the circuit of the present invention has been explained without distinguishing between analog processing and digital processing, when performing processing that involves digital processing and sampling, an AD conversion circuit, a DA conversion circuit, and a filtering circuit are required. . However, how to use these circuits is common knowledge for engineers in the related fields, so explanations are omitted.

【Effect of the invention】

The present invention can simplify a signal conversion circuit that converts the output of a progressive scanning imaging device into an interlaced signal and reproduces the transmitted signal as a progressive scanning television signal in a receiving section.

[Brief explanation of drawings]

Figure 1 is a diagram explaining conventional interlaced scanning;
The figure is a circuit configuration diagram of the transmitting side in the television signal processing system according to the present invention, Figure 3 is a diagram showing an embodiment of the signal conversion circuit of the present invention on the receiving side, and Figure 4 is the signal conversion shown in Figure 3 above. The circuit configuration diagram, FIG. 5, is a waveform diagram showing the operation of FIG. 3. 104...Matrix circuit, 108, 109,
110... Buffer memory circuit, 112... Timing generation circuit, 117... Modulation circuit, 202, 203... Field delay circuit, 213, 215... Buffer memory circuit.

Claims (1)

[Claims] 1. In a television signal processing circuit that converts an interlaced input television signal in which one frame consists of two fields into a line sequential scanning signal whose frame frequency is twice the frame frequency of the input television signal, the input television signal is a first delay circuit that delays the input television signal by two fields; and a second delay circuit that delays the input television signal by two fields, and when the output signal of the first delay circuit is in the first field, the input television signal and the first delay circuit output signal to the first
When the output signal of the first delay circuit is in the second field, the output signal of the first delay circuit and the output signal of the second delay circuit are output as the first television signal and the second television signal, respectively. and a first switch circuit that outputs a second television signal; a first storage circuit that has a storage capacity for at least half the pixels of one scanning line of the first television signal and is capable of independent writing speed and reading speed; a second memory circuit having a storage capacity of at least half the pixel of one scanning line of a television signal and capable of independent writing speed and reading speed, and output signals of the first memory circuit and the second memory circuit for each scanning line. A television signal processing circuit comprising a second switch circuit which alternately switches and converts into the line sequential scanning signal.