JPH0349231B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a solid-state imaging device that can prevent flickering in the solid-state imaging device.

[Background of the invention]

Figure 1 is a principle diagram of a conventional MOS type two-dimensional solid-state image pickup device. MOS type FET 2 for readout switch (hereinafter abbreviated as vertical switch MOST), MOS type FET3 for horizontal readout switch (hereinafter abbreviated as horizontal switch MOST), and shift register 4 of the vertical scanning circuit for switching each switch in an orderly manner. and a shift register 5 of the horizontal scanning circuit, 6 is a vertical gate, 7 is a vertical output line, 8, 1
6, 17, 18, 19 are horizontal gates, 9 and 1
0 is a horizontal output line connected to the output terminal. The vertical and horizontal switching MOS type FETs 2 and 3 have their gate voltages controlled by a shift register to obtain switch operation.

Incidentally, in order to improve vertical resolution (resolution) in such an imaging device, a signal reading method called an interlace method has conventionally been adopted. For example, the vertical scanning line 6 is divided into V ₁ , V ₂ ..., V _i , V _i+1 ..., V _o from the bottom of the figure.
When numbered like this, first, in the first field period, V ₁ +V ₂ , V ₃ +V ₄ , V ₅ +V ₆ ..., V _i-1 +
Read out the signal as V _i ..., and then
In the field period of V ₁ , V ₂ +V ₃ , V ₄ +V ₅ ,
..., V _i +V _i+1 ..., and so on.

In FIG. 1, numeral 11 is a circuit for switching the timing of the output pulse of the vertical shift register 4 using fields (hereinafter referred to as F ₁ and F ₂ ). A conventional circuit is, for example, as shown in FIG. In this figure, during the period of the first field _F1 , pulses are ignited to the vertical gates in the order of A+B, C+D, E+F, . . . and signals are read out. In the next field F ₂ , A, B+C,
Pulses D+E, . . . are applied, signals are read out, and signal reading is performed using the interlaced method. The timing of each pulse in FIG. 2 is shown in FIG. 3.

However, it has been discovered that with this reading method, the DC level of the video signal voltage changes each time the field changes, which appears as a flicker on the video screen called a flicker phenomenon. First, the mechanism of occurrence of the flickering phenomenon will be explained below with reference to FIGS. 4 and 5. FIG. 4 shows the photodiode section of FIG. 1. 30, 31, in the figure
32 is a vertical gate, 41 and 42 are coupling capacitances, 43
is a photodiode, 44 is a vertical switch MOST,
46 and 47 are vertical output lines, to which a video bias _VV is externally applied. Now, focusing on the potential V _sc of the photodiode 43, when the potential of the vertical gate C31 becomes high level, V _sc becomes almost equal to the video bias V _V (reset).
However, when the potential of C becomes low level, _Vsc decreases due to the coupling capacitance that exists parasitically between the vertical gate and the photodiode. The magnitude of the coupling capacitance varies depending on the field, and FIG. 5 shows the situation and pulse timing.

In FIG. 5, vertical gates C31 and D32 are selected at the same timing in a field where pulse F ₁ is at a high level, and B30 and C31 are selected at the same time in a field where pulse F ₂ is at a high level. Now, when we focus on V _SC , in the _F1 field, when the vertical gate of C goes from high level to low level (timings shown from 53 to 55), B
Since the vertical gate of remains at a low level, only C _pcI (41 in the figure) is effective as a coupling capacitance, and as shown at 51 in Figure 5, V _sc decreases (ΔV _s1 ).
is small. On the other hand, in the field of F ₂ , when the vertical gate of C goes from high level to low level (54
), the vertical gate of B also goes from high level to low level at the same time, so both C _pC1 41 and C _pB2 42 are effective as coupling capacitances, and V _sc becomes F ₁
(ΔV _s2 )
(Figure 5 52).

The drop in V _sc is the drop due to the optical signal 56,
Since it is superimposed on 57 and output, it is equivalently ΔV _s2
A signal of -ΔV _s1 appears to appear and disappear in each field, and appears as flickering (flicker development) in each field on the video screen, especially when the signal is small. For this reason, especially when the device is used under low illuminance, the flickering caused by this flickering phenomenon makes the screen extremely difficult to see, and the characteristics of the solid-state video device are significantly degraded.

[Purpose of the invention]

An object of the present invention is to provide a reading method that does not cause the flicker phenomenon in the solid-state imaging device of the two-line simultaneous reading method, and thereby provides a high-sensitivity image sensor capable of obtaining high-quality images even under low illuminance. This is to realize a solid-state imaging device.

[Summary of the invention]

In order to achieve the above object, a two-line simultaneous readout type solid-state imaging device according to the present invention provides
Among the vertical gate lines, turn off the gate line that has coupling capacitance with only one vertical gate line first.
The gist of the present invention is to have two vertical gate lines and a buffer circuit between the gate lines and the interlacing circuit, which later turns off the gate line having a coupling capacitance.

[Embodiments of the invention]

Next, the present invention will be explained with reference to Examples.

FIG. 6 is a circuit block diagram showing one embodiment of the solid-state imaging device according to the present invention, and numeral 101 in the figure is a novel buffer circuit. FIG. 7 shows an example of the buffer circuit described above, and FIG. 8 shows an example of a timing chart of the buffer circuit shown in FIG.

In FIG. 7, 121 is a block indicating a vertical shift register, columns 122 to 131 are transistors for field switching switches that perform interlace operation, 132 and 133 are transmission lines to which field switching pulses F ₁ and F ₂ are applied, respectively;
Columns 166 to 166 are vertical gates, 147 and 148 are transmission lines that apply pulses P ₁ and P ₂ to the vertical gates, and columns 141 to 146 are P 1 or P ₂ .
Switch transistor for sequentially switching P ₂ , 17
0 is a boost strap capacity, 167 and 168 are transmission lines that ignite pulses P ₃ and P ₄ to completely turn off the voltage of the vertical gate, and 151 to 1
Column 56 is transistors controlled by P ₃ and P ₄ .

The operation of the buffer circuit shown in FIG. 7 will be explained using an example of the timing chart shown in FIG.

The corresponding switches 122 to 131 are selected by field selection pulses F ₁ and F ₂ . for example
When F ₂ is “ON” (high level), 124 and 12
The pairs 5, 128 and 129... are selected. This corresponds to the fact that B and C, D and E, . . . are selected as pairs as vertical gates. When F ₁ is “ON”, 122 and 123, 126 and 1
The pairs 27, 130, and 131 are selected, which corresponds to the vertical gates A and B, C and D, etc. being selected as pairs, respectively. That is, F ₁ , F ₂
interlaced operation is possible.

Next, for example, when V ₂ is “ON” and F ₂ is “ON”, when pulses P ₁ and P ₂ are turned “ON”, the corresponding gate lines 162B and 163C are turned “ON” (the eighth Figure time _t1 ). Incidentally, at this time, if there is a bootstrap capacitor 170 as shown in _{FIG .} You can raise the level.

After reading the photodiode signal to the vertical signal line, _P1 is turned "OFF" (low level) and _P3 is turned "ON", thereby turning the vertical gate line 162B "OFF" (time _t2 ). After B is turned "OFF", _P2 is turned "OFF" and _P4 is turned "ON", and C is turned "OFF".

In other words, if the buffer circuit shown in FIG. 7 is used to set the timing of P ₁ - P ₄ as shown in FIG. 8, for example, when vertical gates B and C are selected, B will be placed before C. It can be turned “OFF”.
This also applies when each pair of D and E, . . . is selected. In addition, in the field where F ₁ is "ON", A and B, C and D are selected, but in this case as well, as shown in Figure 8, P ₁ and P ₂ , P ₃ and
By exchanging the timing of _P4 respectively,
“OFF” for A before B, C before D, etc.
Can be done.

Here, to explain using FIG. 4, for example, after B and C are selected and turned "ON", if B is turned "OFF" first and then C is turned "OFF", then B Since the transistor 44 is still in a conductive state when V is turned "OFF", the potential of the _photodiode 43 V _sc
is not affected and vertical gate line 31C is “OFF”
When , the potential only decreases due to the coupling capacitance C _pc1 . Therefore, the field changes (F ₁ is “ON”) and C and D are selected at the same time.
Since the potential fluctuations of V _sc are the same when turning "OFF", there is no difference in the amount of field fluctuation, and no flicker occurs. That is, according to the embodiments shown in FIGS. 7 and 8, it is possible to realize a solid-state imaging device that is free from flicker and can read out two lines simultaneously. Incidentally, the change in V _sc during the above operation is also shown in FIG. Further, FIG. 8 shows (a) the driving timing of one example of the buffer circuit shown in FIG. 7.
In FIG. 8, the timing shift when turning "OFF" is provided by switching the timing of drive pulses P ₁ , P ₃ , P ₂ , and P ₄ for each field.

It goes without saying that the buffer circuit shown in FIG. 7 is not necessarily limited to this.
For example, the drive pulse transmission line for _P1 and _P2 may be shared. In that case, after turning V ₁ , V ₂ ... (vertical register output) from "ON" to "OFF", adjust the timing to turn P ₃ and P ₄ pulses "ON", as shown in Figure 8. Outputs (A, B, . . . ) as shown in b are obtained. Conversely, P ₃ and P ₄ may be made common; in this case,
The pulses of P ₃ and P ₄ may be synchronized with the later timing of turning "OFF" among P ₁ and P ₂ .

〔Effect of the invention〕

As described above, the essence of the present invention is that in a two-wire simultaneous readout type solid-state imaging device, the vertical gate of the photodiode that has a coupling capacitance with only one of the two selected vertical gates is first turned OFF. ,
By later turning off the vertical gate of the photodiode surrounded by the two vertical gates and having coupling capacitance on both sides, the flicker phenomenon caused by the unbalance of the coupling capacitance for each field can be prevented and reduced. The purpose is to realize a highly sensitive solid-state imaging device that can obtain high-quality images even under illuminance, and the drive circuit and pulse train are not necessarily limited to the above example.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the principle of a conventional MOS two-dimensional solid-state imaging device, Figure 2 is a circuit diagram of the switching circuit shown in Figure 1, and Figure 3 is the timing of each pulse appearing in the circuit shown in Figure 2. FIG. 4 and FIG. 5 are diagrams showing the generation mechanism of the flicker phenomenon, FIG. 6 is a circuit block diagram of the solid-state image sensor according to the present invention, and FIG. 7 is a diagram of the buffer circuit in FIG. 6. The circuit diagram, Figure 8, shows the timing and timing of the circuit shown in Figure 7.
It's a chat. 1...Photodiode, 2...Vertical switch
MOST, 3...Horizontal switch MOST, 4, 5...
...Shift register, 6...Vertical gate, 7...Vertical output line, 8, 16, 17, 18, 19...Horizontal gate, 9, 10...Horizontal output line, 11...Timing switching circuit, 30, 31 , 32... Vertical gate, 41, 42... Coupling capacitance, 43... Photodiode, 44... Vertical switch MOST, 46,
47... Vertical output line, 101... Buffer circuit,
121...Vertical shift register, 122-13
1... Field changeover switch transistor, 132, 133, 147, 148, 167,
168...Transmission line, 141-146...Switch transistor, 151-156...Transistor, 161-166...Vertical gate, 170...
...Boostrap capacity.

Claims (1)

[Scope of Claims] 1. A plurality of photodiodes arranged two-dimensionally on the same semiconductor substrate, a group of horizontal switch elements and a group of vertical switch elements that select the photodiodes, and a group of horizontal and vertical switch elements for each of the horizontal and vertical switch elements. A solid-state imaging device that has a horizontal scanning circuit and a vertical scanning circuit for applying scanning pulses, and has an interlace circuit that selects a plurality of vertical scanning lines by a switch element and simultaneously performs horizontal scanning of a plurality of scanning lines. In the apparatus, a photodiode that is not sandwiched between the plurality of vertical scanning lines selected from among the photodiodes selected by the plurality of vertical scanning lines and the vertical switch elements connected to each of the plurality of vertical scanning lines is selected. A solid-state imaging device comprising a buffer circuit that deselects a vertical scanning line before a vertical scanning line that selects a sandwiched photodiode. 2. The buffer circuit receives the selection signal from the interlace circuit as a gate input, and is provided for each vertical scanning line to which multi-phase pulses are applied to drive the vertical scanning line in synchronization with the output pulses of the vertical scanning circuit. A gate circuit including at least a switch transistor, and means for returning the vertical scanning line from a selected state to a non-selected state at at least two or more different times when the plurality of phase pulses are generated. The solid-state imaging device according to item 1. 3. The solid-state imaging device according to claim 2, wherein the switch transistor is an insulated gate field effect transistor, and a capacitance contributing to a bootstrap effect is provided between the gate and source of the transistor. Device. 4. The switch transistor according to claim 3, wherein the drain (source) is connected to a pulse input terminal for driving the vertical scanning line, and the source (drain) is connected to the vertical scanning line. Solid-state imaging device. 5 Among the switch transistors mentioned above, the drains (sources) of the switch transistors connected to the odd-numbered vertical scanning lines are connected to the first drive pulse input terminal, and the drains (sources) of the switch transistors connected to the even-numbered vertical scanning lines are connected to the first drive pulse input terminal. (source) is the second
Claim 4, wherein the first and second drive pulses change the vertical scanning line from a selected state to a non-selected state at different times. Solid-state imaging device. 6 The source (drain) of the switch transistor is connected to the drain (source) of a reset insulated gate field effect transistor whose gate is connected to a common line and whose source (drain) is grounded, and which is connected to the first common line. 5. The solid-state imaging device according to claim 4, wherein a reset pulse is applied to the solid-state imaging device. 7 Among the switch transistors mentioned above, the sources (drains) of the switch transistors connected to the odd-numbered vertical scanning lines have a first reset circuit whose gate is connected to the first common line and whose source (drain) is grounded. The drain (source) of the insulated gate field effect transistor is connected to the source (drain) of the gate element connected to the even-numbered vertical scanning line, the gate is connected to the second common line, and the source (drain) is connected to the second common line. The drain (source) of the second insulated gate field effect transistor for reset is connected to the
5. The solid-state imaging device according to claim 4, wherein the first and second reset pulses are applied to the common lines, respectively.