JPH034935B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a control circuit for a microprocessor suitable for high integration.

Conventional Structures and Problems With the recent improvements in semiconductor integrated circuit technology, high-performance microprocessors have become extremely inexpensive. First, the basic operation of a microprocessor will be explained using the most common structure (FIG. 1). In FIG. 1a, 1 is a control circuit that controls the entire operation of the microprocessor, 2 is a register file, and 3 is a control circuit that controls the entire operation of the microprocessor.
is an ALU that performs arithmetic and logical operations, 4 and 5 are
A latch 6 takes in data input to the ALU 3 from the data bus and temporarily stores it, and a flag register 6 stores a status flag (for example, carry, overflow, sign, etc.) of the operation result of the ALU 3.

Here, we will explain the most basic inter-register operation as an example. For example, when the machine code corresponding to ADD R0, R1 is applied to the control circuit 1, the control circuit 1 sends it to the register file 2.
Register address information corresponding to R0 and R1
Output through the REGA signal line. Further, the control circuit 1 outputs ALU function information corresponding to ADD to the ALU 3 through the ALUF signal line.
The data stored in the register file 2 selected by the register address information is output to the data bus, and is input to the input data latch 4 of the ALU 3.
5 is temporarily stored. The ALU 3 operates on the data in the latches 4 and 5 according to the ALU function code, outputs the operation result to one bus ABus, and rewrites one of the register files 2. Also
ALU3 outputs the calculation result and at the same time carries
An arithmetic state flag signal ALUS such as overcrow or sine is created and registered in the flag register 6.
This flag is later referenced by instructions such as conditional branching.

The first diagram shows the above operation in a timing diagram.
Figure b. Reading of register file 2 is at timing T ₁ , data transfer to ALU input data latches 4 and 5 is at timing T ₂ , ALU operation is at timings T ₂ to T ₃ , and register file 2 of the operation result is read.
Transfer and writing to is performed at timing _T4 .

Conventionally, when designing such microprocessors, attention has been paid to minimizing the number of active elements (transistors), primarily from the perspective of reducing power consumption, so wiring has tended to be neglected. However, as high integration has dramatically improved, it has become possible to increase the number of built-in transistors, but on the other hand, the proportion of the wiring area in the total chip area has also increased, and the parasitic capacitance that exists in the wiring has increased. Many problems related to wiring have become prominent, such as the power consumption of drive transistors that cannot be ignored. Also in the explanation regarding FIG. 1 above, the control line output from the control circuit 1
Since REGA and ALUF must be supplied to the register file 2 and ALU 3 located at separate locations within the chip, this causes an increase in the wiring area.

Recently, in order to eliminate the above-mentioned drawbacks, a method of transmitting control signals in a time-division manner has been proposed. This method will be explained based on FIGS. 2a and 2b. Third
In the figure, 7 is a latch for temporarily storing register address information, and 8 is a latch for temporarily storing ALU function information. The control circuit 1 outputs register address information at timings T ₄ and T ₁ and ALU function information at timings T ₂ and T ₃ to the control bus in a time-division manner. The control bus is taken into latch 7 by register address latch enable signal RALE near register file 2,
Set as register address signal REGA. Also ALU
At around 3, the control bus is taken into latch 8 by ALU function latch enable signal AFLE,
Let the ALU function signal be ALUF. The subsequent operations are the same as those shown in FIG.

However, even in this method, a separate status flag signal line FLG is required for the control circuit 1 to refer to the information in the flag register 6 that latches the arithmetic status flag signal ALUS of the ALU, which becomes an obstacle to reducing the wiring area. There is.

OBJECTS OF THE INVENTION The present invention provides a microprocessor architecture that eliminates the obstacles to reducing the number of wiring lines as described above, further reduces the number of wiring lines, and is adapted to high integration.

Structure of the Invention In order to achieve the above object, the present invention makes the control bus that connects the control circuit and each wave control circuit bidirectional,
The gist of this system is to transmit control information from a control circuit to a controlled circuit, and state information from a controlled circuit to a control circuit, using temporarily stored register address information as input. At the same time, the data stored in the two registers specified by the data bus is outputted to each of the two data buses, and a read status flag such as a parity error is created. Furthermore, at different timings, the signal on one data bus is transferred to the register. A 2-port readable/writable register file and temporarily stored ALU function information are used as control inputs.
an ALU that calculates two pieces of data that temporarily store data on one data bus according to the control input, outputs the results to one bus again, and creates an operation status flag at the same time; Register address information is sent at timing 1, the register read status flag signal is sent back at timing 3, ALU function information is sent to the ALU at timing 2, and calculation is performed at timing 4. The register address information and ALU function information are transmitted to the control/status bus to which the status flag information is returned, and the register address information and ALU function information are transmitted to the control/status bus at the first and second timings, respectively, and at the third and fourth timings. The control circuit has a built-in latch that takes in the register read status flag information and the calculation status flag information on the control/status bus and temporarily stores them, and has a control circuit that has the function of changing the flow of control depending on the contents. This is what I did.

Description of Embodiments Embodiments of the present invention will be described above based on the drawings. FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a time chart of this embodiment.The operation of this embodiment will be explained using these figures.

9 is a register address information output buffer, 10
11 is a register read state flag latch, 12 is an arithmetic state flag latch, 13 is a register read state flag output buffer, and 14 is an arithmetic state flag output buffer.

On the control/status bus, buffer 9 is opened by the register address output control line RAO at timing _T1 , and register address information is sent to the control/status bus.
At _T2 , the buffer 10 is opened by the ALU function output control line AFO and the ALU function information is output. The operation of taking these signals into the register address information latch 7 and ALU function latch 8 is the same as that shown in FIG. The register file 2 outputs data to the data bus and at the same time creates a read status flag signal REGS such as a parity error. This REGS is timing T ₃
The register read status flag is output to the control/status bus through the buffer 13 opened by the output control line RSO. This information is temporarily stored in the register read state flag latch 11 by the register read state flag latch enable signal RSLE, and is used by the control circuit 1 for conditional branching and the like. The ALU 3 calculates the input data, outputs the calculation result to the ABus of one bus, and simultaneously creates the calculation status flag signal ALUS. This ALUS is output to the control/status bus through the buffer 14 opened by the arithmetic status flag output control line ASO at timing _T4 . This information is temporarily stored in the arithmetic state flag latch 12 by the arithmetic state flag latch enable signal ASLE, and is used by the control circuit 1 for conditional branching and the like.

As described above, the number of control signal lines and status signal lines connecting the control circuit 1 and each controlled circuit can be significantly reduced.

Effects of the Invention According to the present invention, the following effects are brought about.

(i) By connecting the control circuit and the controlled circuit with a bidirectional control/status bus, the number of wiring lines can be significantly reduced, making it possible to greatly improve the degree of integration. Furthermore, by reducing the number of wiring lines, the power consumed by the drive transistor can also be reduced.

(ii) By placing the control signal and the resulting state information within the control circuit block, operations such as conditional branching can be sped up.

(iii) By creating post-operation status information for all controlled circuits and sending it back to the control circuit, various control circuits can be designed with a uniform concept, which has the advantage of simplifying the overall architecture. Motsu.

[Brief explanation of drawings]

Figures 1a and b are block diagrams and timing diagrams explaining the basic structure of a microprocessor, Figure 2 is a block diagram and timing diagram explaining a conventional example with slight improvements, and Figure 3 is the main FIG. 4 is a block diagram illustrating one embodiment of the basic structure of a microprocessor according to the invention, and FIG. 4 is a timing diagram illustrating the operation of the embodiment shown in FIG. 1...Control circuit, 2...Register file, 3
...Arithmetic logic circuit (ALU), 4, 5...
ALU input data latch, 6...flag register,
7... Register address information latch, 8...
ALU function latch, 9...Register address information output buffer, 10...ALU function output buffer, 11...Register read status flag latch, 12...Arithmetic status flag latch, 13...Register read status flag output buffer, 14... ...Calculation status flag output buffer.

Claims (1)

[Claims] 1 Using the temporarily stored register address information as input, the data stored in the two specified registers is output to the two data buses, and at the same time, read status flags such as parity errors are created, and different In terms of timing, there is a 2-port readable/writable register file that takes signals on one data bus into the register,
The temporarily stored ALU function information is used as a control input, and the two temporarily stored data on the two data buses are calculated according to the control input, and the result is output to one bus again, and at the same time the calculation status flag is set. Register address information is transmitted to the arithmetic and logic operation circuit (ALU) to be created and the register file at a first timing, the register read status flag signal is returned at a third timing, and the arithmetic and logic operation is performed. A control/status bus to which ALU function information is sent to the circuit at a second timing and arithmetic status flag information is returned at a fourth timing; and a control/status bus at the first and second timings. A built-in latch is provided to transmit the register address information and ALU function information, respectively, and to take in the register read status flag information and calculation status flag information on the control/status bus at third and fourth timings, and to temporarily store them respectively. and a control circuit having a function of changing the flow of control based on its contents.