JPH034938B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a storage control method for a computer, in particular, a method for receiving information on the access time of a storage element from a main memory so that the access time of the storage element can be easily changed. The present invention relates to the above-mentioned method.

In the conventional storage control method, after sending an access request to a predetermined storage unit (bank) of a storage device, the time until the next access request to the same bank can be sent, that is, the time required for sending an access request to the same bank, that is, A time corresponding to the access time is fixed in the storage control device, and after an access request is sent to a predetermined bank, control is performed to suppress sending of the next access request to the same bank for the above period of time. It was starting to happen. For this reason, when the access time of an element in the main memory device changes or the type of the element itself changes, in order to change the value of the access request sending suppression time,
There was a problem in that it was necessary to change the logic of the storage control device and set new values, and when changing elements, both the main storage device and the storage control device had to be changed. .

This invention was made to solve the above problems, and its purpose is to indicate the number of bank blockage clocks when a plurality of access request control devices access a storage device consisting of a plurality of banks. By sending level signals from the main memory device to the storage control device and controlling the sending of access requests for several clock hours, changes in the access time of elements in the main memory device or changes in the element itself can be controlled. An object of the present invention is to provide a storage control method that can easily change the time period for suppressing sending of access requests in response to changes.

That is, in the storage control method of the present invention, when a plurality of access request control devices sequentially access a storage device consisting of a plurality of banks at high speed, the access request processing devices are different depending on the type of access request. When a signal indicating the number of bank blockage clocks (bank blockage time signal) is received from the main memory and the access request received from the access request control device is sent to the main memory, a subsequent bank blockage state of the main memory is simulated. , storage control that controls not to send the next access request to the requested bank for the number of clocks indicated by the bank closure time signal, depending on the type of access request sent to the main storage device; It is related to the method.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the main parts of a computer system, which includes an arithmetic unit 10, a plurality of (four in this example) access request control devices 20, 21,
22, 23, a storage control device 30, and a storage device 40, and this storage device 40 has a plurality of (in this example, four
4) banks 400, 401, 402, and 403.

FIG. 2 shows an access request control device 20, which has a data buffer 200 and an address generation section 201, and data read from the storage device 40 is stored in the data buffer 200. It's becoming like that. The access request control devices 21 and 22 have the same structure as this device 20, and the access request control device 23 has the same structure as this device 20.
This device 20 is configured to store data from a data buffer to a storage device 40.
It has the same structure as .

FIG. 3 shows a storage control device 30 according to the present invention.
is shown schematically. Access request stack devices 300, 301, 302, and 303 are provided corresponding to the access request control devices 20, 21, 22, and 23, respectively. For example, the access request control device 20
The access request and address information are sent to. Regarding the access request stack device 300, this device stacks sent access requests in the stack 300A in the order in which they were sent, and sends them to the access request processing device 310A in that order. Other access request stack devices 301, 302, and 303 operate in a similar manner. The access request processing device 310 selects any one access request according to the priority order of the access requests received from each access request stack device, and converts the access request into the address information that the access request has. Send to the bank corresponding to . At that time, a number indicating which access request control device the selected access request is from (access request control device number) is set in the shift register circuit 310A. When an access is actually performed, data is read out after, for example, n clocks. The access request processing device 310 includes a shift register circuit 310A.
The access request controller number set in is sequentially shifted and after n clocks, the read data is set in the data register of the access request controller indicated by the access request controller number. Because of this method, there is no possibility that the order of access requests and read data will be out of order.

FIG. 4 shows an embodiment in which access request control devices 20, 21, 22, and 23 according to the present invention access a storage device 40.

The access request control device 20 sends an access request to the access request stack device 300. Other access request control devices 21, 22, 23
Similarly, access requests are sent to the corresponding access request stack devices 301, 302, and 303, respectively. This access request consists of information such as valid bits, address information, and the type of access request. Each access request stacking device stacks the access requests in the order in which they are received and sets them in the access request processing device in the same order. The set signal is created by the control unit (300B in the case of the access request stack device 300). Here, the access request stack device 30
An example of an access request stacked with 0 will be explained.

When control section 300B issues a set signal, the oldest access request stored in stack 300A at that time is set in latches 310B and 311B. The valid bit and address information of the access request are set in latch 310B, and the information on the type of access request is set in latch 311B. Access requests set in latch 310B pass through access request suppression logic 310M, and access requests that are not suppressed here enter priority determination logic 310Q, which will be described below. Similar processing is performed for access requests stacked in other access request stacking devices.

Prioritization logic 310Q prioritizes the access requests sent from each access request stack to select one access request and set it in latch 310F. What is set in latch 310F? These are the valid bit of the selected access request, address information, and the number of the access request stack device to which the access request is sent (access request stack device number). Latch 311B, 311C, 311
D, 311E, the priority determination logic 310Q
The one corresponding to the access request stack device number determined in is selected, and its contents (access request type information) are set in latch 310C.
The access request set in latch 310F is
When the valid bit is "1", the data is sent to the corresponding bank according to the address information. Also, depending on the access request stack device number, the corresponding access request stack device is
A signal is sent out indicating that the access request sent from the access request stack device has been selected. For example, when an access request is set in latch 310F, access request stack device 300
If the access request has been sent from the access request stack device 300, a signal 50 is sent to the access request stack device 300 indicating that the access request sent from the access request stack device has been selected. Upon receiving the signal 50, the control unit 300B of the access request stack device 300 sends the next access request to the access request processing device 310.

The problem here is that the bank to which the access request set in latch 310F is sent is in a state in which the next access request cannot be accepted for the period of time that it is being accessed. This, 1
The period of time during which the next access request cannot be accepted after one access request is sent is called bank closure time. Bank closure time depends on the type of access (“read”, “full write”, “partial write”).
etc.). The main focus of the present invention is to suppress processing of the next access request during this bank closure time.

For convenience of explanation regarding FIG. 4, there are three types of access requests: "read", "full write", and "partial write", and the corresponding bank closure times are 1 clock, 1 clock, and 1 clock, respectively. It is assumed that they are also J Kuroku and K Kurotsu. The storage device 40 stores the bank blockage clock number minus 1, that is,
A level signal 53 (a signal that does not change over time) representing the numerical values of I-1, J-1, and K-1 is sent to the access request processing device 310. signal 33
will be called the bank blockage clock number signal.
The bank blockage clock number signal 53 is normally sent out when the computer system is in operation. This signal 53 enters the counter initial value creation logic 310R. The access request processing device 310 also provides counters 310H, 310J, and 310 that simulate bank closure times corresponding to banks 0, 1, 2, and 3.
K,310L. Information about the type of access request set in latch 310F is set in latch 310G. Assume now that the information set in latch 310G is "read" and the access request set in latch 310F is for bank 0.

The counter initial value creation logic 310R selects I-1 corresponding to "Read" from the bank blockage clock number signal 53, and sets the counters 310H to 310L.
Send to. Based on the address information set in latch 310F, latch 310I in counter 310H corresponding to bank 0 is set to the above value I-1. The counter 310H sends a signal 51 (bank 0 blockage signal A) indicating that "the value of the latch 310I is not 0" to the access request suppression logic 310M, 310N, 310O, 310P.
Send to. Additionally, the latch 310F directly connects the access request suppression logic 310M,
310N, 310O, and 310P, a signal 52 (bank 0 block signal B) indicating that an access request has been sent to bank O is sent for one clock period. Access request suppression logic 310M, 310
N, 310O, 310P are latches 310B, 310P when either signal 51, 52 is "1".
If the access requests set in 10C, 310D, and 310E are for bank 0, they are suppressed and not entered into the priority determining logic 310Q. By doing this, the I clock after the access request set in latch 310F is sent to bank 0 will not cause the next access request to bank 0 to be sent.

FIG. 5 is a time chart for explaining the operation of the system according to the present invention, and in more detail,
Time for the case where access request 1 for bank 0 is set in latches 310B and 311B, access request 2 for bank 0 is set in latches 310C and 311C, and access request 3 for bank 1 is set in latches 310D and 311D. It's a chat.

Priority determination logic 3 at timing TO
It is assumed that access request 1 among access requests 1, 2, and 3 is taken by 10Q. At timing T1, the valid bit and address information of access request 1 are also transferred to latch 310F.
The type of access (eg, "read") for access request 1 is set for latch 310G.
At this timing T1, access request 1 set in latch 310F is sent to bank 0. Since access request 1 is for bank 0, signal 52 remains "1" for one clock.
become. Therefore, at timing T1, access request 2 for bank 0 is suppressed and does not enter priority determining logic 310Q, and only access request 3 enters at this timing. At timing T2, access request 3 is set in latch 310F, and access request 3 is sent to bank 1. From the information set in the latch 310G at timing T1, the counter initial value creation logic 310R
selects the number of bank blocking clocks for ``read'' minus 1 from the bank blocking clock number signal 53 (the number of bank blocking clocks for ``reading'' is, for example, 3), and sets 2 in latch 310I. The value of latch 310I decreases by 1 every clock and becomes 0 at timing T4. Therefore, the signal 51 becomes "1" between two clocks at timings T2 and T3, and the access request 2 for bank 0 does not enter the priority determining logic 310Q. Signal 51 at timing T4
becomes "0", the priority determination logic 310Q
Access request 2 enters into bank 0, is set in latch 310F at timing T5, and is sent to bank 0.

According to the system of the present invention, during a period when a certain bank is blocked by an access request (three clocks in the example of FIG. 5), no next access request is sent to that bank. Here, since the bank blockage clock signal is a level signal consisting of several bits, it is easy to change the signal value. Therefore, the method of the present invention has the advantage that when changing the access time of an element in a storage device, it is only necessary to change the value of a level signal of several bits.

As explained above, according to this invention,
The number of bank blocking clocks corresponding to the type of access request is transmitted from the storage device to the storage control device using a several-bit level signal whose value can be changed arbitrarily. By simply changing the value, the time interval at which access requests to the same bank are sent can be adjusted. Therefore, in response to changes in the access time of memory device elements or changes in the type of elements themselves,
This has the remarkable effect that by simply changing the value of the above-mentioned signal, the control of the storage control device can be changed without changing the logic of the storage control device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a computer system to which the present invention is applied, FIG. 2 is a schematic diagram of an access request control device used in the system of FIG. 1, and FIG. FIG. 4 is a detailed diagram of the storage control system according to the present invention, and FIG. 5 is a time chart for explaining the operation of the system of FIG. 10: Arithmetic device, 20 to 23: Access request control device, 30: Storage control device, 40: Storage device,
400-430: Bank, 300-303: Access request stack device, 310: Access request processing device, 310M-310P: Access request suppression logic, 310Q: Priority determining logic, 310R:
Counter initial value creation logic, 310H to 310L:
Counter 53: Bank blockage clock number signal.

Claims (1)

[Claims] 1 A plurality of access request control devices generate access requests independently of each other, and a storage device consisting of a plurality of storage units that can be accessed independently of each other,
In a storage control method configured to send the access request when each storage unit is accessible, valid bits, address information, and type of access request of the access request sent from each access request control device are set. a plurality of latches in which information is set; a counter that simulates the state of each storage unit based on the information set in the latches;
A means for determining priorities among access requests set in the latch receives information from the storage device about the number of blocking clocks for each storage unit, which varies depending on the type of access request, and blocks the blockage by the number of clocks. A storage control system characterized in that the access request set in the latch by a counter is inhibited from being input to the priority order determining means, and the access request is not sent when each of the storage units is blocked.