JPH035077B2 - - Google Patents
Info
- Publication number
- JPH035077B2 JPH035077B2 JP57027927A JP2792782A JPH035077B2 JP H035077 B2 JPH035077 B2 JP H035077B2 JP 57027927 A JP57027927 A JP 57027927A JP 2792782 A JP2792782 A JP 2792782A JP H035077 B2 JPH035077 B2 JP H035077B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- conductive ink
- pin
- ink
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明はプリント配線基板の表裏両面に形成し
た導電パターンを電気的に接続する方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for electrically connecting conductive patterns formed on both the front and back surfaces of a printed wiring board.
従来より第8図、第10図に示す方法で配線基
板1の貫通孔3に導電インキ4を流し込んで表裏
両導電パターン2,2間を電気的に接続すること
が行なわれている。 Conventionally, conductive ink 4 is poured into the through holes 3 of the wiring board 1 to electrically connect the front and back conductive patterns 2, 2 using the method shown in FIGS. 8 and 10.
第8図の方法は先端に導電インキ4を付着させ
たピン5を基板1の孔3の真上で振動させて導電
インキ4を基板上に滴下するもので、インキは孔
壁を伝つて自重で垂れ落ちることによつて基板の
裏面側に達し、第9図の如く孔の内面及び孔縁に
インキが付着する(特開昭52−139962号)。 In the method shown in Fig. 8, a pin 5 with conductive ink 4 attached to the tip is vibrated just above the hole 3 of the substrate 1, and the conductive ink 4 is dripped onto the substrate, and the ink travels along the hole wall due to its own weight. The ink drips down and reaches the back side of the substrate, and the ink adheres to the inner surface and the edge of the hole as shown in FIG. 9 (Japanese Patent Laid-Open No. 139962/1982).
第10図の方法は先端に導電インキ4を付着さ
せたピン5を基板1の孔3に貫通させ、この状態
でピン5と直交する面内で基板1を振動させ、孔
3の内面及び孔縁にインキを付着させた後、ピン
5を抜くものである(特開昭56−70696号)。 In the method shown in FIG. 10, a pin 5 with conductive ink 4 attached to the tip is passed through a hole 3 of a substrate 1, and in this state, the substrate 1 is vibrated in a plane perpendicular to the pin 5, and the inner surface of the hole 3 and the hole 3 are vibrated. After applying ink to the edge, the pin 5 is removed (Japanese Patent Application Laid-open No. 70696/1983).
ところが、第8図の方法の場合、粘性が高く流
動性の悪い導電インキが自重で垂れ落ちて孔の下
端縁に回り込む迄に時間が掛かり、能率が悪い。 However, in the case of the method shown in FIG. 8, it takes time for the conductive ink with high viscosity and poor fluidity to drip down under its own weight and wrap around the lower edge of the hole, resulting in poor efficiency.
又、第8図の方法は導電インキの自然流下によ
つて孔内面に導電インキを付着させるものであ
り、導電インキの粘性が高いときは、流下に時間
が掛かり、加工能率が低下する。 Further, in the method shown in FIG. 8, the conductive ink is allowed to adhere to the inner surface of the hole by its natural flow, and when the conductive ink has a high viscosity, it takes time for the conductive ink to flow down, reducing processing efficiency.
導電インキの粘性を下げるために、該インキに
含まれる溶剤の添加量を増すと、導電インキの硬
化時にガスの発生量が増えて、インキの充填部に
空〓或はクラツクが発生し、導電性の信頼度が低
下する問題がある。 In order to lower the viscosity of conductive ink, if the amount of solvent added to the ink is increased, the amount of gas generated increases when the conductive ink hardens, creating voids or cracks in the ink-filled area, and reducing the conductivity. There is a problem in which the reliability of sex decreases.
又、第10図の方法の場合、基板1の孔3を貫
通したピン5と孔壁との間の隙間が狭く、導電イ
ンキ4は孔3の上縁部と下縁部に集中し、ピン5
を抜いた後に孔3に残存するインキ量が少なく、
電気導通の信頼性に欠けていた。又、第10図の
方法は、ピンは挿入した基板の孔から必ず抜かね
ばならず、この際に導電インキの塗布層に空気を
巻き込んで、空〓が生じ易い。 In addition, in the case of the method shown in FIG. 10, the gap between the pin 5 passing through the hole 3 of the substrate 1 and the hole wall is narrow, and the conductive ink 4 concentrates on the upper and lower edges of the hole 3, and the conductive ink 4 concentrates on the upper and lower edges of the hole 3. 5
The amount of ink remaining in hole 3 is small after removing the
Electrical continuity was unreliable. Furthermore, in the method shown in FIG. 10, the pin must be removed from the hole in the board into which it has been inserted, and at this time air is likely to be drawn into the conductive ink coating layer, resulting in voids.
更に、ピンに導電インキが繰り返し塗布される
ことによつて、ピンの実効径が大きくなること及
び導電インキを孔縁でしごいて基板に塗布するた
め、孔内面へのインキの塗布量の調整が困難であ
る。 Furthermore, by repeatedly applying conductive ink to the pin, the effective diameter of the pin becomes larger, and because the conductive ink is applied to the substrate by squeezing the conductive ink at the edge of the hole, it is necessary to adjust the amount of ink applied to the inner surface of the hole. is difficult.
本発明は上記実情に鑑み、先端に導電インキ4
を付着させたピン5を上下に往復させて基板1上
の上面の孔縁に複数回接近離間させることによ
り、高能率に且つ信頼性の高い導電パターン間の
接続方法を提供することを目的とする。 In view of the above-mentioned circumstances, the present invention has been developed with conductive ink 4 at the tip.
The purpose is to provide a highly efficient and reliable method of connecting conductive patterns by reciprocating up and down the pin 5 to which it is attached, approaching and separating it from the edge of the hole on the upper surface of the substrate 1 multiple times. do.
以下図面に示す実施例に基づき本発明を具体的
に説明する。 The present invention will be specifically described below based on embodiments shown in the drawings.
第7図は本発明の方法により表裏両導電パター
ン2,2間を形成したプリント配線基板1の要部
断面図である。 FIG. 7 is a sectional view of a main part of a printed wiring board 1 in which both the front and back conductive patterns 2 are formed by the method of the present invention.
プリント配線基板1は表裏両面に導電パターン
2,2を有し、両パターン2,2の対向位置に基
板1を貫通して孔3を開設し、該孔3に導電イン
キ4を充填して固化させている。 The printed wiring board 1 has conductive patterns 2, 2 on both the front and back sides, and a hole 3 is formed through the board 1 at a position opposite to both the patterns 2, 2, and the hole 3 is filled with conductive ink 4 and solidified. I'm letting you do it.
第1図は基板1に導電インキ4を充填する充填
装置50を示しており、上記充填装置50は基板
1の貫通孔3の孔径よりも僅か小径のピン5を孔
3の配列に対応して植設した昇降板51を第1上
下動装置52及び第2上下動装置53に連繋し、
昇降板51の下方に導電インキ4を容れた槽41
を配備している。 FIG. 1 shows a filling device 50 that fills the substrate 1 with conductive ink 4. The filling device 50 has pins 5 with a diameter slightly smaller than the diameter of the through holes 3 of the substrate 1 corresponding to the arrangement of the holes 3. The planted lifting plate 51 is linked to the first vertical movement device 52 and the second vertical movement device 53,
A tank 41 containing conductive ink 4 below the lifting plate 51
is being deployed.
導電インキ4は粘度が25〜50Psの銀ペースト
である。 The conductive ink 4 is a silver paste with a viscosity of 25 to 50 Ps.
次にインキの充填方法を説明する。 Next, the ink filling method will be explained.
充填装置50の第1上下動装置52によつて、
昇降板51を上下に1往復させ、各ピン5の先端
部を導電インキ槽41に漬けて引き上げ、ピン5
の先端部に導電インキ4を付着せしめる(第3
図)。 By the first vertical movement device 52 of the filling device 50,
The lifting plate 51 is moved up and down once, and the tip of each pin 5 is immersed in the conductive ink tank 41 and pulled up.
Conductive ink 4 is applied to the tip of the (third
figure).
次に昇降板51の下方に配線基板1を対向さ
せ、該基板1の貫通孔3とピン5の芯を一致させ
る。 Next, the wiring board 1 is placed opposite to the lower part of the lifting plate 51, and the through holes 3 of the board 1 are aligned with the centers of the pins 5.
上記状態の侭、第2上下動装置52を作動して
ピン5の先端が孔3の上縁に近接する位置に昇降
板51を下降させ、ピン5上の導電インキ4を基
板1の孔縁に転移せしめる(第4図)。 While in the above state, the second vertical movement device 52 is operated to lower the elevating plate 51 to a position where the tip of the pin 5 is close to the upper edge of the hole 3, and the conductive ink 4 on the pin 5 is transferred to the hole edge of the substrate 1. (Figure 4).
実施例では第2上下動装置53のストークは10
mmで、又、上死点位置のピン5と基板1との間隔
も10mmである。 In the embodiment, the stalk of the second vertical movement device 53 is 10
mm, and the distance between the pin 5 at the top dead center position and the board 1 is also 10 mm.
従つてピン5が下降した時、ピン先端と基板1
の上面高さは一致するが、これに限定されること
はなく、ピン上の導電インキ4が基板1に転移出
来るならピン5の下死点は基板上面より僅か上で
も或は孔3に僅か入り込んでも可い。 Therefore, when pin 5 descends, the pin tip and substrate 1
Although the top surface heights are the same, the height is not limited to this. If the conductive ink 4 on the pin can be transferred to the substrate 1, the bottom dead center of the pin 5 may be slightly above the top surface of the substrate or slightly below the hole 3. You can sneak in.
孔縁に導電インキ4が付着したら、直ちにピン
5を上昇させる。 Immediately after the conductive ink 4 adheres to the edge of the hole, the pin 5 is raised.
基板1上のインキ4は表面張力により、ピン5
の穴跡を埋めて孔3の真上にて丸くまとまる(第
5図)。 The ink 4 on the substrate 1 is attached to the pin 5 due to surface tension.
Fill in the hole left and form a circle just above hole 3 (Figure 5).
次に第2上下動装置53によりピン5を1秒間
に2回の割で約6秒間往復動させる。 Next, the pin 5 is reciprocated twice per second for about 6 seconds by the second vertical movement device 53.
前記の様にピン5が孔3の上縁に近接する位置
迄下降することにより、孔縁に跨がつて付着して
いる導電インキ4がピン5によつて孔中に押し込
まれる。 As the pin 5 descends to a position close to the upper edge of the hole 3 as described above, the conductive ink 4 adhering across the edge of the hole is pushed into the hole by the pin 5.
ピン5が上昇すれば、基板上面の孔縁に残存し
ている導電インキ4が表面張力で孔3の軸心側へ
引き込まれる様に丸くまとまる。 When the pin 5 rises, the conductive ink 4 remaining on the edge of the hole on the upper surface of the substrate is drawn into the axial center of the hole 3 by surface tension and becomes rounded.
再びピン5が下降して導電インキ4を孔内に押
し込む。 The pin 5 descends again to force the conductive ink 4 into the hole.
上記動作を繰り返すことにより、導電インキ4
が下部の孔縁に達して孔3が導電インキ4で埋ま
るのである(第6図)。 By repeating the above operation, the conductive ink 4
reaches the bottom edge of the hole and the hole 3 is filled with conductive ink 4 (FIG. 6).
孔3に導電インキ4の充填を完了した基板1を
乾燥処理すれば導電インキ4中の溶剤が蒸発して
インキが収縮し、第7図に示す如く、インキ層の
上面と下面の夫々中央部が少し凹んだ状態でイン
キが固化する。 When the substrate 1 with the conductive ink 4 filled in the holes 3 is dried, the solvent in the conductive ink 4 evaporates and the ink shrinks, and as shown in FIG. The ink solidifies with a slight depression.
本発明は上記の如く、基板1の孔縁に転移させ
た導電インキ4を往復動するピン5で孔中に強制
的に突き込むから、従来の様に導電インキが孔壁
を伝つて自重で垂れ落ちるのを待つのと較べて、
孔壁をインキで覆うに要する時間は短かくなり、
作業能率が上がる。又、従来よりも粘性の高い導
電インキ、即ち、溶剤の添加量の少ない導電イン
キを使用出来るため、該インキが乾燥硬化する際
のガスの発生量が少なく、導電インキの充填部に
空〓やクラツクの発生を抑えることができる。 As described above, the present invention forcibly pushes the conductive ink 4 transferred to the hole edge of the substrate 1 into the hole with the reciprocating pin 5, so that the conductive ink travels along the hole wall and is absorbed by its own weight, unlike in the conventional case. Compared to waiting for it to drip,
It takes less time to cover the hole walls with ink,
Work efficiency increases. In addition, since it is possible to use conductive ink with higher viscosity than conventional conductive ink, that is, conductive ink with a small amount of added solvent, less gas is generated when the ink dries and hardens, and there is no void or void in the area filled with conductive ink. It is possible to suppress the occurrence of cracks.
又、ピン5は孔の上縁に近接する位置迄しか下
がらず、孔3を貫通しないから、孔3は殆んど導
電インキ4で充まり電気導通の信頼度は高い。 Further, since the pin 5 is lowered only to a position close to the upper edge of the hole and does not penetrate through the hole 3, the hole 3 is almost filled with the conductive ink 4, and the reliability of electrical continuity is high.
尚、本発明は上記構成に限定されることはなく
特許請求の範囲に記載の技術範囲内で種々の変形
が可能であるのは勿論である。 It goes without saying that the present invention is not limited to the above configuration, and that various modifications can be made within the technical scope of the claims.
第1図は塗布装置の正面図、第2図は塗布板を
上昇した状態の塗布装置の正面図、第3図乃至第
7図は工程説明図、第8図は従来例の説明図、第
9図は従来例の断面図、第10図は従来例の説明
図である。
1……配線基板、3……貫通孔、4……導電イ
ンキ。
Fig. 1 is a front view of the coating device, Fig. 2 is a front view of the coating device with the coating plate raised, Figs. 3 to 7 are process illustrations, and Fig. 8 is an illustration of the conventional example. FIG. 9 is a sectional view of the conventional example, and FIG. 10 is an explanatory diagram of the conventional example. 1... Wiring board, 3... Through hole, 4... Conductive ink.
Claims (1)
導電インキを付着させることにより、配線基板の
両面に形成した導電パターン2,2を電気的に接
続する方法に於て、先端に導電インキ4を付着さ
せたピン5を該ピンの先端が配線基板1の孔3の
上縁に近接するまで下降させて、ピン上の導電イ
ンキ4を孔3の上側孔縁へ移し、次にピン5を上
昇させてピンを基板上のインキから離し、該ピン
を再び孔の上縁に近接して下降させ、このピンの
往復動作を繰り返して導電インキ4を徐々に孔3
中に押し込むことにより孔内に孔3の上下縁部に
跨がつて導電インキを付着せしめることを特徴と
する配線基板の表裏両導電パターン間の接続方
法。1 In a method of electrically connecting conductive patterns 2, 2 formed on both sides of a wiring board by attaching conductive ink to the inner surfaces of through holes 3, 3 made in a wiring board 1, conductive ink is applied to the tips of the wiring board 1. The conductive ink 4 on the pin is moved to the upper edge of the hole 3 by lowering the pin 5 to which the conductive ink 4 is attached until the tip of the pin approaches the upper edge of the hole 3 of the wiring board 1. is raised to separate the pin from the ink on the substrate, and the pin is lowered again close to the upper edge of the hole, and by repeating this back and forth movement of the pin, the conductive ink 4 is gradually drawn into the hole 3.
A method for connecting conductive patterns on both the front and back sides of a wiring board, characterized in that conductive ink is deposited in the hole so as to extend over the upper and lower edges of the hole 3 by pushing the conductive ink into the hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2792782A JPS58145189A (en) | 1982-02-22 | 1982-02-22 | Connection method between conductive patterns on both the front and back sides of a wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2792782A JPS58145189A (en) | 1982-02-22 | 1982-02-22 | Connection method between conductive patterns on both the front and back sides of a wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58145189A JPS58145189A (en) | 1983-08-29 |
| JPH035077B2 true JPH035077B2 (en) | 1991-01-24 |
Family
ID=12234513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2792782A Granted JPS58145189A (en) | 1982-02-22 | 1982-02-22 | Connection method between conductive patterns on both the front and back sides of a wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58145189A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51127374A (en) * | 1975-04-28 | 1976-11-06 | Sanwa Denki Seisakusho Kk | Method of connecting conductors at opposite surfaces of printed wiring substrate |
-
1982
- 1982-02-22 JP JP2792782A patent/JPS58145189A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58145189A (en) | 1983-08-29 |
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