JPH0351104B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic integrated circuit, and more particularly to a logic integrated circuit including a combinational circuit and having a scan path.

In recent years, the integration of logic integrated circuits has become more prominent, making it possible to integrate complex logic functions at high density. Testing integrated circuits for failure is becoming increasingly difficult. For this reason, the configuration of such a logic integrated circuit is sometimes devised in advance so that it can be easily tested for failures.

Conventional logic integrated circuits of this type include shift registers (scanpaths) configured by interconnecting flip-flops and registers that exist as internal storage elements for normal sequential circuit operations, and convert sequential circuits into combinational circuits (decoders). , encoders, comparators, multiplexers, etc.) can be tested separately. The scan data supplied in bit series from the tester to the logic integrated circuit under test is output to the tester via the scan path, and this output data is compared with the expected value data for the scan data to test the logic integrated circuit. Do this.

In such a conventional configuration, since testing is performed using only the scan path, the first drawback is that only flip-flops and registers that can be connected to the scan path can be tested. Also, since the gates through which signals pass are different between the scan path and the normal path during normal operation,
A second drawback is that even if it is abnormal during normal operation, it may be determined to be normal during testing, and it may be difficult to identify the cause of the defect or the defective location.

In order to eliminate these first and second drawbacks, the test does not rely solely on scan paths;
It is easy to consider providing external output terminals to logic integrated circuits in order to identify the cause of failure, identify the defective location, and analyze operation by setting a large number of observation points inside the circuit and observing the signals at these observation points. It will be done. However, such a simple configuration naturally causes a serious problem of pin-necking.

An object of the present invention is to provide a logic integrated circuit that allows an internal observation signal to be taken out to the outside without increasing the number of external output terminals.

The integrated circuit of the present invention is a logic integrated circuit including a combinational circuit and equipped with a scan path, in which a scan-out signal from the scan path and at least one internal observation signal of the combination circuit are connected to the external circuit from the same terminal in response to a switching signal. The present invention is characterized in that it includes a switching means for switching and outputting the switching signal, and a switching signal supplying means for supplying the switching signal to the switching means in advance.

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, this embodiment is a large scale logic integrated circuit (LSI) 1 having 26 input signal terminals and 19 output signal terminals. A total of 26 input signal terminals include a scan mode designation signal SM, scan data SD, scan clock SC, and 3 normal clocks NCL1,
NCL2 and NCL3 and 8 normal input data
NDI1, NDI2, NDI3...NDI8 and 12 normal input control signals NCI1, NCI2, NCI3...NCI1
It consists of terminals for performing two inputs. In addition, a total of 19 output signal terminals have 8 normal output data NDO1, NDO2, NDO3...NDO8,
10 normal output control signals NCO1, NCO2, NCO
3...Consists of terminals for outputting the NCO 10 and a test output terminal TO.

Referring to FIG. 2 showing a detailed diagram of the LSI 1, this embodiment has a combinational circuit 2, a multiplexer 3,
Inverter 4, three AND circuits 5, 6 and 7, and 24 flip-flops (FF) F1, F
2, F3...F24 and 48 switches (SW) S
1, S2, S3...S48.

The combinational circuit 2 is composed of a decoder, an encoder, a comparator, a multiplexer, etc. It can also be seen that the switches S1 to S24, the flip-flops F1 to F24, the multiplexer 3, and the test output terminal TO constitute a scan path. The multiplexer 3 outputs the internal observation signals K1 to K7 at seven points selected from the internal key points of the combinational circuit 2 and the scan-out signal SCO.
and is switched and outputted to the test output terminal TO in response to three switching signals M1 to M3.

FIG. 3 shows a detailed diagram of switches S1-S48. According to this figure, each of the switches S1 to S48 has two logic integrated circuits 8 and 9 and an inverter 1.
0 and an OR circuit 11. Input terminal 12 of switches S1 to S24
is the scan data SD (switch S1 only) or the output data terminal (Q terminal) output of the flip-flop F1 to F23 in the previous stage (switch S2 to S2).
4) is input, and input terminal 13 receives normal input data.
NDI1 (switch S1) or normal input data
NDI2 (switch S2) or normal input data
The output from NDI3 (switch S3) or the combinational circuit 2 (switches S4 to S24) is input, the scan mode designation signal SM is input to the input terminal 14, and the output terminal 15 is the input data terminal (D terminal).
The scan clock SC is input to the input terminal 12 of the switches S25 to S48, and the normal clock NCL1 is input to the input terminal 13 (switches S25 to S27).
Or normal clock NCL2 (switch S28)
Or normal clock NCL3 (switch S29~
S48) is input, the scan mode designation signal SM is input to the input terminal 14, and the output terminal 15 is the clock terminal (C terminal) of the flip-flop in the same stage.
It is connected to the.

Therefore, when the scan mode designation signal SM is logic "0", the signal input to the input terminal 13 appears at the output terminal 15, so that the switches S1, S2, S3, S4 to S24, S25
- Normal input data NDI1 and normal input data from S27, S28 and S29 to S48, respectively
NDI2, normal input data NDI3, combinational circuit 2
output, normal clock NCL1, normal clock
NCL2 and normal clock NCL3 will be output. In addition, scan mode designation signal SM
When is logic "1", the signal input to the input terminal 12 appears at the output terminal 15, so the switches S1, S2 to S24 and S25 to
The scan data SD, the Q terminal output of the flip-flop in the previous stage, and the scan clock SC are outputted from S48, respectively.

Now, when the present LSI 1 is caused to perform normal operation, the scan mode designation signal SM is set to logic "0". LSI1 usually has input data NDI1~
Based on NDI8 and normal input control signals NCI1 to NCI12, it operates in response to normal clocks NCL1 to NCL3, and the results of this operation are used as normal output data.
NDO1~NDO8 and normal output control signal NCO1~
Output as NCO10. At this time, the normal input data NDI1 to NDI1 to NDI from the AND circuits 5 to 7 respectively
NDI3 is output to the multiplexer 3 as switching signals M1 to M3, respectively, but the test output terminal
The signal obtained at TO is usually input data NDI1~
It is meaningless because it does not correspond to NDI3.

In order to obtain significant internal observation signals K1 to K7 at the test output terminal TO, first set the scan mode designation signal SM to logic "0" and apply only the normal clock NCL1 to output the normal input data.
Internal observation signals K1 to K7 as NDI1 to NDI3
The value corresponding to is supplied externally. Normal input data NDI1 to NDI3 3-bit binary data 001 to
111 correspond to internal observation signals K1 to K7, respectively.

Normally input data NDI1 to NDI3 are sent to flipflop F1 via switch circuits S1 to S3, respectively.
-F3 and is set in response to the normal input clock NCL1, which is supplied to flip-flops F1-F3 via switch circuits S25-C27.
The respective outputs of the flip-flops F1 to F3 are output as switching signals M1 to M3 from AND circuits 5 to 7, respectively, and are supplied to the multiplexer 3.

Next, normal clocks NCL2 and NCL3,
By supplying normal input data NDI1 to NDI8 and normal input control signals NCI1 to NCI12 from the outside,
Make LSI1 perform normal operation. At this time, since the normal clock NCL1 is not applied, the normal input data NDI1-NDI3, which is also supplied to the flip-flops F1-F3, is applied to the flip-flops F1-F3.
Therefore, the previously set switching signals M1 to M3 do not change. LSI
1, internal observation signals K1 to K
2 is supplied to multiplexer 3. The multiplexer 3 selects the already supplied switching signals M1 to M from among these internal observation signals K1 to K7.
Select only one based on 3 and test output terminal
Output to TO. Of course, normal output data NDO
1~NDO8 and normal output control signal NCO1~
NCO10 is also output.

In this way, when one internal observation signal is obtained at the test output terminal TO, the normal clock NCL1 and the normal input data NDI1 to NDI are input again.
3 from the outside, set another switching signal, and supply normal clocks NCL2 and NCL3, normal input data NDI1 to NDI3, and normal input control signals NCI1 to NCI12, then another internal observation signal can be set. Obtainable. By repeating this operating procedure, data useful for diagnosing the failure of LSI 1 can be collected.

When the scan mode designation signal SM is set to logic "1", a scan path as described above is established. The scan mode designation signal SM is inverted to logic "0" by the inverter 4 and input to the AND circuits 5 to 7, so the switching signals M1 to M3 become 000, and the multiplexer 3 selects the scan out signal SCO from the flip-flop F24. Then, it becomes possible to output to the test output terminal TO. In this state,
By supplying scan data SD and scan clock SC, it becomes possible to test using the normal scan pass method.

The first effect of this embodiment is that the switching signals M1 to M
Since 3 is the same binary data as normal input data NDI1 to NDI3, normal input data NDI1 to NDI3 is the same binary data as normal input data NDI1 to NDI3.
It is easy to correspond with NDI3.

The second effect of this embodiment is that the switching signals M1 to M
Since the external supply signal for generating 3 is supplied using the external input terminal that is also used during normal operation, it is possible to suppress the increase in the number of external input terminals.

In this embodiment, in order to generate the switching signals M1 to M3, the normal input signals NDI1 to NDI are
3 are directly supplied to the switches S1 to S3, respectively, but the combinational circuit 2 supplies the switches S1 to S3 directly.
It is possible to easily realize an embodiment in which the power is supplied to the user.

Furthermore, the switching signals M1 to M3 may be directly supplied to the multiplexer 3 from outside.

According to the present invention, by employing the above configuration, the test output terminal can be used to time-divisionally output the internal observation signal and the scan-out signal, without increasing the number of external output terminals. , it becomes possible to take out internal observation signals to the outside.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention, and FIGS. 2 and 3 show detailed views of this embodiment. 1...Large scale logic integrated circuit, 2...Combination circuit, 3...Multiplexer, 4, 10...Inverter, 5, 6, 7, 8, 9......Logic product circuit, 11
... OR circuit, 12, 13, 14 ... Input terminal, 15 ... Output terminal, F1 to F24 ... Flip-flop, S1 to S48 ... Switch circuit,
SM...Scan mode designation signal, SD...Scan data, SC...Scan clock, TO...Test output terminal, NCL1, NCL2, NCL3...Normal clock, NDI1 to NDI8...Normal input data, NDO1 to NDO8... Normal output data, NCI
1~NCI12...Normal input control signal, NCI1~
NCI10...Normal output control signal, M1, M2, M
3...Switching signal, K1 to K7...Internal observation signal, SCO...Scan out signal.

Claims (1)

[Claims] 1. In a logic integrated circuit including a combinational circuit and equipped with a scan path, a scan-out signal from the scan path and at least one internal observation signal of the combination circuit are connected to the outside from the same terminal in response to a switching signal. 1. A logic integrated circuit comprising: switching means for switching output to the switching means; and switching signal supply means for supplying the switching signal to the switching means in advance. 2. Claim 1, wherein the switching signal is generated, held, and supplied based on a signal applied to at least one input terminal of the combinational circuit and a scan mode designation signal.
Logic integrated circuit described in section.