JPH0352159B2 - - Google Patents

Description

[Detailed description of the invention]

For example, the present invention can be applied to associative memory (Content memory).
This provides a simple circuit configuration of a prioritized address encoder used to encode multiple matching address signals such as Addressable Memory (CAM) in a certain order to obtain a binary address output. The basic function of CAM is to input reference data, contrary to normal memory, and output the address of the word where data that matches the reference data is stored, but if a match is obtained in multiple words. In some cases, a normal encoder cannot provide the correct encoded output. That is, before applying signals to a normal binary encoder, it is necessary to set an appropriate order so that only one signal becomes an ON potential, and to synchronize with a clock signal so that the signals are switched and output in sequence. The functions that the priority address encoder should have are explained below using FIG. now,
It is assumed that the priorities of the input signal vectors (IN ₃ , IN ₂ , IN ₁ , IN ₀ ) decrease in the order of IN ₃ > IN ₂ > IN ₁ > IN ₀ . _C1 is the set terminal, _C2 is the clock terminal, _C3 is the
This is the input terminal of the inverted clock of _C2 . (
UT ₃ , UT ₂ , UT ₁ , UT ₀ ) are intermediate output vectors corresponding to each input signal vector, ADR ₀ ,
ADR ₁ and ADR ₂ are encoded final address outputs. After resetting the entire system using the set terminal _C1 , addresses are sequentially output according to the input vector and clock signal. IN → (IN ₁ , IN ₂ , IN ₃ , IN ₄ ) UT (UT ₁ ,
Conversion of UT ₂ , UT ₃ , and UT ₄ is performed according to the following rules. (1) When there is 0 or 1 logic “1” in the input vector elements, UT=IN→(first clock), UT=0→(second clock onward), (2) Input vector When there are two or more logic "1"s in an element, for example, if IN _i , IN _j , IN _k are logic "1" and i > j > k, the priority decreases in this order, i th ↓ UT=(0,...0,1,0...,0)(1st
clock) jth ↓ UT=(0,...0,1,0...,0)(2nd
clock) kth ↓ UT=(0,...0,1,0...,0)(3rd
clock) UT=(0, 0, . . . 0) (from the fourth clock onward) In other words, the output vector contains only one or less logic "1" as an element. If the input vector contains a plurality of "1" elements, they are output one by one to the output vector in order of priority according to the clock. For example, when IN → = (1, 0, 1, 0), UT = (1, 0, 0, 0) (first clock) (0, 0, 1, 0) (second clock) (0, 0, 0, 0) (after the third clock) Next, according to these intermediate output vectors OUT-→,
Address encoding is done. If UT _i is logic "1", the binary representation of i is output as is as the output address. This encoder is a normal one, and the part surrounded by the broken line in FIG. 1 has its function. For example, UT ₁ is “1”
(i.e., at ON potential), the field effect transistor (FET) connected to ADR ₂ and ADR ₁ is ON.
, current flows through the load resistances R and R',
The potential of output terminals ADR ₂ and ADR ₁ decreases to logic “0”
becomes. On the other hand, since the potential of ADR ₀ does not fall, it is in the logic "1" state, and the result is (ADR ₂ , ADR ₁ , ADR ₀ )=(001). If IN→ is directly applied to the encoder without passing through block x that converts IN→OUT−→, a correct address output will not be obtained if multiple elements are logic “1”. For example, if IN ₂ and IN ₁ are “1”, if you do not go through X (ADR ₂ , ADR ₁ , ADR ₀ ) = (0, 0, 0)
This results in a malfunction. Conventionally, there was no relatively simple circuit with such a conversion function, so
It was nearly impossible to configure a prioritized address encoder. FIG. 2 shows the principle of construction of the present invention. IN is the input terminal, OUT is the output terminal, _C1 is the set pulse input terminal,
C ₂ is a clock pulse input terminal, C ₃ is an input terminal for the inverted clock pulse of C ₂ , P ₁ is a propagation control input terminal, P ₂ is a propagation control output terminal, and S ₁ , S ₂ , S ₃
is a switch circuit that has an output holding function, and in this case an N-channel enhancement field effect transistor (FET) is used, but any circuit that has a similar function may be used. _A1 ～ _A3
is a logical product circuit (AND), and _I1 is a logical inversion circuit (INVERTER, INV.). If even one “ ₁ ” is applied as an input signal at a higher priority address (in this example, the upper block), the propagation control input P1 becomes “0”.
is propagating. Switch _S2 is a switch with a reset function, and when _P1 is "1", clock _C2
It is reset to "0" each time the input signal is applied, and continues to be reset until the next switch _C1 is turned on to set the input signal. Avoid applying "1" to C ₁ and C ₂ at the same time. An example of this is shown in FIG. The operation of the circuit of FIG. 2 is classified as follows according to the input signal. (1) When P ₁ = “1” and the potential of node Q is set by S ₁ and not yet reset by S ₂ , OUT = IN (Q) P ₂ = IN → () (2) P If ₁ = “1” and the reset by S ₂ has been completed, UT = “0” (Q) P ₂ = “0” () (3) If P ₁ = “0”, UT = “0” P ₂ = “0” However, switch S ₃ , which is inserted just before P ₂ ,
P ₂ becomes “0” at the moment Q is reset by S ₂
This is inserted to temporarily prevent the propagation of the control signal so that the portion corresponding to Q in the next stage and subsequent stages is not reset. Therefore, when C ₂ is “1”, S ₃ is
In order to turn OFF, an inverted clock pulse of _C2 is applied as _C3 . The above input/output truth tables are summarized in Tables 1 and 2 below. In Table 2, UT _o and P _2o are current values OUT _o-1 and P _2o-1 are values one clock ago, respectively.

【table】

[Table] In this way, the circuit of Figure 2 has one signal input, one propagation control input, three clock control inputs C ₁ , C ₂ , C ₃ and one signal output. Each terminal has three propagation control output terminals, and three AND circuits.
It consists of A ₁ , A ₂ , A ₃ , three switch circuits S ₁ , S ₂ , S ₃ with an output holding function, and one logic inversion circuit I ₁ , and is controlled by a clock control input C _1. A switch circuit _S1 is arranged at the signal input terminal, and the output of the switch circuit _S1 is input to the AND circuit A3 via the AND circuit _A1 and the logic inversion circuit _I1 , and the clock control input _C2 is input to the AND circuit _A3 . Similarly, the AND circuit A ₂ is inputted to the control input terminal of the switch circuit S ₃ , the propagation control input is used as the other input of each of the AND circuits A ₁ , A ₂ , and A ₃ , and the output of the AND circuit A ₂ is A signal source of logic "0" is connected as a control input of _the switch circuit _S2 , and a signal source of logic "0" is connected as an input of the switch circuit _S2 , and its output is made common to the output of the switch circuit S1, and the logical product _A1
This is an encoding circuit element consisting of a circuit group in which the output of the logical product _A3 is used as a signal output, the output of the logical product _A3 is used as an input of a switch circuit S3, and the output of the switch circuit _S3 is used as a propagation control output. A plurality of such circuit elements are arranged in a line, a logic "1" signal source is connected to the propagation control input terminal of the first element in the encoding circuit element sequence, and the propagation control output of the first element is used as the propagation control input of the second element. input, connect the propagation control output of the second and subsequent elements to the propagation control output of the next stage element one after another, leave the propagation control output end of the last element open, and as a whole the number of encoding circuit elements and A prioritized address encoder having the same number of input terminals and output terminals can be obtained. In practice, when realizing a logic circuit similar to the one shown in FIG. 2, it is often difficult to form an AND circuit in one stage. What can be easily formed is the logical product of negative polarity outputs (NAND) or the logical product of negative polarity inputs (NR).
Add INV., and for NR, add INV. to the input. FIG. 4a uses NRA ₁ to A ₃ and uses I ₃ and I ₄ as input INV. Further, clock ₂ applies a negative polarity clock ( ₂ in FIG. 3). Therefore, even if the same clock is applied to the input of A ₂ and the control input of switch S ₃ (that is, C ₂ and C ₃ are made common), the result will be the same as applying the opposite phase clock. Same effect. On the other hand, FIG. 4b uses NANDA ₁ to A ₃ and adds INV.I ₅ to I ₇ to each NAND output.
Since C ₂ is still a negative polarity clock, INV.I ₂ is required for input to A ₂ . That is, in FIG. 4a, three AND circuits each having a negative polarity input and a positive polarity output are used, the corresponding input signals are inputted through the logic inverting circuit, and the clock control input _C2 is inputted. The encoder circuit element is configured by inputting the signal with negative polarity and applying the clock control input _C3 , which is the same as _C2 , to the control input of the switch circuit _S3 . In addition, in FIG. 4b, logic circuits each having a positive polarity input and a negative polarity output are used as three AND circuits, and corresponding output signals are outputted via a logic inverting circuit,
By inputting the clock control input _C2 with negative polarity and making the clock control input _C3 the same as _C2 , the switch circuit
In addition to applying the clock control input to the control input of _S3 , the clock control input is applied to the AND circuit _A2 via another inverting circuit _I2 . Figure 4c shows an arrangement of NAND type and NR type elements alternately, and when connecting the propagation control output of one element to the propagation control input of the next stage, two stages of INV. are connected in series, so this is the case. is omitted. That is, in FIG. 4c, an encoding element a using a negative polarity input positive polarity output AND circuit and an encoding circuit element b using a positive polarity input negative output AND circuit are arranged alternately, and , the two logic inversion circuits are omitted: the logic inversion circuit at the propagation control input terminal of encoding circuit element a, and the logic inversion circuit at the propagation control output section of encoding circuit element b, which is connected in series with the logic inversion circuit. This is a combination of propagation control input and output. As is almost clear from the above explanation, the circuit element of the present invention operates as shown in the truth tables of Tables 1 and 2, so this circuit element is placed in the part marked X in FIG. It can be seen that the function of the prioritized address encoder can be realized by sequentially connecting the propagation control input and output terminals. Here, the problem in terms of operating speed is the propagation time of the propagation control signal, and if this is long, the operating speed of the entire priority address encoder becomes slow. When the circuit elements in Figure 4 a and b are arranged in order to form part X in Figure 1, the propagation control signal passes through two stages of gates (INV.+NAND or INV.NOR) for each element, resulting in a large delay. There is a high possibility that it will happen. Therefore, as shown in Figure 4c,
By arranging NAND-type elements and NOR-type elements alternately, INV. in the path of the propagation control signal can be omitted, and each element only needs to go through one stage of gates, so the delay can be reduced to about half. Therefore, the overall operation is improved approximately twice, and a prioritized address encoder with good characteristics can be realized.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing an example of the basic overall configuration of a prioritized address encoder, and FIG. 2 is a basic circuit of elements of an encoding circuit according to an embodiment of the present invention having the basic functions of a prioritized address encoder. Diagram,
Figure 3 is a diagram showing a time chart of the set signal and control clock applied to the encoding circuit element shown in Figure 2, and Figures 4 a, b, and c realize the encoding circuit element shown in Figure 2. FIG. 2 is a circuit configuration diagram constructed using easy-to-use circuit elements. C ₁ , C ₂ , C ₃ ... Clock control input, S ₁ , S ₂ ,
S ₃ ... Switch circuit, A ₁ , A ₂ , A ₃ ... AND circuit, P ₁ , P ₂ ... Propagation control input, output, I ₁ , I ₂ , I ₃ ,
I ₄ , I ₅ , I ₆ ... Inverting circuit.

Claims (1)

[Claims] 1. Signal input, propagation control input, first, second, third
It has a clock control input, a signal output, and a propagation control output terminal, and has first, second, and third AND circuits, first, second, and third switch circuits with an output holding function, and logic inversion circuits. a circuit, the first
said first clock control input controlled by a clock control input of
a switch circuit is disposed at the signal input terminal, the output of the first switch circuit is inputted to the third AND circuit via the first AND circuit and the logic inversion circuit, and the second A clock control input is input to the second AND circuit, a third clock control input is input to the control input terminal of the third switch circuit, and the propagation control input is input to the first, second, and third switch circuits. , the output of the second AND circuit is used as the control input of the second switch circuit, and a logic "0" signal source is connected as the input of the second switch circuit. The output thereof is made common to the output of the second switch circuit, the output of the first AND circuit is used as the signal output, and the output of the third AND circuit is used as the input of the third switch circuit, A plurality of encoding circuit elements whose propagation control output is the output of the third switch circuit are arranged in a row, and a logic "1" signal source is connected to the propagation control input terminal of the first element of the encoding circuit element array. , connect the propagation control output of the first element to the propagation control input of the second element, and connect the propagation control outputs of the second and subsequent elements to the propagation control outputs of the elements in the next stage one after another, An encoding circuit characterized in that a propagation control output terminal of the last element is open, and the encoding circuit has the same number of input terminals and output terminals as the number of elements as a whole. 2. As the first, second, and third AND circuits, AND circuits each having a negative polarity input and a positive polarity output are used, and the corresponding input signals are inputted through the logic inverting circuit, and the second clock control input is inputted. A patent characterized in that the third clock control input is input with negative polarity, is the same as the second clock control input, and is applied to the control input of a third switch circuit to configure the encoding circuit element. An encoding circuit according to claim 1. 3. As the first, second, and third AND circuits, logic circuits with positive polarity input and negative polarity output are used, and corresponding output signals are outputted via logic inversion circuits, and the second
a clock control input of negative polarity, a third clock control input identical to the second clock control input and applied to the control input of the third switch circuit, and the second clock control input 2. The encoding circuit according to claim 1, wherein the encoding circuit has an encoding circuit element in which the voltage is not directly applied to the second AND circuit, but is applied through another logic inversion circuit.