JPH0352585B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor integrated circuit having a built-in test circuit and at least three power supply terminals (including a ground terminal), in which the test circuit is driven to control the internal circuitry. This invention relates to semiconductor integrated circuits for testing performance, etc.

As is well known, in semiconductor integrated circuits, complex and large-scale circuits are integrated within a single semiconductor substrate. When testing circuits built into semiconductor integrated circuits, if a dedicated testing circuit designed to improve testing efficiency is not built-in, the testing itself will not only be complicated, but also be difficult to test. This requires a long time, and the efficiency of the inspection process is significantly reduced. This decrease in inspection efficiency is one of the major factors that increases the manufacturing cost of semiconductor integrated circuits. Therefore, in order to test semiconductor integrated circuits easily and efficiently, there are semiconductor integrated circuits that have a built-in circuit dedicated to testing. To test a semiconductor integrated circuit using this test circuit, it is necessary to input a signal from the outside that changes the internal state of the semiconductor integrated circuit to test mode, or a special signal to operate the test circuit. .

Conventionally, when supplying the above-mentioned mode switching signal or special signal from the outside, there is a method in which one of the external leads of the semiconductor integrated circuit is used as an input terminal exclusively for the test signal.

FIG. 1 is a schematic diagram showing a semiconductor integrated circuit to which such a conventional method is applied, and one of the external lead wires led out from the sealed container 1 serves as a test-only input terminal TST. Note that V _S1 to V _S3 are power supply terminals. By the way, the TST terminal is a terminal used only during testing, and when the voltage level applied to this terminal is set to high level (VDD level), the internal testing circuit becomes operational, and semiconductor integrated circuit testing can be performed in this state. It becomes possible to do so.
However, during actual operation, this pin TST
is not used at all and remains at low level (ground level)
is fixed. In this way, adding terminals that are not used at all during actual operation is not desirable in multifunctional, high-density semiconductor integrated circuits where the number of terminals is severely restricted. In particular, as shown in the figure, if the arrangement of the external lead wires is a dual-in-line type, an increase in one terminal will essentially lead to an increase in two external lead wires, and in some cases, an increase in the number of external lead wires may occur. This causes the inconvenience that the container itself becomes larger.

The present invention provides a semiconductor integrated circuit that can eliminate the above-mentioned disadvantages, and includes a built-in test circuit and at least three power supply terminals. A power supply voltage and a voltage at a level different from the power supply voltage are selectively applied to the power supply voltage, and when the latter voltage is applied, a test signal is generated from the test circuit, and this signal is used to determine the state of the semiconductor integrated circuit. The present invention is characterized in that it is set as the inspection mode.

FIG. 2 is a schematic diagram showing a semiconductor integrated circuit to which the present invention is applied, and as shown in the figure, the power supply terminal V _S1
One of the external lead-out lines, eg, V _{S3 ,} is shared with the test-only input terminal TST.

FIG. 3 is a partial schematic diagram of the integrated circuit configured in the sealed container 1, and shows the power supply terminals shown in FIG.
It is a diagram showing the relationship between V _S3 and internal circuits connected thereto, where 2 is a test circuit, 3 is a Schmitt circuit, 4 is an inverter, and 5 is a power supply line within the semiconductor integrated circuit.

During normal operation, the original power supply voltage (high level voltage) is applied to the power supply terminal V _S3 , and this voltage is applied to a predetermined portion of the internal circuit via the power supply line 5. On the other hand, during inspection, if the terminal V _S3 is forcibly fixed to φV (ground level) from the outside, the terminal
By the function of Schmitt circuit 3 and inverter 4 installed between V _S3 and test circuit 2, test circuit 2
The signal being sent inside changes from high level to low level. The level change of this signal becomes a signal that enables the test circuit 2 inside the semiconductor integrated circuit, and the state of the semiconductor integrated circuit becomes the test mode. In other words, terminal V _S3 is an input terminal exclusively for inspection.
It becomes TST.

As explained above, according to the present invention, the power supply terminal also serves as a test-only input terminal, so that a terminal such as the test-only input terminal TST, which is essential in the example of FIG. 1, is no longer necessary. Also, power terminal 1
As mentioned above, one terminal is also used as a test-dedicated terminal, so a predetermined constant voltage can be applied during normal operation, and the voltage at this terminal will not fluctuate. Note that the method of the present invention in which one of the power supply terminals is shared does not share the input terminal to which a complex digital signal is applied. There is no need to add a circuit to eliminate the inconvenience of falling into inspection mode due to time noise or the like.

It should be noted that the reduction in the number of input terminals dedicated to inspection leads to the effect of increasing the number of external lead-out wires or the effect of downsizing the sealed container based on the reduction in the number of external lead-out wires themselves.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a semiconductor integrated circuit to which a conventional testing method is applied, and FIGS. 2 and 3 are schematic diagrams of a semiconductor integrated circuit to which the present invention is applied. 1... Sealed container, 2... Inspection circuit, 3... Schmitt circuit, 4... Inverter, 5... Power line, TST
… Input terminals exclusively for inspection, V _S1 to V _S3 … Power supply terminals.

Claims (1)

[Claims] 1. A power supply voltage and a voltage at a level different from the power supply voltage should be selectively applied to one of the power supply terminals of a semiconductor integrated circuit that has a built-in test circuit and at least three power supply terminals. , a semiconductor integrated circuit characterized in that a test signal is generated from the test circuit when the latter voltage is applied.