JPH0353671B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control circuit for a memory used by being connected to a data flow calculation section, and more specifically, the information stored in the memory can include not only data values but also program templates. The present invention relates to a template reading circuit characterized by:

The template refers to a template that has a destination address and a control signal field in addition to a data field, as shown in FIG. The value of the control field determines the meaning of the data field, and represents, for example, a data value to be subjected to an operation, an address value of an external memory, a command word, etc.

Before starting an operation, it is necessary to set the command and accompanying parameters in advance, and in this case, the command word is stored in the data field. The main function of the template reading circuit of the present invention is to store these instructions in an external memory in advance and load them directly from the external memory into the processor at high speed during initialization.

Conventionally, data values such as numerical values and images could be stored in a memory connected to a data flow calculation unit. However, the program template itself had to be transferred from the host processor to the data flow calculation section via the interface each time, which required a considerable amount of time for transfer. A program template consists of control information and template values, and the control information field output from memory is either generated using the control information field of data input to memory, or The value set in the register in the control circuit was used. When writing to memory, only the data value that is part of the input data is written, and the control information field disappears within the memory control circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a template reading circuit which is capable of storing the program template itself in memory, and which is capable of storing both data values and program templates, rather than simply using the memory to store data values. There is a particular thing.

According to the present invention, a register for temporarily storing input data, a memory accessed by an address value and a data value output from the register,
a control unit that generates a control signal for the register, the memory, and an external output signal based on information in a control field that is part of input data; and a control unit that increments and updates an address value from the register to generate an address for the memory. and an address generation unit that stores a data value or a program template that is part of the input data in the memory according to the information in the control field, and generates an address value of the memory in which the program template is stored. A template reading circuit is provided, characterized in that the template of the program can be read out at high speed by generating an address specified by input data and sequentially incremented from the address generation section, and can be sent to an external data flow calculation section. It will be done.

Next, the present invention will be explained using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 101 is a control unit, 102 is a memory, 111 is a register that latches a control field of input data, and 112 is a register that latches a data field of input data when it is a data value to be written to the memory 102. , 113
The data field of the input data is in the memory 102.
121 to 123 are AND gates, and 131
~132 is a multiplexer, 141 is an adder, 1
51 to 171 are signals.

The input data 151 is composed of a control signal field and a data field, and the control signal field is a write/read switching signal of the memory 102;
It consists of a template write control signal, a valid flag, a signal indicating whether it is an address or data, and a signal indicating the destination of the data, and the data field is set as an address value, a data value, and a template value, respectively, depending on the value of the control signal field. Switch and use. The contents stored in memory 102 are data values or templates. Input data 151
is sent in synchronization with the system pipeline clock 162, and is divided into a control signal field and a data field, making up a set of two fields, and is taken into the circuit of the present invention in this order.

A plurality of templates are stored in advance in an external memory in the order of a program template and a startup data template. The template reading circuit of the present invention allows a program template stored in an external memory to be loaded at high speed without the intervention of a host processor, and processing in the processor does not start just by loading the program template. The processor is in an idle state. Processing does not begin until the activation data template is then input. Generally, the number of program templates is large, whereas the number of activation data is small, so the present invention is mainly aimed at loading program templates at high speed. By using the template reading circuit of the present invention, the host processor first transfers templates and data values to external memory, and then simply activates the template reading circuit. First, the program template is set, and then the program template is activated. Data templates flow, processing is started, data templates are generated one after another, data values are read from external memory, processed, and the results are written back to external memory. After the processing is finished,
If the program is programmed in advance to return end data to the host processor, the host processor can thereby know that the processing has ended.

A program template is set only once before executing a series of processing programs, and is repeatedly read and used without being changed during processing. On the other hand, data values of data templates are changed as a result of processing.

The signal 153 is a busy signal, and the control unit 101
is output to the previous pipeline stage.
Signal 153 is a control signal for stopping data input from the previous stage while reading from memory 102 occurs twice in succession when input data 151 indicates a template read command. When the signal 153 is "0", it indicates that input is possible, and when it is "1", it indicates that input is disabled.

The signal 154 is a reset signal, and the control unit 10
This is to set the flip-flop in 1 to the initial state. When signal 154 is "1", the internal state is reset.

A signal 157 is a write/continue output switching signal of the memory 102, and when it is "0", it indicates writing, and when it is "1", it indicates reading.

Signal 162 is the system pipeline clock. The circuit of the present invention is connected to an external data flow calculation circuit by a ring-shaped pipeline bus, and one set of data is generated in two pipeline cycles. In the first pipeline cycle, the input data 151 carries a control signal field, and in the next pipeline cycle, it carries a data field. The same applies to output data 170.

The control section 101 inputs a control field signal 152, a reset signal 154, a system pipeline clock 162, a busy signal 153, a signal 15
5,156,157,158,159,160,
161 is output. The control unit 101 generates latch enable signals for the registers 111, 112, and 113, switching signals for the multiplexers 131 and 132, and write/read switching signals for the memory 102, and controls the internal circuit of the present invention. Generates output data to a certain data flow arithmetic circuit.

The memory 102 is accessed using the address value 166 output from the register 113 as an address, and when the value of the signal 157 output from the control unit 101 is "0", the signal 166 from the register 113 is accessed.
6 is written as data, and the signal 157
When the value of is “1”, reading is performed and the read value is used as the signal 169 to be sent to the multiplexer 13.
Output to 2.

The register 111 latches a control field that is part of the input data 151 at the rising edge of the clock 171, holds its value, and outputs it as a signal 152 to the control section 101 and multiplexer 132.

Register 112 latches at the rising edge of clock 163 when a data value that is part of input data 151 is data to be written to memory 102 and outputs it to memory 102 as signal 164 .

When the data value that is part of the input data 151 is a write address to the memory 102, the register 113 becomes the signal 165 via the multiplexer 131, latches at the rising edge of the clock 168, and outputs it to the memory 102 as the signal 166. do.

Gate 121 receives system pipeline clock 162 and enable signal 16 from control unit 101.
1 and outputs the clock signal 171 of the register 111.

The enable signal 161 becomes "1" when the input data 151 is a control field. In the initial state, that is, when the reset signal 154 is "1", it becomes "1".

Gate 122 receives system pipeline clock 162 and enable signal 16 from control unit 101.
It is ANDed with 0 and outputs the clock signal 163 of the register 112. The enable signal 160 becomes "1" when the input data 151 is a data value.

Gate 123 receives system pipeline clock 162 and enable signal 15 from control unit 101.
8 and outputs the clock signal 168 of the register 113. Enable signal 158 is “1” when input data 151 is an address value
becomes.

Multiplexer 131 combines data values that are part of input data 151 and signal 16 from adder 141.
7 is selected and the input signal 165 of the register 113 is generated. The value of the multiplexer switching signal 159 output from the control unit 101 is “0”
When it is "1", the signal 151 is selected, and when it is "1", the signal 167 is selected. The multiplexer switching signal 159 becomes "1" when outputting the data field for template reading.

The multiplexer 132 selects either the output signal 152 of the register 111 or the output signal 169 of the memory 102 and sets it as output data 170. When the selection signal 156 from the control unit 101 is "0", the signal 169 is selected, and when it is "1", the signal 152 is selected. The selection signal 156 becomes "1" when the data field for template reading is output.

Adder 141 receives output signal 16 of register 113
6 and the value "1" are added, and a signal 167 is output to the multiplexer 131.

Next, the operation of this circuit will be explained.

The input data 151 can be roughly divided into the memory 102
There are write data values, write address values, data value read address values, template value read address values, and invalid data. memory 10
When writing data values and template values to register 112, first place these values in the data value field and set them in register 112, place the data write code in the control signal field, and write them into register 112.
Set to 11. Next, a write address value is placed in the data field and set in the register 113, and an address write code is placed in the control signal field and set in the register 111. At the same time that the address value is set in register 113, writing to memory 102 is performed. At this time, the output data 170 becomes invalid, and the valid flag included in the output data 170 becomes "0". That is, no output is performed to the next pipeline stage.

When reading data values from the memory 102,
A data read code is placed in the control signal field of the input data 151 and set in the register 111, and the address value of the memory 102 is placed in the data field and set in the register 113. At the same time as the read address is set, the memory 102
The read value becomes output data 170 and is output to the next pipeline stage. At this time, the valid flag included in the output data 170 is set to "1", indicating that this data is valid.

When reading a template from memory 102, a template reading code is placed in the control signal field of input data 151, and register 1
11 and set the data field to memory 10.
The address value of 2 is placed in the register 113. Reading from the memory 102 is performed at the same time as the read address is set, but in this case, the read is first performed using the address set in the register 113, and the output data 17
At the same time as the value becomes 0, "1" is added to the value 166 of the register 113 in the adder 141, and is latched into the register 113 via the multiplexer 131 at the next pipeline stage. In the next pipeline stage, the address value 166 latched in the register 113 is used to read out the memory 102 again, resulting in output data 170. During this time, the busy signal 153 becomes "1" and the input data 151 is stopped. Therefore, template values are written in data value write mode using four pipeline clocks when writing to memory 102, and are implemented using three pipeline clocks when reading from memory 102.

When the control signal field of the input data 151 indicates invalid data, the circuit of the present invention neither writes to the memory 102 nor generates the output data 170; Set the flag to “0”.

FIG. 2 is a more detailed block diagram of the control section 101 in FIG. 1.

In the figure, 201 is a decoder, 202 is a register, 203 is a gate circuit, 211-212 are flip-flops, 221-222 are AND gates,
231-232 are logical negation gates, 251-25
5 is a detailed signal corresponding to the signal 152 in FIG. 1, and 256 to 261 and 263 to 272 are signals.

Decoder 201 decodes signals 251-255 and generates signals 256-260. signal 25
1 indicates whether the data field of the input data 151 in FIG. 1 is an address value or a data value; when it is an address value, it is "1" and when it is a data value, it is "0". A signal 252 indicates whether the data field of the input data 151 in FIG. 1 is a read address or a write address, and is "1" when it is a read address and "0" when it is a write address.
It is. A signal 253 indicates whether the data field of the input data 151 in FIG. 1 is a template address; when it is "1", it is a template address; when it is "0", it is a data address. A signal 254 is a signal indicating whether the input data 151 in FIG. 1 is a control signal field or a data field.
It becomes "0" by the reset signal 154 in the figure. When the signal 254 is "0", it is a control signal field, and when it is "1", it is a data value field. Signal 255 is input data 15 in FIG.
1 indicates whether it is valid or invalid,
It is valid when it is “1” and invalid when it is “0”. When invalid, the data disappears inside the circuit of the present invention and does nothing.

The register 202 latches the signals 256 to 259 and 264 at the rising edge of the clock signal 162.
The signals are output to signals 261 to 265, respectively. signal 256
indicates whether the data field of the input data 151 in FIG. 1 is a read address,
It becomes "1" when it is a read address, and becomes "0" when it is not. A signal 257 indicates whether the data value field of the input data 151 in FIG. 1 is a write data value, and becomes "1" when it is a write data value, and becomes "0" otherwise. A signal 258 indicates whether or not the data value field of the input data 151 in FIG. 1 is a write address, and becomes "1" when it is a write address, and "0" otherwise.
becomes. A signal 259 indicates whether the data field of the input data 151 in FIG. 1 is a template read address or not, and becomes "1" when it is a template read address, and becomes "0" when it is not. The signal 260 becomes "1" when the input data 151 in FIG. 1 is invalid, and becomes "0" otherwise. signal 261
is signal 256, signal 262 is signal 257, signal 263 is signal 258, signal 264 is signal 25
9, signal 265 is the output signal after latching signal 264.

The gate circuit 203 receives signals 261 to 265, 25
Input 6 to 260, take the logical OR of the input signals,
Signals 153, 156 to 161, 155, 271 are output. A signal 271 is a signal indicating whether or not the field of the input data 151 in FIG. 1 changes in the next pipeline cycle, and becomes "1" when the field changes, and becomes "0" otherwise.
A signal 155 is a signal indicating whether or not the field of the output data 170 in FIG. 1 changes in the next pipeline cycle, and becomes "1" when the field changes, and becomes "0" otherwise. Flip-flop 211 samples signal 267 at the rising edge of clock 272 and outputs it as signal 254.

Flip-flop 211 receives reset signal 154
The signal 254 becomes "0". Flip-flop 212 samples signal 269 at the rising edge of clock 272, and samples signal 268.
Output to. The signal 268 becomes "0" when the output data 170 in FIG. 1 is a control signal field, and becomes "1" when it is a data field. Flip-flop 212 receives reset signal 15
4, and the signal 268 becomes "0". The gate 221 ANDs the signal 271 and the signal 162 and outputs the result as a signal 272. gate 222
takes the logical product of signal 155 and signal 162 and returns signal 2
Output to 70. Gate 231 logically negates signal 266 and outputs it as signal 267 . gate 23
2 takes the logical negation of the signal 268 and outputs it as the signal 269.

FIG. 3 is a logic table of decoder 201 in FIG. 2. Input signals 251 to 255 are written in the horizontal direction, and output signals 256 to 260 are written in the vertical direction. Each signal corresponds to the signal in FIG. For example, this decoder can be implemented with a programmable logic array, in which case each horizontal row corresponds to a term, "0" is a low level input, "1" is a high level input, and blank spaces indicate that the input is low level. Show that either high level is fine. When the input conditions are met, the output becomes "1" and a high level is output.

FIG. 4 is a logic table of the gate circuit 203 in FIG. 2. Input signals 256 to 265 are written in the horizontal direction, and output signals 153, 271, and 265 are written in the vertical direction.
155, 159, 156, 160, 157, 16
1,158 is written on it. The input signals corresponding to "1" in the table are logically summed and used as an output signal.

FIG. 5 shows the data format of the input signal 151 in FIG. Signal 301 is the destination address and signal 302 is the data field. Signals 301, 252, 253, 255, 25
1 forms the control signal field of input signal 151 in FIG.

As explained above, the present invention is characterized in that data values and program templates in a data flow processing device can be stored and read out in the same memory, reducing the burden on the host processor and processing This has the effect that performance can be improved and processing can be performed at high speed while replacing templates inside the data flow processing device.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of the template reading circuit of the present invention, and FIG. 2 is a control unit 1 of FIG.
01, FIG. 3 is a diagram showing the logic of the decoder 201 in FIG. 2, FIG. 4 is a diagram showing the logic of the gate circuit 203 in FIG. 2, and FIG. 5 is a diagram showing the input signal of FIG. 151 is a diagram showing an example of a data format of No. 151. In the figure, 101 is a control unit, 102 is a memory, 111 to 113 are registers, and 121 to 123 are
is a gate, 131 to 132 are multiplexers, 1
41 is an adder, 201 is a decoder, 202 is a register, 203 is a gate circuit, 211 to 212 are flip-flops, 221 to 222 are gates, 23
1 to 232 are gates.

Claims (1)

[Claims] 1 In a template reading circuit in a data flow processing device, a register temporarily stores input data, a memory accessed by the address value and data value output from the register, and information on a control field that is part of the input data. The controller includes a control unit that generates the register, a control signal for the memory, and an external output signal, and an address generation unit that increments and updates an address value from the register and generates an address to the memory, and the control unit A data value or a program template that is a part of the input data is stored in the memory based on the field information, an address value of the memory where the program template is stored is specified by the input data, and the data value is sequentially imported from the address generation unit. 1. A template reading circuit characterized in that the template of the program can be read out at high speed by generating an address that has been cleared, and can be sent to an external data flow calculation section.