JPH0354474B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) This invention utilizes a light-emitting light-receiving transistor,
The present invention relates to a light-emitting light-receiving device that also exchanges and controls information signals with internal storage cells and the outside.

(Prior Art) Conventionally, optical storage devices have had the disadvantage of slow information writing and reading speeds because they require mechanical operations, as seen in optical disk devices.

Furthermore, there have been proposals for memory using semiconductor lasers, and it is believed that ultra-high-speed memory devices are possible, but the device configuration requires extremely precise processing to manufacture, and the controllability of its use is also limited. However, it has the disadvantage that it is expected to be extremely difficult.

Furthermore, a device using a pnpn type negative resistance light-emitting light-receiving device has been considered, but it has several drawbacks such as difficulty in controlling its characteristics and use.

(Objective of the Invention) The present invention has been made to eliminate these conventional drawbacks. It is an object of the present invention to provide a light emitting/receiving device that can be easily controlled and internally utilizes optical signals and operations.

(Structure of the Invention) The light emitting/receiving device of the present invention turns on and off a first pair of light emitting/receiving transistors using an external electric control signal and a received light beam, and stores the results in a binary state.
A memory cell is configured to perform a read operation, and a second pair of light-emitting and light-receiving transistors is turned on and off in response to changes in the emitted light beam and relative bias potential of the first pair of light-emitting and light-receiving transistors. The light emitted from each light emitting/receiving transistor that performs reading and writing operations is transmitted through a light guide path.

(Example) Hereinafter, an example of the light emitting light receiving device of the present invention will be described based on the drawings. FIG. 1 is a schematic diagram of the first embodiment. Its configuration includes both electrical and optical elements. In the figure, Q ₁ to _{Q 4} are light-emitting and light-receiving transistors, which are made of compound semiconductors such as
It is made of - group compound semiconductors such as GaAs, AlGaAs, InP, and InGaAsP. Electrically, it has the same current amplification effect as a normal bipolar transistor, and optically, it has light receiving sensitivity over a wide wavelength range. This is a transistor that has a photoelectric conversion function and a current-optical exchange function that emits light in a relatively narrow wavelength range. Furthermore, when a large current is applied, laser light may be emitted near the base region.

The electrical circuit shown in FIG. 1 is constructed using a flip-flop circuit as a memory cell. Therefore, there are some electrical variations of this circuit that are commonly used.

Also, A ₁ , A ₃ , A ₅ are collector side bias terminals, A ₂ , A ₄ , A ₆ are emitter side bias terminals,
B ₁ and B ₂ are base side bias terminals.

Collector side bias terminals A ₁ , A ₂ , A ₃ , A ₅ are connected to horizontal common lines W ₁ , W ₂ ,
They are connected by W ₃ and W ₄ (word selection lines). Either or both of the common lines W ₁ and W ₂ may be used at the same time, and the common lines W ₃ and W ₄ may be used in common, and furthermore, they may be used in common with the common line W ₁ .

Emitter side bias terminals A ₄ and A ₅ are used for reading and writing digit lines (bit lines) D ₁ ,
It is connected to D ₁ and commonly connected to other cells in the vertical direction.

Although the base side bias terminals B ₁ and B ₂ are connected to the vertical common lines D ₂ and ₂ , they may be connected to the horizontal common line.

R ₁ to _{R 6} are electrical resistances that determine the electrical and optical operating conditions of the light emitting and receiving transistors Q ₁ to _{Q 4} , respectively. Furthermore, circuit modifications in which other resistors, diodes, and transistors are added are omitted for the sake of simplicity.

Base side bias terminal _B1 is connected via resistor _R5 ,
Connected to the base of the light emitting and receiving transistor _Q3 . The collector of this light emitting/receiving transistor _Q3 is connected to the collector side bias terminal _A3 via a resistor _R3 . Further, the emitter is connected to the emitter side bias terminal _A4 .

Similarly, the base side bias terminal B ₂ is connected to a resistor.
It is connected to the base of the light emitting/receiving transistor _Q4 through _R6 . This light emitting light receiving transistor _Q4
The collector of is connected to the collector side bias terminal _A5 via the resistor _R4 , and its emitter is connected to the emitter side bias terminal _A6 .

Furthermore, the light-emitting and light-receiving transistors Q ₁ and Q ₂ form the main body of the flip-flop circuit. The base of the light emitting and receiving transistor _Q1 is connected to the collector of the light emitting and receiving transistor _Q2 , and the base of the light emitting and receiving transistor _Q2 is connected to the collector of the light emitting and receiving transistor _Q1 .

The collectors of both the light emitting and receiving transistors Q ₁ and Q ₂ are connected to the collector side bias terminal A ₁ through resistors R ₁ and R ₂ respectively. It is connected to the emitter side bias terminal A ₂ of both the light emitting and receiving transistors Q ₁ and Q ₂ .

On the other hand, F ₁ , F ₂ , F ₃ , F ₄ are light guide paths (fibers)
For example, it is made of optical glass or transparent resin.

The light guide path F ₁ faces the light introduction or emission parts 32 and 34 (both shown in FIG. 3) of the light emitting/receiving transistors Q ₁ and Q ₃ .

The light guide path F ₂ faces the light introduction and emission sections 33 and 35 (both shown in FIG. 3) of the light emitting and receiving transistors Q ₂ and Q ₄ .

One end of the light guide path F ₃ faces the output light exit port I ₁ , and the other end faces the light introduction/emission section 34 of the light emitting/receiving transistor Q ₃ .

Furthermore, one end of the light guide path _F4 faces the output light exit port _I2 . The other end of the light guide path F ₄ faces the light introduction or emission section 35 of the light emitting/receiving transistor Q ₄ .

Optical filters _{G 1 ,
G2} is provided. This optical filter G ₁ , G ₂
This allows only a certain wavelength range to pass with low attenuation and blocks other wavelength ranges with high attenuation, and can be realized using an interference filter, a diffraction grating, an optical glass filter, or the like.

Note that C is a light emitting/receiving transistor Q ₁ , Q ₂ , Q ₃ ,
A light shielding part for optically insulating and separating Q ₄ from each other, and can be made of an optically absorbing material, such as an insulator such as black resin, liquid, powder, or black solid. Furthermore, the optical filters G ₁ and G ₂ are not essential.

Next, the operation of the light emitting/receiving device of the present invention configured as above will be explained. The light emitted from the light emitting/receiving transistors Q ₁ , Q ₂ enters the light emitting/receiving transistors Q ₃ , Q ₄ from the light guide paths F ₁ , F ₂ , respectively, and is detected as a light receiving current passing through the digit lines D ₁ , ₁ .

At the same time, the light emitting/receiving transistors Q ₃ and Q ₄ emit light in accordance with the light receiving current, so that the output light passes through the light guides F ₃ , F ₄ and the optical filters G ₁ , G ₂ to the output light ports I ₁ , I ₂ , it can also be detected as emitted light.

The wavelengths of light emitted from the light emitting and receiving transistors Q ₁ to _{Q 4} do not necessarily have to be the same wavelength, and the fact that they are different wavelengths may be utilized.

FIG. 2 is an example showing the circuit operation of FIG. 1 in chronological order. In this example, the common lines W ₁ , W ₃ ,
It is assumed that W ₄ is fixed at approximately the same positive potential, and that the base side bias terminals B ₁ and B ₂ are also at approximately the same positive potential.

Therefore, the operation of this circuit is almost determined by the potentials of the emitter side bias terminals A ₂ , A ₄ , A ₆ to which the common line W ₂ and the writing digital lines D ₁ , ₁ are connected.

In the steady state storage state, the potential of the emitter side bias terminal _A2 is kept slightly lower than the potential of the collector side bias terminal _A1 . At that time, the light emitting/receiving transistor Q ₁ connected to these terminals,
Since Q ₂ constitutes a flip-flop circuit,
One of them is on and the other is off.

Assume that the light-emitting and receiving transistor Q ₁ is on (light-emitting state) and the light-emitting and receiving transistor Q ₂ is off (quenching state). The horizontal axis in FIG. 2 indicates time, and it is assumed that during the time period _t0 to _t5 , the storage state is read out from _t1 to _t2 , and the write operation is performed during the time period _t3 to _t4 . The vertical axis indicates the relative potential of each terminal.

2a to 2c show a time series of relative potentials for a read operation, and FIGS. 2d to 2f show a time series of relative potentials for writing.

During readout (between _t1 and _t2 ), the potential of the emitter side bias terminal _A2 is made sufficiently lower than the potential of the collector side bias terminal _A1 , and the light emitting/receiving transistor _Q1
A large current is applied to the light emitting and receiving transistors Q ₃ , to increase the light emission intensity, and at the same time, the potential of the emitter side bias terminals A ₄ and A ₆ is slightly lower than the potential of the base side bias terminals B ₁ and B ₂ . Leave Q ₄ in a state somewhat close to shutoff.

As a result, the light emitted from the light emitting and receiving transistor _Q1 is received by the light emitting and receiving transistor _Q3 through the light guide path F1, and is amplified and detected as a light receiving _current on the writing digit line _D1 .

At the same time, since the light emitting/receiving transistor _Q3 emits light in accordance with this light receiving current, light can also be detected from the output light port _I1 through the light guide path _F3 and the optical filter _G1 .

On the other hand, since the light emitting/receiving transistor _Q2 is in the extinction state, no light passes through the light guide path _F2 . Therefore, the light receiving current of the light emitting and receiving transistor _Q4 ,
Since there is no detection current in the write digit line ₁ , this means that the off state has been detected.

During writing (between t ₃ and t ₄ ), the emitter side bias terminal A ₂ is the collector side bias terminal as well as during storage.
The potential of the emitter side bias terminals A ₄ and A ₆ , which should be kept at a potential slightly lower than that of A ₁ , should be sufficiently lower than the potential of either base side bias terminal B ₁ or base side bias terminal B ₂ , whichever one you want to turn on. A memory state can be created by

In this example, in order to turn on the light emitting/receiving transistor Q ₂ , the emitter side bias terminal A ₆
is sufficiently lower than the base side bias terminal B ₂ to cause the light emitting/receiving transistor Q ₄ to emit light, and the light is incident on the light emitting/receiving transistor Q ₂ through the light guide path F ₂ to turn on the light emitting/receiving transistor Q ₂ .
The light emitting/receiving transistor _Q1 is turned off.

The state where the light emitting/receiving transistor Q ₁ is on and the light emitting/receiving transistor Q ₂ is off is the logic "1" state, and the state where the light emitting/receiving transistor Q ₁ is off and the light emitting/receiving transistor Q ₂ is on is the "0" state. If they are made to correspond, the above-mentioned operations and states will mean that the functional state of binary logic is stored, and storage and operations such as reading and writing are possible. Figure 2a to Figure 2f
indicate this state, and
A ₁ , A ₂ , A ₄ , A ₆ , B ₁ , and B ₂ correspond to the symbols in FIG. 1, respectively, and indicate the potentials at those positions.

As you can see from the above explanation, the storage state, reading, and writing all depend on the relative potential between the terminals, so for example, the emitter side bias terminal A ₂ can be fixed and the collector side bias terminal A ₁ can be made variable. Alternatively, both can be made variable at the same time, or the emitter side bias terminal A ₄ ,
Reading and writing operations can also be performed by fixing A ₆ and making the base side bias terminals B ₁ and B ₂ variable.

However, even if the base side bias terminals B ₁ and B ₂ are changed, the detection current is the same as the write digit line.
A larger current can be obtained by using D ₁ and ₁ .

Some of these combinations will be omitted for simplicity.

FIG. 3 shows a cross-sectional view of an embodiment of a specific construction method corresponding to the schematic diagram of FIG. 1. Although resistors R ₁ to _{R 6} are not shown as external connections in this configuration example, they are connected to the compound semiconductor layer 1 inside or on the insulating compound semiconductor substrate 19 shown in this figure.
1 to 31 can be constructed within a single substrate using impurity diffusion, ion implantation, or the like.

In addition, it is possible to replace it with a transistor, diode, etc., as any equivalent resistance other than a pure resistor is required, but as this is not an essential requirement, detailed explanations of specific examples have been omitted for the sake of brevity. .

Compound semiconductor layers 11 to 31 in the figure constitute light emitting and receiving transistors Q ₁ to _{Q 4} . The insulating compound semiconductor substrate 19 is made of, for example, GaAs or InP, and light emitting/receiving transistors Q ₁ to _{Q 4} are formed on it.
are simultaneously configured on a single substrate.

On the insulating compound semiconductor substrate 19 are compound semiconductor layers 14, 18, 23, 27 forming the collector portions of the respective light emitting/receiving transistors _Q1 to _Q4 , and compound semiconductor layers 13, 1 forming the base portions thereon.
7, 22, 26, compound semiconductor layers 12, 16, 21, 25 forming emitter portions, compound semiconductor layers 11, 15, 2 as contact layers to enable good ohmic connection of emitter electrodes.
0.24 is grown epitaxially.

Next, the same p as the base layer to take out the base electrode from the top (n in the case of a pnp transistor)
Compound semiconductor layer 2 as a layer in which impurities of the form are altered using a diffusion method, an ion implantation method, etc.
8, 29, 30, and 31 are formed up to compound semiconductor layers 13, 17, 22, and 26 as base layers.

After that, a part of the emitter part is removed by chemical or physical mesa etching, or by insulation using ion implantation method, a part of the emitter base is insulated and light is introduced into the base layer or the light emitting part 32, 33. , 34, 35 are formed.

Further, portions 36 and 37 also indicate optical coupling portions between the light emitting and receiving transistors Q ₁ and Q ₃ and between Q ₂ and Q ₄ . Therefore, this part may be simply a vacuum or a gas, but it is preferably a resin, liquid, or solid that is transparent at each wavelength of input and output light and has a refractive index as close to that of the semiconductor or light guide as possible. It consists of:

Thereafter, etching is performed to provide collector electrodes of the light emitting and receiving transistors Q ₁ to _{Q 4} and etching to electrically insulate the light emitting and receiving transistors Q ₁ to _{Q 4} from each other.

Thereafter, ohmic electrodes for each layer are added using a vapor deposition method, a plating method, a sintering method, or the like.

Generally, it is desirable that the compound semiconductor layers 12, 16, 21, 25 as emitter layers have a larger energy gap than the compound semiconductor layers 13, 17, 22, 26 as base layers, thereby reducing the fractional carrier from the emitter. injection efficiency can be improved.

For example, a compound semiconductor layer 1 as a base layer
3, 17, 22, 26 are made of GaAs or InP, compound semiconductor layer 1 as an emitter layer
For example, AlGaAs or InGaAsP is used for 2, 16, 21, and 25, respectively.

Moreover, if this is done at the same time, the emitter layer can be made optically transparent to the wavelength of light to be absorbed by the base layer, making it possible to further enhance the photoelectric conversion efficiency.

The compound semiconductor layers 11, 15, 20, 24 as emitter contact layers are essentially unnecessary, but the compound semiconductor layers 12, 1 as emitter contact layers are essentially unnecessary.
It is used as an auxiliary layer when it is difficult to attach ohmic electrodes directly to 6, 21, and 25.

Compound semiconductor layers 13, 17 as base layers,
Generally, the compositions 22 and 26 are the same and are made at the same time, but if it is desired to variously change the wavelength characteristics for input and output light, they are made to have different compositions.

This can be achieved, for example, by changing the composition of the base material crystal using selective epitaxial growth, or by selectively diffusing impurities after growing a crystal with the same composition or modifying it using ion implantation. be.

In addition, this base layer is used as a light emitting/receiving transistor.
This layer has a particularly important effect on the electrical and optical properties of Q ₁ to _{Q 4} , and particularly desirable properties are often obtained when a group element is used as an impurity for - group compound semiconductors.

That is, characteristics such as a long minority carrier diffusion length and high exchange efficiency for light emission or light reception can be obtained.

Furthermore, part C in the figure is a light emitting/receiving transistor.
A substance for providing mutual optical and electrode insulation between Q ₁ to _{Q 4} and light guide paths F ₁ to _{F 4} , and is made of the above-mentioned material, and is similar to the light shielding part described in Fig. 1. It is. This makes it possible to separate the input and output and at the same time avoid malfunctions of the light-emitting and light-receiving transistors.

In addition, although the figure shows a structure in which all the light guide paths F ₁ to _{F 4} are taken out from the top, it is also possible to attach them to the lower part of the insulating compound semiconductor substrate 19, or especially when emitting laser light. It is desirable to install light guide paths F ₁ to _{F 4} for output extraction in the lateral direction.

Further, although the light shielding part C is added only to the upper part of the semiconductor part, it is preferable to add it also to the lower part and the lateral part in order to achieve more complete optical shielding.

Note that the optical filters G ₁ and G ₂ are omitted as external connections for simplicity.

FIG. 4 is a schematic diagram of a partially modified embodiment of the configuration example of FIG. 1. Figure 4a shows a form (Qi, Q'i) in which a larger amplification factor and input impedance are obtained by connecting some or all of the light emitting/receiving transistors Q ₁ to _{Q 4} in Figure 1 to Darlington connections (Qi, Q'i). This is an example in which the configuration is changed to .

Further, FIG. 4b shows another embodiment in which a diode Di is added between the base and collector of the light-emitting and light-receiving transistor shown in FIG.

This diode Di is a Schottky barrier diode or a normal p-n junction diode which has a forward voltage drop smaller than the forward voltage drop between the base and collector of a transistor, for example, a semiconductor material with a smaller energy gap than the material of the base collector. It consists of the diode used.

This eliminates the inflow of an excessive base drive current of the light emitting/receiving transistor, reduces excessive minority carrier injection, and has the advantage that the switching time delay due to the accumulation effect is significantly shortened.

FIG. 4a and FIG. 4b have mutually independent concepts, and therefore, they may be used in combination. Structural diagrams for specific configurations are omitted for the sake of simplicity.

5 and 6 are schematic diagrams of other embodiments that are modified from the embodiment of FIG. 1. In this embodiment, the light-emitting and light-receiving transistors Q ₁ ,
Only the flip-flop type memory cell section composed of Q ₂ is modified, and a resistor R ₃ is simply added to the collector section (in the case of FIG. 5) or the emitter section (in the case of FIG. 6). The other parts are the same as those in FIG. 1, so they are shown in a simplified manner.

By doing this, high resistance resistance
When R ₃ is inserted, the light emitting/receiving transistors Q ₁ and Q ₂ can operate in a non-saturated manner, allowing higher speed operation than in the saturated type operation shown in FIG. The storage operation and configuration example are the same as in the case of FIG. 1, so a description thereof will be omitted.

As explained above, in each of the above embodiments, the active elements of the light-emitting and light-receiving transistors have multi-functional characteristics in terms of electro-optics, so a large number of them can be constructed on the same substrate with a relatively simple circuit and simple configuration. It is.

In addition, it has the advantage of being easily electrically controllable, and since the memory cell and drive circuit use optical input/output signals, it can operate in a completely electrically isolated state from other circuits. , has great advantages in its independence and controllability.

Therefore, these devices can be connected in parallel and in series, and can be integrated in large numbers on the same plane.

In addition, although each of the above-mentioned embodiments shows only an example using an npn type light emitting/receiving transistor, it is easily possible to implement the structure in a similar manner with a pnp type, so the description is omitted.

(Effects of the Invention) As described above, according to the light emitting/receiving device of the present invention, the first
The first pair of light emitting and receiving transistors is turned on and off to form a memory cell that performs storage and read operations in a binary state, and changes in the emitted light beam and relative bias potential of the first pair of light emitting and receiving transistors are performed. The second pair of light emitting/receiving transistors is turned on and off in response to the reading and writing operations of the memory cell, so that the optical storage circuit device is simple and has multifunctionality and controllability. can exhibit the following functions. Accordingly, it can be widely applied to various devices such as other optical comparators, delay circuits, optical sweep circuits, optical sensors, display circuits, mixing, amplification, and oscillation circuits.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the configuration of an embodiment of the light emitting and receiving device of the present invention, and FIGS. 2a to 2f are diagrams chronologically showing the operation of the light emitting and receiving device of FIG. 1, respectively. FIG. 3 is a cross-sectional view of a main part showing the structure of the light-emitting and receiving device of FIG. 1, FIG. 4a is a circuit diagram when the light-emitting and receiving transistors in the light-emitting and receiving device of the present invention are connected in Darlington, and FIG. 4b is is a circuit diagram in which a diode is clamp-connected between the base and collector of the light-emitting and light-receiving transistor in the light-emitting and light-receiving device of the present invention, and FIGS. 5 and 6 are schematic diagrams showing other embodiments of the light-emitting and light-receiving device of the present invention, respectively. It is a diagram. Q ₁ to Q ₄ , Qi, Q′i……light emitting light receiving transistor,
_R1 to _R6 ...Resistor, C...Light shielding part, F1 _{to F4} ...Light guide path, _G1 , _G2 ...Optical filter, Di...Diode, 11-31...Compound semiconductor layer, 19 ……
Insulating compound semiconductor substrate, 32-35... Light introduction or emission part, 36, 37... Optical coupling part.

Claims (1)

[Claims] 1 A first pair of light-emitting and light-receiving transistors constituting a memory cell that is turned on and off by an external electrical control signal and a light-receiving light beam, emitting light when on and extinguishing when off, exhibiting a storage and read function in a binary state; , a first pair of light guide paths for transmitting the light emitted from the first pair of light emitting/receiving transistors;
The emitted light beams transmitted through the first pair of light guide paths emit light individually, and the emitted light beams are detected as a received light current, and are turned on and off by relatively changing the bias potential to be sent to the memory cell. The second one performs read and write operations of
A pair of light-emitting and light-receiving transistors, a second pair of light guide paths that transmit the light emitted from the second pair of light-emitting and receiving transistors to the outside, and each light-emitting and receiving transistor is integrally formed with each of the above-mentioned light-emitting and light-receiving transistors. A light-emitting light-receiving device consisting of a light-shielding part that optically shields a transistor.