JPH0354475B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of configuring a matrix array, and more particularly to a method of configuring a matrix array with high electrostatic resistance.

As electronic devices become smaller every year, display devices as peripheral devices also become lighter and smaller.
Various types of flat display panels have been researched as an alternative to CRTs, and are now on the market. Most of the construction methods for such flat display panels, especially for large-capacity panels, are matrix array types using switching elements, and the following is a typical example of the array construction. Figure 1 is a and b. This is taken as an example of an active matrix array liquid crystal display device, and in figure a,
It is composed of a plurality of source lines 3, a plurality of gate lines 4 perpendicular to the source lines 3, and a nonlinear element 2 connected to the intersection of these source lines and gate lines. This is formed on one glass substrate, and a liquid crystal is interposed between this substrate and a substrate on which a common electrode is formed on the entire surface, thereby producing a liquid crystal display panel. Figure 1b
shows a specific example of the nonlinear element 2 of a, and a MOS transistor 5 is used as the nonlinear element.
It uses The source electrode of the transistor is connected to a source line 3, the gate electrode is connected to a gate line 4, and the drain is further connected to a charge storage capacitor 6 and a liquid crystal display cell 7. Here, MOS type transistors are susceptible to static electricity, and the gate insulating film is easily destroyed by static electricity.If static electricity enters the source line and gate line of the matrix array, static electricity voltage is applied directly to the gate insulating film, which causes damage to the gate insulating film. Transistors in the position are also easily destroyed when static electricity is applied. Furthermore, since the substrate forming the array is glass, it is an insulator, and as can be seen from Figure 1a, both the source line and the gate line are extended to the outside of the matrix array area for electrical connection. So,
When exposed to static electricity, charges concentrate on conductive source or gate lines, and from this point of view, matrix arrays on insulating substrates are susceptible to static electricity. Furthermore, since it is an insulating substrate, it is difficult for the charges accumulated on the substrate to escape, and if a conductor such as a human body is connected to the source line of the substrate,
If it comes into contact with the gate line, the charge will instantly escape, leading to destruction in this case as well. Therefore, when handling the substrate, sufficient care must be taken to prevent the generation of static electricity, and an atmosphere must always be maintained in which the charges accumulated on the substrate can spontaneously discharge into the air. As mentioned above, when an active matrix array using nonlinear elements is constructed on a glass plate, which is an insulator, it is extremely susceptible to static electricity and is difficult to handle.
Large problems arise in mass production, such as fluctuations and declines in yield.

The present invention has been made in view of the above-mentioned drawbacks, and its object is to provide a matrix array with improved electrostatic resistance.

The present invention will be explained in detail below with reference to the drawings. Second
The figure shows an example of a cross section of a MOS transistor. Polycrystalline silicon 9, which is a semiconductor material, is formed on the surface of glass 8 and patterned. Next, a gate insulating film 10 is formed covering at least the polycrystalline silicon 9, and a gate material 11 of the transistor is formed thereon. This gate material 11 is further extended left and right to form a gate line 4. Next, the gate insulating film not covered with the gate electrode 10 is removed, and boron or phosphorus is diffused into the exposed region of the polycrystalline silicon 9 to form the source 9- of the transistor.
1. Drain 9-2. Next, an insulating film 12 is formed on the entire surface, and the insulating film 12 is formed on the source and drain regions.
2 is removed by etching and a contact hole is opened as shown in the drawing. Finally, aluminum 13 is formed and patterned to complete the manufacture of the MOS transistor. The aluminum wire connected to the source of the transistor is extended perpendicularly to the drawing to form the source line 3, and the aluminum wire 13 connected to the drain of the transistor is connected to the capacitor 6 and the liquid crystal as shown in FIG. 1b. It is connected to cell 7. FIG. 3 shows an example in which the MOS transistors of the example shown in FIG. 2 are arranged in a matrix array, and resistors are arranged outside the matrix region of the source line and gate line.

There are 3 source lines, 4 gate lines, and 2 MOS transistors. A resistor 15 is connected to the outside of the source line 3, and a resistor 14 is connected to the outside of the gate line 4.

The line resistance when aluminum is used for the source line is that the specific resistance of the aluminum thin film is approximately 5×
10 ^-6 Ω·m, so if the film thickness is 1 micrometer, the sheet resistance is 5×10 ^-2 Ω/mouth.
If the size of the display panel is 5 cm square and the aluminum wire width of the source is 10 microns, then the resistance will be 250 ohms. FIG. 4 shows a method of connecting a resistor to this source line. At the same time as forming the second gate 11, a resistor is fabricated at the position 15 in FIG. If the gate material in No. 11 is polycrystalline silicon, and if boron or phosphorus is diffused during pre-deposition at 1000 degrees, the sheet resistance (film thickness is
3000 angstrom) is 50 to 100 Ω/mouth. Therefore, a width of 10 micrometers and a length of 200 micrometers can provide a resistance of more than 1 kilohm. Here, the effects of the electrostatic protection resistor will be described based on the results of experiments conducted by the present inventor. The experiment consisted of storing charges at various voltages in a 100 picofarad capacitor, discharging this charge into each source line, and counting the number of transistors destroyed. Figure 5 shows the results; the horizontal axis shows the voltage charged to the 100 picofarad capacitor, and the vertical axis shows the number of transistors destroyed. First, if you do not include a resistor, destruction will occur at 300 volts, and increasing the charging voltage will rapidly destroy the number of transistors. On the other hand, when a resistor of 5 kilohms is inserted, the voltage at which breakdown occurs increases approximately twice, and the rate at which the number of breakdowns increases also decreases when the voltage is increased above the breakdown starting voltage. This graph shows that the effect begins to appear when the resistance value of the externally inserted resistor is around 1 kilohm, and as the resistance value increases, the breakdown resistance increases. This is thought to be because the time for static electricity received by the resistor to reach the matrix region is delayed, and furthermore, the rate of increase in the voltage applied to the transistor is slowed down. By the way, even if you increase the voltage applied to the line from 0 volts to 80 volts in about 10 seconds without attaching a protective resistor, no damage will occur, so the damage is not caused by the absolute value of the voltage, but by the electrostatic transistor. It can be seen that the rising speed of the voltage applied to is important. The effect is the same whether such a protective resistor is connected not only to the source line but also to the gate line, and the resistor in Figure 4 is not only the gate material of the MOS transistor, but also the polycrystalline resistor in Figure 2. Even if a layer of silicon 9 is used, it can be manufactured and the effect will not change in any way.

Furthermore, although the present invention can be applied not only to the liquid crystal display panel as described above but also to other display panels, the effect is most effective when a matrix array is constructed on an insulating substrate. Applicable matrix arrays are not only effective when source lines and gate lines are on the same substrate, but also matrix arrays in which source lines are configured on one substrate and gate lines on the other substrate. In that case, electrostatic protection must be applied to the wires to which the nonlinear elements are connected.

As described above, in a matrix array substrate including a plurality of gate lines and a plurality of source lines orthogonal to the gate lines, and in which a nonlinear element is formed at each intersection of the gate lines and the source lines, At least one of the plurality of gate lines or the plurality of source lines includes, for each of the plurality of lines, outside the matrix array area on the signal input side of the gate line or the source line.
By inserting a resistor made of an impurity-containing polycrystalline Si layer, the electrostatic withstand capacity is greatly improved, and damage to nonlinear elements due to static electricity is greatly reduced, making it possible to provide highly reliable liquid crystal display devices. Furthermore, since the resistor is formed of a polycrystalline Si layer,
A high-resistance resistor can be obtained, and polycrystalline Si, which is the gate electrode that constitutes the nonlinear element, can be used.
This has the effect that even if a resistor is manufactured, the cost does not increase.

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional structure of a matrix array. FIG. 2 is a sectional view of an example of the structure of a MOS transistor, and FIG. 3 shows an example of the structure of a matrix array in which the present invention is implemented. FIG. 4 is a sectional view of an example of the structure of the protective resistor of the present invention. FIG. 5 shows experimental data showing the effect of protective resistance.

Claims (1)

[Claims] 1. In a matrix array substrate comprising a plurality of gate lines and a plurality of source lines orthogonal to the gate lines, and a nonlinear element is formed at each intersection of the gate lines and the source lines, At least one of the gate line or the plurality of source lines is provided with a resistor made of an impurity-containing polycrystalline Si layer outside the matrix array region on the signal input side of the gate line or the source line for each of the plurality of lines. A matrix array board characterized by inserting.