JPH0354490B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter, and more particularly to a series-parallel type analog-to-digital converter.

A conventional serial/parallel type analog-to-digital converter includes two analog-to-digital converters 1 and 2 (hereinafter referred to as ADC) and a digital-to-analog converter 3 (hereinafter referred to as DAC) as shown in Figure 1. , a sample and hold circuit 5 (hereinafter abbreviated as S/H), a delay circuit 6, and the like. Analog input signal 100 is sampled and held by S/H5,
The upper bit is AD converted by ADC1. ADC
The output of 1 is latched into register 71 and output to DAC3.
is converted into an analog value corresponding to the upper bit, and the delay circuit 6 outputs the ADC 1 and the register 71.
The subtraction circuit 4 obtains the difference between the analog input signal and the analog input signal delayed by the time required for the DDAC 3. This value is AD converted as the remaining lower bit by ADC2, the digital sum of the output of ADC1 and the output of ADC2 is taken, and this is output as a digital signal corresponding to the analog input signal sampled and held by S/H5. It is something to do.
In the figure, 72 is a register that latches the AD conversion value of the upper bit (output of ADC 1) until the lower bit is AD converted by ADC 2, and 73 is a register that latches the AD conversion value of the lower bit (output of ADC 1).
This is a register that latches the output (output of 2). In this method, when the subsequent ADC2 starts converting,
The conversion speed can be increased because the ADC 1 in the previous stage starts AD converting the next sample value in a so-called traveling wave type, but it is necessary to delay the analog input signal by the delay circuit 6 to match the timing with the output of the ADC 3. Coaxial cable delay lines, LC filters, etc. are usually used to delay this analog input signal, but this requires a large amount of driving power, the signal is distorted when passing through the delay line, and waveform distortion due to the termination is a problem. However, there were drawbacks such as difficulty in adjusting the delay time.

An object of the present invention is to provide a high-speed and stable analog-to-digital converter without using a delay circuit having such drawbacks.

The present invention realizes a series-parallel type ADC without using a delay circuit by using multiple S/Hs and switching their outputs in a time-divisional manner using an analog switch and using them as inputs for the preceding and succeeding ADCs. It is something to do.

Hereinafter, the present invention will be explained in detail with reference to Examples.
The first embodiment is shown in FIG. 2, and its time chart is shown in FIG. First, the S/H51 enters the sample mode with logic "1" by the control signal φ _H1 ,
Analog input signal 100 is sampled and held at logic "0". At this time, the analog switch (hereinafter abbreviated as ASW) 811 is closed at logic "1" by the control signal φ _S1 , and the ASW 812 is opened at logic "0" by the control signal φ _S1 . Therefore
The output of the S/H 51 is connected to the ADC 1, and AD conversion of the upper bits is performed on the value.
After AD conversion, the digital value latched in the register 71 is subjected to DA conversion by the DAC 3. At this time, the S/H 52 samples and holds the analog input signal using φ _H2 . Along with this, ASW811,
812 has reverse opening and closing due to φ _S1 and _S1 , and ADC
The input of 1 is connected to the S/H 52, and the ADC 1 starts AD converting the next analog signal. on the other hand,
In the ASWs 821 and 822, the output of the S/H 51 is connected to the input of the subtracter 4 by the control signals φ _{S2 and S2} , and the difference with the output of the DAC 3 is determined. This difference signal is input to the subsequent ADC2, and the lower bit of
AD conversion is performed, and the AD conversion of the analog input value sampled by the S/H 51 is completed for all bits. After that, ASW821,82
2, the opening and closing are reversed by the control signals φ _S2 and _S2 ,
Subtractor 4 is connected to S/H52,
AD conversion of the upper bit of the input signal held at
The subtracter 4 calculates the difference between the latch and the DA converted value. In this way, each S/H needs to hold an analog input value from the time when the ADC 1 in the preceding stage starts AD conversion of the upper bits until the AD conversion of the lower bits by the ADC 2 in the succeeding stage is completed. Furthermore, since S/Hs 51 and 52 each perform sampling and holding with different phases, while DAC3, subtracter 4, and ADC2 are operating, ADC1 is sampling and holding the next analog input signal. It is possible to perform a traveling waveform operation that performs AD conversion, and high-speed AD conversion is possible. In addition, in Figure 2, 7
2 is a register that latches the AD conversion value of the upper bit until the lower bit is AD converted by the ADC 2, and the output of this register becomes the upper bit of the converter output of the AD converter. Reference numeral 73 is a register that latches the AD converted value of the lower bit, and the output of this register becomes the lower bit of the converter output of the AD converter. In other words, the outputs of both these registers are combined to obtain a conversion output with a desired number of bits. Also, in Figure 3,
LE1, LE2, and LE3 are latch controls for registers 71, 72, and 73, respectively;
In FIG. 3, it is assumed that the signal is latched when the logic changes from "1" to "0". Further, in FIG. 3, ADC1 and ADC2 indicating the conversion status of the ADC are shown as logic "1", indicating that AD conversion is being performed.

Although the first embodiment described above shows an example in which two sample and hold circuits are used, the same operation can be performed even if three sample and hold circuits are used. An example thereof is shown in FIG. 4, and a time chart thereof is shown in FIG. As in the case of the first embodiment, the S/H is set to the sample mode when the control signal is logic "1", and the ASW is closed when the control signal is logic "1". First, when the S/H51 changes from sample to hold mode by the control signal φ _H1 , the ASW 811 closes by the control signal φ _S11 .
The output of S/H51 is connected to ADC1, and ADC1
is the analog input signal held in S/H51.
AD convert. At this time, the S/H 52 is in the sample mode by the control signal φ _H2 and samples the next analog input signal. S/H51
of the upper bit of the analog input signal held at
When AD conversion is completed, ASW switches and ASW
812 is closed by the control signal φ _S12 , and ADC1
The output of the S/H 52 is connected to the ADC 1, and the ADC 1 starts AD conversion of the upper bit of the next sample value held in the S/H 52. At this time, the first AD-converted value is latched in register 71, and DA conversion is performed for the upper bits of DAC3.
The subtracter 4 calculates the difference with the value held in the S/H 51 connected by the ASW 821, and the ADC 2 performs AD conversion of the lower bits. In this way, similar to the first embodiment, high-speed
AD conversion becomes possible. Here, the difference from the first embodiment is that since there are three S/Hs, the sampling time can be taken longer than in the first embodiment. This is a major advantage in sample-and-hold circuit design, which is difficult to maintain accuracy and speed. Here, S/H
Although the case where there are three circuits has been described, it is clear that the same operation can be performed in the case of three or more circuits.

The above two embodiments have two stages: a front stage and a rear stage.
Although this is an example of a configuration using an ADC, a series-parallel AD converter can also be realized by combining a sample-and-hold circuit and an analog switch in the case of a multi-stage configuration. As an example, a three-stage configuration is shown in FIG. 6, and a time chart thereof is shown in FIG. 51-53 are S/H, 811-813,8
21-823, 831-833 are ASW.
The operation is similar to the first and second embodiments above, but
First, the input signal sampled and held by S/H51 is changed by closing ASW811.
It is connected to the ADC 11, and AD conversion of the upper bits is performed. Its value is latched in register 71,
The DAC 31 performs DA conversion, and by closing the ASW 821, the subtracter 41 calculates the difference from the input signal. While this DA conversion is being performed,
ASW811 is open, ASW812 is closed,
The ADC 11 AD converts the next input signal sampled and held by the S/H 52. On the other hand, the difference signal obtained by the subtracter 41 is subjected to AD conversion corresponding to the middle bit by the second ADC 12, and its digital output is latched in the register 73. 2
The digital values obtained by the two ADCs 11 and 12 are input to the second DAC 32 corresponding to each bit, and DA conversion is performed on the AD conversion results of the upper and middle bits. That DAC32
The subtracter 42 takes the difference between the output of the subtracter 42 and the input signal held in the S/H 51, and the third ADC 13 performs AD conversion of the lower bits of the difference output. During this time, the second ADC 12 is performing AD conversion on the next difference output, and in this way, the AD conversion results are sequentially stored in registers 74 and 7.
5 and 76, it is obtained as a traveling waveform. In the time chart shown in FIG. 7, the S/
The H control signals φ _H1 to φ _H3 indicate the sample state at logic “1”, and the ASW control signals φ _SA1 to φ _SA3 , φ _SB1 to _{φ SB3} ,
φ _SC1 to _{φ SC3} are closed when the logic is "1" and open when the logic is "0". In addition, latch control signals LE1 to LE6 and ADC11 and ADC1 indicating the conversion status of the ADC are also provided.
2. The ADC 13 is described in the same manner as in the first and second embodiments. Although the case of three stages has been described above, if the number of S/Hs and ASWs is increased, a further multi-stage configuration is also possible.

According to the present invention, a series-parallel type AD converter can be realized without the need for a delay circuit, thereby reducing the large drive power and adjustment effort associated with the use of a delay circuit, and eliminating signal distortion. It becomes possible to realize a precision ADC. Furthermore, coaxial cables and LC circuits are generally used as delay circuits, but these are not suitable for LC. In the present invention, since these are not used, the effect is great for LC conversion as well.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining a conventional series-parallel AD converter, FIG. 2 is a configuration diagram showing a first embodiment of the present invention, and FIG. 3 is a time chart of the embodiment of FIG.
4 is a block diagram showing a second embodiment of the present invention, FIG. 5 is a time chart of the embodiment of FIG. 4, FIG. 6 is a block diagram showing a third embodiment of the present invention, and FIG. The figure is a time chart of the embodiment shown in FIG. 1, 2, 11, 12, 13...AD converter,
3, 31, 32...DA converter, 5, 51, 5
2,53...Sample hold circuit, 811,8
12,813,821,822,823,83
1,832,833...Analog switch.

Claims (1)

[Claims] 1. A first analog-to-digital converter for converting an analog input signal into a digital signal and using it as the upper bit of the converter output, and converting the output of the first analog-to-digital converter into a digital signal again. a calculation means for converting the signal into an analog signal and calculating a difference from the analog input signal; and a second analog-to-digital conversion means for converting the output of the calculation means into a digital signal and using it as the lower bit of the converter output. and which synthesizes the outputs of the first and second analog-to-digital conversion means to produce a converter output, wherein the analog input signal is sequentially sampled and held at different phase timings. a plurality of sample and hold means for obtaining a plurality of hold outputs; a first switching means for sequentially switching the plurality of hold outputs and sequentially connecting the plurality of hold outputs to the first analog-to-digital conversion means;
and second switching means for sequentially switching the plurality of hold outputs and sequentially connecting them to the calculation means, wherein the second switching means selects one hold output and connects it to the calculation means. During the period in which the calculation means calculates the difference between the value obtained by converting the output of the first analog-to-digital conversion means corresponding to the one hold output into an analog signal and the connected hold output, An analog-to-digital converter, characterized in that the first switching means connects another hold output to the first analog-to-digital converting means. 2 The outputs of the first and second analog-to-digital conversion means are latched in sequence, so that the upper bits of the converter output corresponding to one hold output and the lower bits of the converter output corresponding to one hold output are within the same period. 2. The analog-to-digital converter according to claim 1, further comprising register means for holding the data.