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JPH0355438B2 - - Google Patents
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JPH0355438B2 - - Google Patents

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Publication number
JPH0355438B2
JPH0355438B2 JP29257485A JP29257485A JPH0355438B2 JP H0355438 B2 JPH0355438 B2 JP H0355438B2 JP 29257485 A JP29257485 A JP 29257485A JP 29257485 A JP29257485 A JP 29257485A JP H0355438 B2 JPH0355438 B2 JP H0355438B2
Authority
JP
Japan
Prior art keywords
etching
substrate crystal
hcl
vapor phase
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP29257485A
Other languages
Japanese (ja)
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JPS62153198A (en
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Filing date
Publication date
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Priority to JP29257485A priority Critical patent/JPS62153198A/en
Publication of JPS62153198A publication Critical patent/JPS62153198A/en
Publication of JPH0355438B2 publication Critical patent/JPH0355438B2/ja
Granted legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、−族化合物半導体の非常に精密
に制御された気相エツチング方法に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a highly precisely controlled vapor phase etching method for -group compound semiconductors.

〔従来技術とその問題点〕[Prior art and its problems]

GaAs、InP等のような−族化合物半導体
の気相エピタキシヤル成長結晶は、発光ダイオー
ド、レーザダイオードのような光デバイスや、
FETのようなマイクロ波デバイスに広く応用さ
れている。ところで、基板結晶上に気相成長によ
りエピタキシヤル成長を行なう場合、基板結晶の
エツチングを行なうのが普通である。このエツチ
ングには、基板結晶を反応管にセツトする前に行
なう溶液によるケミカルエツチングと、反応管に
セツト後成長直前に行なう気相エツチングとがあ
る。前者は主として基板結晶表面に残つている鏡
面研磨の際に発生した破壊層を取り除くのが目的
であり、後者は主としてケミカルエツチング後か
ら反応管にセツトするまでの間に表面に形成され
た酸化膜や、ゴミなどの付着した不純物を除去し
たり、昇温の間に形成された変成層を除去するの
が目的である。この気相エツチングが十分でない
と、表面上に残つた酸化膜や微小ゴミ等が核とな
り、ヒルロツク等の表面欠陥の非常に多い成長面
となる。また、エピタキシヤル層と基板結晶の界
面にデイツプ層と呼ばれるキヤリア濃度の非常に
低下した部分が生じたりする。これらは何れもデ
バイス作製上、有害なものである。従つて、この
気相エツチングは結晶成長上欠かせないプロセス
である。
Vapor phase epitaxially grown crystals of - group compound semiconductors such as GaAs and InP are used for optical devices such as light emitting diodes and laser diodes,
It is widely applied to microwave devices such as FETs. By the way, when epitaxial growth is performed on a substrate crystal by vapor phase growth, the substrate crystal is usually etched. This etching includes chemical etching using a solution, which is carried out before the substrate crystal is set in the reaction tube, and vapor phase etching, which is carried out after setting the substrate crystal in the reaction tube and immediately before growth. The purpose of the former is mainly to remove the destructive layer that remains on the surface of the substrate crystal during mirror polishing, and the purpose of the latter is mainly to remove the oxide film formed on the surface after chemical etching until it is set in the reaction tube. The purpose is to remove attached impurities such as dirt and dust, and to remove metamorphic layers formed during temperature rise. If this vapor phase etching is not sufficient, the oxide film, minute dust, etc. remaining on the surface become nuclei, resulting in a growth surface with many surface defects such as hillocks. Further, a portion called a dip layer where the carrier concentration is extremely reduced may be formed at the interface between the epitaxial layer and the substrate crystal. All of these are harmful to device fabrication. Therefore, this vapor phase etching is an essential process for crystal growth.

ところで、最近では、結晶の一部を選択的にエ
ツチングし、そこに改めて周りの結晶とは電気
的、光学的に性質の異なるエピタキシヤル層の成
長を行なう選択成長が行われている。この場合に
はエツチング深さの精密な制御が要求される事が
多い。例えば、GaAs FETに於けるソースとド
レイン部の電極形成用コンタクト層の成長を例に
とると、従来の一般的な方法では、選択エツチン
グにはSiO2等のマスクを通した溶液によるケミ
カルエツチングが主として用いられてきた。しか
し、この方法ではデバイスから要求されるエツチ
ング深さの精密な制御が困難であり、更に、ケミ
カルエツチング後、空気中に取り出し基板結晶の
反応管へのセツトを行なうため、前述したよう
に、エピタキシヤル層と基板結晶の界面にデイツ
プ層と呼ばれるキヤリア濃度の非常に低下した部
分が生じたりする。これもコンタクト層にとつて
非常に望ましからざる現象であつた。
Incidentally, recently, selective growth has been carried out in which a part of a crystal is selectively etched and an epitaxial layer having different electrical and optical properties from the surrounding crystal is grown thereon. In this case, precise control of the etching depth is often required. For example, when growing a contact layer for forming source and drain electrodes in a GaAs FET, conventional selective etching methods involve chemical etching using a solution through a mask such as SiO 2 . It has been mainly used. However, with this method, it is difficult to precisely control the etching depth required by the device, and furthermore, after chemical etching, the substrate crystal is taken out into the air and set in the reaction tube, so it is difficult to perform epitaxy as described above. At the interface between the carrier layer and the substrate crystal, a portion called a dip layer where the carrier concentration is extremely reduced may occur. This was also a very undesirable phenomenon for the contact layer.

従来の気相エツチングを、第4図に示したハイ
ドライド気相成長法を用いて説明する。GaAsの
成長を例に取ると、反応管1の上流にGaソース
ボート9を置き、その上流からH2キヤリヤガス
と共にHClガスを供給する。この結果、GaClが
生成され下流に運ばれる。また、Gaソースボー
ト9をバイパスするパイプ2からAsの水素化物
であるAsH3をH2キヤリヤガスと共に供給する。
この両者のガスが基板結晶3の領域で混合し成長
が起こる。気相エツチングはバイパスパイプ2か
らHClガスを供給することによつて行ない、Ga
輸送用のHClガスとの比を調整することによつて
そのエツチング速度を制御していた。しかしなが
ら、この従来方法では、基板結晶温度、Ga輸送
用のHClガス流量、あるいはAsH3流量等成長条
件にエツチング速度が大きく影響され、デバイス
作製上要求される精度を持つてエツチング深さを
制御することは不可能であつた。
Conventional vapor phase etching will be explained using the hydride vapor phase growth method shown in FIG. Taking the growth of GaAs as an example, a Ga source boat 9 is placed upstream of the reaction tube 1, and HCl gas is supplied together with H2 carrier gas from the upstream side. As a result, GaCl is produced and transported downstream. In addition, AsH 3 which is a hydride of As is supplied from the pipe 2 that bypasses the Ga source boat 9 together with the H 2 carrier gas.
These two gases mix in the region of the substrate crystal 3 and growth occurs. Gas phase etching is performed by supplying HCl gas from bypass pipe 2, and Ga
The etching rate was controlled by adjusting the ratio with HCl gas for transport. However, in this conventional method, the etching rate is greatly affected by growth conditions such as substrate crystal temperature, HCl gas flow rate for Ga transport, or AsH 3 flow rate, and it is difficult to control the etching depth with the accuracy required for device fabrication. That was impossible.

また、エツチングの深さも上流部が大きく、下
流部が小さいというように不均一性が大きかつ
た。
Furthermore, the etching depth was large in the upstream part and small in the downstream part, so there was great non-uniformity.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、−族化合物半導体の気相
エツチングおいて、従来のかかる欠点を除去し、
エツチング深さの精密な制御が可能な気相エツチ
ングの方法を提供しようとするものである。
The purpose of the present invention is to eliminate such conventional drawbacks in vapor phase etching of - group compound semiconductors,
The present invention aims to provide a vapor phase etching method that allows precise control of etching depth.

〔発明の構成〕[Structure of the invention]

本発明によれば、−族化合物半導体の気相
エツチング方法において、ハロゲンないしハロゲ
ン化水素ガスを結晶表面に吸着させる第一の工程
と、−族化合物半導体の族元素のハロゲン
化物として結晶表面から族元素を揮発させる第
二の工程とにより、全体として−族化合物半
導体の結晶表面から一分子層を取り除き、この第
一の工程と第二の工程を繰り返すことによてエツ
チングを行なうことを特徴とする−族化合物
半導体の気相エツチング方法が得られる。
According to the present invention, in the vapor phase etching method of a - group compound semiconductor, the first step is to adsorb a halogen or hydrogen halide gas onto the crystal surface, and the step of adsorbing a halogen or hydrogen halide gas from the crystal surface as a halide of a group element of the - group compound semiconductor. A second step of volatilizing the elements removes one molecular layer from the crystal surface of the - group compound semiconductor as a whole, and etching is performed by repeating the first and second steps. A method for vapor phase etching of - group compound semiconductors is obtained.

〔作用〕 本発明は2つの工程に分けられる。先ず最初に
基板結晶上にCl2のようなハロゲンガスないし
HClのようなハロゲン化水素ガスを吸着させる第
一の工程である。例えばGaAsとHClガスの場合、
基板結晶温度が比較的高い場合には、HClガスの
供給によりすぐにエツチングが生じるが、以下の
実施例でも述べるように、400℃程度になると、
基板結晶上にHClガスを供給してもエツチングを
生じることはなくHClの吸着のみが起こる。この
ようにHClが吸着した後、HClガスの供給を止
め、次にこの基板結晶温度を何らかの方法で上昇
させ、GaClとして結晶表面からGaを取り去る。
これが第二の工程である。Gaの結合ボンドを切
られたAs原子は自分自身で気相中に飛び出すと
考えられる。この第一の工程と第二の工程によ
り、基板結晶表面の一分子層がエツチングされる
ことになる。
[Operation] The present invention is divided into two steps. First, a halogen gas such as Cl 2 or
This is the first step to adsorb hydrogen halide gas such as HCl. For example, in the case of GaAs and HCl gas,
If the substrate crystal temperature is relatively high, etching will occur immediately due to the supply of HCl gas, but as will be described in the examples below, when the substrate crystal temperature reaches about 400°C,
Even if HCl gas is supplied onto the substrate crystal, no etching occurs and only HCl adsorption occurs. After HCl is adsorbed in this way, the supply of HCl gas is stopped, and then the substrate crystal temperature is increased by some method to remove Ga from the crystal surface as GaCl.
This is the second step. It is thought that the As atoms that have broken the Ga bond will fly out into the gas phase by themselves. Through these first and second steps, one molecular layer of the substrate crystal surface is etched.

従つて、本発明による気相エツチング方法を用
いると、エツチングの深さは第一の工程と第二の
工程の繰り返しの数にのみ依存し、しかも、一分
子層の単位で制御できるようになる。更に、HCl
の吸着は一定基板温度以下なら温度に依存せず基
板全面に均一に起こるため、エツチング深さは原
理的には完全に均一となる。
Therefore, when using the gas phase etching method according to the present invention, the etching depth depends only on the number of repetitions of the first and second steps, and can be controlled on a monolayer basis. . Furthermore, HCl
Adsorption occurs uniformly over the entire surface of the substrate, regardless of temperature, below a certain substrate temperature, so the etching depth is, in principle, completely uniform.

次に、本発明を実施例に基づき具体的に説明す
る。
Next, the present invention will be specifically explained based on examples.

〔実施例〕〔Example〕

実施例 1 本実施例ではGaAs基板結晶を前面に亘つて気
相エツチングする場合に本発明を適用した場合に
ついて述べる。本実施例に用いる気相エツチング
装置の概略を第1図に示した。この装置に於いて
反応管1の上流からH2キヤリヤガスと共にHCl
ガスを供給する。また、反応管に挿入したバイパ
スパイプ2からAsの水素化物であるAsH3をH2
キヤリヤガスと共に供給する。基板結晶3として
は(100)面方位のGaAsを用いた。反応管の温
度は抵抗加熱により制御し上流部は400℃、下流
部は600℃に保つた。ガス流量条件は次の通りで
ある。
Embodiment 1 In this embodiment, a case will be described in which the present invention is applied to vapor phase etching the entire front surface of a GaAs substrate crystal. FIG. 1 schematically shows the vapor phase etching apparatus used in this example. In this apparatus, HCl is supplied with H2 carrier gas from upstream of reaction tube 1.
Supply gas. In addition, AsH 3, which is a hydride of As, is transferred to H 2 from the bypass pipe 2 inserted into the reaction tube.
Supplied with carrier gas. As the substrate crystal 3, GaAs with (100) plane orientation was used. The temperature of the reaction tube was controlled by resistance heating and maintained at 400°C in the upstream part and 600°C in the downstream part. The gas flow conditions are as follows.

HCl 5c.c./min AsH3 5c.c./min H2 2000c.c./min エツチングの手順としては、先ず、基板結晶3
を反応管上流の低温領域4に置き、所定温度
(400℃)まで昇温した。その温度に達したところ
でHClを供給し、そこで10秒間HClを十分に吸着
させ(第一の工程)、基板結晶3を下流の高温領
域5(600℃)に移動し(第二の工程)、10秒後再
び基板結晶3を反応管上流の低温領域4に移動し
た。これを一サイクルとして、ここでは、300サ
イクル行なつた。この後、基板結晶3を取り出
し、エツチング深さの評価を行なつたところ、
GaAsは約850Åの厚さエツチングされているこ
とがわかつた。これは、一サイクルに一分子層が
エツチングされていることを示している。
HCl 5c.c./min AsH 3 5c.c./min H 2 2000c.c./min As for the etching procedure, first, the substrate crystal 3
was placed in the low temperature region 4 upstream of the reaction tube, and the temperature was raised to a predetermined temperature (400°C). When that temperature is reached, HCl is supplied, HCl is sufficiently adsorbed there for 10 seconds (first step), and the substrate crystal 3 is moved downstream to the high temperature region 5 (600 ° C.) (second step). After 10 seconds, the substrate crystal 3 was moved again to the low temperature region 4 upstream of the reaction tube. This is regarded as one cycle, and 300 cycles were performed here. After that, the substrate crystal 3 was taken out and the etching depth was evaluated.
It was found that the GaAs was etched to a thickness of approximately 850 Å. This indicates that one molecular layer is etched in one cycle.

次に反応管上流部に温度を200〜400℃、反応管
下流部の温度を600〜750℃の間で変化させたり、
HCl流量を変化させてエツチング深さの変化を調
べたが、一サイクルにほぼ一分子層がエツチング
されている結果は変わらなかつた。これらの結果
は、エツチングの深さは第一の工程と第二の工程
の繰り返しの数にのみ依存し、しかも、一分子層
の単位(約3Å)で精密に制御できる本発明効果
を良く現わしている。また、それぞれにおけるエ
ツチングの均一性は、±1%以下の測定誤差以内
の優秀なものであつた。更に、エツチング面は、
表面欠陥や、特別なモフオロジーがなく鏡面性に
優れたものが得られた。
Next, the temperature at the upstream part of the reaction tube was varied between 200 and 400°C, and the temperature at the downstream part of the reaction tube was varied between 600 and 750°C.
We investigated changes in etching depth by varying the HCl flow rate, but the result remained unchanged: approximately one molecular layer was etched in one cycle. These results clearly demonstrate the effect of the present invention, in which the etching depth depends only on the number of repetitions of the first and second steps and can be precisely controlled in units of a single molecular layer (approximately 3 Å). I'm watching. Further, the uniformity of etching in each case was excellent with a measurement error of ±1% or less. Furthermore, the etched surface is
A product with excellent specularity and no surface defects or special morphology was obtained.

なお、この実施例はエツチングのみを行なうも
のであるが、これを基本として従来の成長手法を
組み合わせることによつて、容易にエツチング−
成長の連続プロセスを実現出来ることは明らかで
あろう。
Although this example only performs etching, it is possible to easily perform etching by combining this with conventional growth methods.
It should be clear that a continuous process of growth can be achieved.

実施例 2 本実施例ではSiO2マスクの窓を通してGaAs基
板結晶の一部に気相エツチングし、その場所に再
成長する場合に本発明を適用した場合について述
べる。本実施例に用いる成長装置の概略を第2図
に示した。この成長装置では、上段反応室6には
その上流からH2キヤリヤガスと共にHClガスを
供給できる。また、上流から基板結晶3に対して
アルゴンレーザ光7を照射出来る。下段反応室8
の上流にはGaソースボート9が置かれ、その上
流からH2キヤリヤガスと共にHClガスを供給出
来る。また、Gaソースボート9をバイパスする
パイプ2からはAsの水素化物であるAsH3をH2
キヤリヤガスと共に供給できる。基板結晶3とし
ては、第3図に示すように半絶縁性GaAs(100)
上にSiO2マスクを形成し、そこに10μm幅の窓1
1を開けたウエフアーを用いた。反応管の温度は
抵抗加熱により制御し、Gaソース部は800℃、基
板結晶は400℃に保つた。ガス流量条件は次の通
りである。
Embodiment 2 In this embodiment, a case will be described in which the present invention is applied to a case where a part of a GaAs substrate crystal is vapor phase etched through a window of a SiO 2 mask and regrown at that location. FIG. 2 shows an outline of the growth apparatus used in this example. In this growth apparatus, HCl gas can be supplied to the upper reaction chamber 6 from upstream thereof together with H 2 carrier gas. Further, the substrate crystal 3 can be irradiated with the argon laser beam 7 from upstream. Lower reaction chamber 8
A Ga source boat 9 is placed upstream of the Ga source boat 9, from which HCl gas can be supplied along with H2 carrier gas. In addition, from the pipe 2 that bypasses the Ga source boat 9, AsH 3 , which is a hydride of As, is transferred to H 2
Can be supplied with carrier gas. The substrate crystal 3 is semi-insulating GaAs (100) as shown in Figure 3.
A SiO 2 mask is formed on top, and a 10 μm wide window 1 is formed there.
A wafer with No. 1 opened was used. The temperature of the reaction tube was controlled by resistance heating, and the temperature of the Ga source was kept at 800°C and the temperature of the substrate crystal was kept at 400°C. The gas flow conditions are as follows.

上段反応室 HCl 5c.c./min H2 2000c.c./min 下段反応室 HCl 5c.c./min AsH3 5c.c./min H2 2000c.c./min 先ず、エツチングの手順を示す。基板結晶3を
反応管にセツトし、上段反応室6で所定温度
(400℃)まで昇温した。その温度に達したところ
でHClを供給し、10秒間HClを十分に吸着させた
(第一の工程)。次に、HClの供給を止め、基板結
晶3に対してアルゴンレーザビームを照射した
(第二の工程)。これを一サイクルとして、ここで
は700サイクル行なつた。一方、下段反応室8の
Gaソースに対しHClを供給し、バイパスパイプ
2からはAsH3ガスと1×1018cm-3程度ドーピン
グするためのドーパントガスH2Sを供給した。上
段反応室6でプロセスが終了したところで基板結
晶3を下段反応室8に移動し、GaAsを約2000Å
の厚さに成長させた。成長結晶を調べた結果、窓
11のGaAs部分に最初エツチングが行なわれ、
その場所に高濃度ドーピング層が再成長している
ことが判明した。ところで、エツチング深さの評
価を行つたところ、GaAsは約2000Åの厚さエツ
チングされていることがわかつた。これは、一サ
イクルにほぼ一分子層がエツチングされているこ
とを示している。エツチング領域におけるエツチ
ング深さの均一性は、±1%以下の測定誤差以内
であつた。また、エツチングを施した所に再成長
したエピタキシヤル層はヒルロツク等の表面欠陥
の非常に少なく、鏡面性に優れたものであつた。
Upper reaction chamber HCl 5c.c./min H 2 2000c.c./min Lower reaction chamber HCl 5c.c./min AsH 3 5c.c./min H 2 2000c.c./min First, perform the etching procedure. show. The substrate crystal 3 was set in a reaction tube, and the temperature was raised to a predetermined temperature (400° C.) in the upper reaction chamber 6. When that temperature was reached, HCl was supplied, and HCl was sufficiently adsorbed for 10 seconds (first step). Next, the supply of HCl was stopped, and the substrate crystal 3 was irradiated with an argon laser beam (second step). This is considered one cycle, and here 700 cycles were performed. On the other hand, the lower reaction chamber 8
HCl was supplied to the Ga source, and AsH 3 gas and dopant gas H 2 S for doping about 1×10 18 cm −3 were supplied from the bypass pipe 2. When the process is completed in the upper reaction chamber 6, the substrate crystal 3 is moved to the lower reaction chamber 8, and GaAs is deposited to a thickness of approximately 2000 Å.
grown to a thickness of As a result of examining the grown crystal, it was found that the GaAs portion of window 11 was first etched;
It was found that a highly doped layer had regrown at that location. By the way, when we evaluated the etching depth, we found that GaAs was etched to a thickness of about 2000 Å. This indicates that approximately one molecular layer is etched in one cycle. The uniformity of the etching depth in the etched area was within a measurement error of less than ±1%. Furthermore, the epitaxial layer regrown on the etched area had very few surface defects such as hillocks and had excellent mirror finish.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明による−族化合
物半導体の気相エツチング方法を用いると、エツ
チング深さの一分子量単位での精密な制御および
極めて高い均一性の確保が可能となる。従つて、
本発明の気相エツチング方法は、種々のデバイス
作製に応用可能である。
As described above, by using the vapor phase etching method of - group compound semiconductors according to the present invention, it is possible to precisely control the etching depth in units of one molecular weight and to ensure extremely high uniformity. Therefore,
The vapor phase etching method of the present invention is applicable to manufacturing various devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による実施例1説明するための
図で、GaAs基板結晶を前面に亘つて気相エツチ
ングする場合に本発明を適用した場合の気相エツ
チング装置の概略図である。第2図は本発明によ
る実施例2を説明するための図で、SiO2マスク
の窓を通してGaAs基板結晶の一部を気相エツチ
ングし、その場所に再成長させる成長装置の概略
図である。第3図は実施例2で用いた基板結晶上
のSiO2パターンを示す図である。第4図は従来
の気相エツチング方法を説明するための図であ
る。 1……反応管、2……バイパスパイプ、3……
基板結晶、4……低温領域、5……高温領域、6
……上段反応室、7……レーザ光、8……下段反
応室、9……Gaソースボート、10……マスク、
11……窓。
FIG. 1 is a diagram for explaining Embodiment 1 of the present invention, and is a schematic diagram of a vapor phase etching apparatus to which the present invention is applied when performing vapor phase etching over the front surface of a GaAs substrate crystal. FIG. 2 is a diagram for explaining Example 2 according to the present invention, and is a schematic diagram of a growth apparatus in which a part of a GaAs substrate crystal is vapor-phase etched through a window of an SiO 2 mask and regrown at that location. FIG. 3 is a diagram showing the SiO 2 pattern on the substrate crystal used in Example 2. FIG. 4 is a diagram for explaining a conventional vapor phase etching method. 1...Reaction tube, 2...Bypass pipe, 3...
Substrate crystal, 4...Low temperature region, 5...High temperature region, 6
...Upper reaction chamber, 7...Laser light, 8...Lower reaction chamber, 9...Ga source boat, 10...Mask,
11...window.

Claims (1)

【特許請求の範囲】[Claims] 1 −族化合物半導体の気相エツチング方法
において、ハロゲンないしハロゲン化水素ガスを
結晶表面に吸着させる第一の工程と、−族化
合物半導体の族元素のハロゲン化物として結晶
表面から族元素を揮発させる第二の工程とによ
り、全体として−族化合物半導体の結晶表面
から一分子層を取り除き、この第一の工程と第二
の工程を繰り返すことによつてエツチングを行な
うことを特徴とする−族化合物半導体の気相
エツチング方法。
1 In a vapor phase etching method for a group-1 compound semiconductor, the first step is to adsorb halogen or hydrogen halide gas onto the crystal surface, and the second step is to volatilize the group element from the crystal surface as a halide of the group element of the group-1 compound semiconductor. A - group compound semiconductor characterized in that by the second step, one molecular layer is removed from the crystal surface of the - group compound semiconductor as a whole, and etching is performed by repeating the first step and the second step. vapor phase etching method.
JP29257485A 1985-12-27 1985-12-27 Method for gaseous-phase etching of iii-v compound semiconductor Granted JPS62153198A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29257485A JPS62153198A (en) 1985-12-27 1985-12-27 Method for gaseous-phase etching of iii-v compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29257485A JPS62153198A (en) 1985-12-27 1985-12-27 Method for gaseous-phase etching of iii-v compound semiconductor

Publications (2)

Publication Number Publication Date
JPS62153198A JPS62153198A (en) 1987-07-08
JPH0355438B2 true JPH0355438B2 (en) 1991-08-23

Family

ID=17783534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29257485A Granted JPS62153198A (en) 1985-12-27 1985-12-27 Method for gaseous-phase etching of iii-v compound semiconductor

Country Status (1)

Country Link
JP (1) JPS62153198A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6475687A (en) * 1987-09-18 1989-03-22 Tanaka Precious Metal Ind Method for removing coating metal from metal oxide base material
JP2680644B2 (en) * 1988-01-14 1997-11-19 三洋電機株式会社 Photo-excited etching method
JPH01289121A (en) * 1988-05-16 1989-11-21 Nec Corp Digital etching process of iii-v compound semiconductor

Also Published As

Publication number Publication date
JPS62153198A (en) 1987-07-08

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