JPH035658B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a short gate field effect transistor which has good microwave characteristics and is easy to manufacture.

The present invention is not limited in any way to materials, and can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as Si or compound semiconductors. The explanation will be given using GaAs among semiconductors as an example.

The general structure of a conventional shot gate field effect transistor is that, as illustrated in the cross-sectional view of FIG. After forming the n-type active layer 12, a source electrode 13, a drain electrode 14, and a shot gate electrode 15 are formed by depositing metal on the surface of this active layer. In a short gate field effect transistor having such a conventional structure, good microwave characteristics cannot be obtained because the resistance between the gate and the source is large. It is also inferior in high-speed switching operation. Therefore,
There was a strong need for technology to reduce gate-source resistance.

In order to solve this problem, as illustrated in FIG. 2, while keeping the thickness of the active layer 12' directly under the gate, which controls the pinch-off voltage, at a desired value,
A structure has been proposed in which the thickness of the active layer 12'' near the source electrode is increased.In this structure, first, an active layer with a uniform thickness corresponding to the thickness directly under the source electrode 13 and the drain electrode 14 is formed, and then, After thinning only the portion 12' that should be directly under the gate electrode 15 by etching, etc., each electrode 13, 1
4 and 15 are formed.

However, in such a structure, not only is it difficult to perform fine photolithography for electrode formation because the surface of the active layer is not flat, but also extremely strict precision is required to control the etching of the active layer, resulting in low yields. There is a drawback that it becomes low.

Furthermore, in order to improve the high frequency characteristics of MESFETs, it is necessary to reduce the gate length as much as possible, which requires extremely fine precision machining in device fabrication. However, in the conventional manufacturing method, when forming the pattern of the gate electrode 15 on the resist, the source electrode 15 is placed very close to the gate pattern.
3 and the drain electrode 14 exist in addition to the step in the operating region 12, the resolution of the photoresist pattern is lower than that on a flat surface, making it difficult to reliably form a gate pattern as short as about 1 μm. It was hot. In particular, in compound semiconductors such as GaAs, it is common practice to perform alloy treatment on the source electrode 13 and drain electrode 14 before forming the gate electrode 15 in order to lower their contact resistance. If alloying is performed at a sufficiently high temperature and for a long time in order to make the gate sufficiently small, agglomeration of the source and drain electrode metals will occur, which tends to cause extremely large steps, which is also a cause of deterioration of the resolution of the gate photoresist pattern. It's getting old.

In addition, the gate electrode 15 is located between ±0.2 μm between the source electrode 13 and the drain electrode 14 that have already been formed.
It is necessary to form with a positional accuracy of m or less. Furthermore, the distance between the source electrode 13 and the gate electrode 15 is
Regarding the electrical characteristics of MESFET, it directly affects the parasitic resistance and parasitic capacitance between the source and gate, so the distance between both electrodes must be as small as possible and controlled with high precision. This distance between the electrodes is also required. However, it is extremely difficult to form such fine patterns with high precision using conventional techniques, and therefore there is a problem in that the manufacturing yield is extremely low.

The present invention has been made in view of the above-mentioned conventional problems, and its object is to provide a short gate field effect transistor with good microwave characteristics and good yield.

The details of the present invention will be explained below with reference to Examples.

FIG. 3 is a cross-sectional view of a shot gate field effect transistor according to an embodiment of the present invention, and 21 is a cross-sectional view of a shot gate field effect transistor according to an embodiment of the present invention.
A semi-insulating semiconductor substrate such as GaAs, 22 an n-type active layer, 23 a source electrode, 24 a drain electrode,
25 is a shot gate electrode. 26 is an insulating film. The field effect transistor of the present invention has a third
As illustrated in the figure, the surface of the active layer is flat and the number of carriers per unit area of the active layer 22'' between the source and drain is larger than the number of carriers of the active layer 22' directly under the gate, and layer 2
2'', 22', gate electrode 25, high impurity concentration layer 22, source electrode 23/drain electrode 2
4 is formed based on the same insulating film pattern 26 using a so-called self-alignment method. Therefore, the positional relationship of each component of the field effect transistor is automatically determined with high precision. Therefore, the present invention has advantages such as simplifying the manufacturing process, improving yield, and enabling fine processing.

FIG. 4 is a cross-sectional view showing an example of a method for manufacturing the field effect transistor shown in FIG. 3.

First, as shown in FIG. 4A, a pattern 27 made of an insulating material is formed on the surface of a GaAs semi-insulating substrate 21.
form. The first ion implantation is performed using this pattern as a mask. This implantation is performed at a high dose to reduce the gate-source resistance, and at a high acceleration voltage and implantation amount to form a conductive layer at a deep position to reduce the gate parasitic capacitance.
Ion implantation is performed at a dose of 1.0×10 ¹³ /cm ² .
As an example, Si ⁺ was implanted at 200 KeV, and the mask pattern 27 was formed using polyimide resin with a thickness of 1.5 μm by ordinary photolithography and sputter etching. Here, the mask pattern 27 is not limited to the polyimide of the embodiment as long as it is a material that serves as a mask for ion implantation or thermal diffusion and can be selectively removed from the insulating film 26.

After the first ion implantation, an insulating film 26' is formed over the entire surface of the substrate as shown in Figure B. In this example, a 3000 Å thick SiO ₂ film formed by vacuum evaporation was used.

The insulating film 26' satisfies the requirements of the present invention if it has resistance to high temperature processes such as annealing. Therefore, the material is not limited to silicon oxide in any way, but any material with excellent heat resistance that does not cause unnecessary reactions with semiconductors even at temperatures of about 800°C may be used, such as silicon nitride, aluminum oxide, zirconium oxide, or silicon oxide. Inorganic compound films such as titanium and aluminum nitride are also possible. Regarding the formation method,
As long as it does not damage the substrate 21 or the mask pattern 27, it is not limited to the vapor deposition method, but also the CVD method, plasma
Any method such as CVD method or sputtering method is possible.

Next, the mask pattern 27 is made of hydrazine,
Alternatively, a new photoresist pattern 28 is formed by removing it with O ₂ gas plasma. Using this as a mask, holes are opened in the insulating film 26' using CF ₄ gas plasma as shown in FIG. C, thereby forming an insulating film pattern 26.
The second photoresist pattern 28 is used as a mask.
After performing the second ion implantation, the high concentration impurity layer 22
form. This ion implantation makes electrode contact between the source electrode/drain electrode and the active layer ohmic with low resistance, and forms a highly concentrated impurity layer near the surface of the substrate 21. One example of ion implantation conditions for this is the implantation energy.
30 KeV and an implantation dose of 1×10 ¹³ dose/cm ² were selected.
Thereafter, the photoresist pattern 28 is removed leaving the insulating film pattern 26, and another photoresist pattern 29 as shown in FIG. D is formed. In this state, a third implantation is performed using the photoresist pattern 29 and the insulating film pattern 26 as masks.
This implantation is carried out in the active layer 22' of the field effect transistor.
The thickness and carrier concentration of this active layer are selected to achieve the desired pinch-off voltage. For example, pinch-off voltage
To achieve 0.1V, the implantation energy was 50KeV,
Injection amount: 1.5×10 ¹² dose/cm ² (however, the activation rate is 100
%. ) is selected.

As is clear from the amount of ion implantation, the total number of carriers in the active layer 22'' near the source electrode 23 is approximately 7 times larger than the total number of carriers in the active layer 22' directly under the gate electrode 25. - The source-to-source resistance is reduced by a factor of at least 7 compared to the case where the active layer 22'' is formed uniformly. On the other hand, the active layer 22'' is deeply implanted at a high accelerating voltage, and the carrier concentration near the surface of the active layer 22'' is sufficiently low, which has the effect of sufficiently reducing the gate parasitic capacitance. Thereafter, the photoresist pattern 29 is removed and annealing is performed to activate the implanted element. The active layers 22' and 22'' formed in contact with each other become continuous active layers due to lateral scattering during ion implantation.

After this, as shown in FIG. 4E, the source electrode 2
3. Form the drain electrode 24.

Finally, as shown in FIG. 4F, a gate electrode 25 is formed using conventional vapor deposition and lithography techniques.

Note that as shown in Figure F, the source electrode 23,
The drain electrode 24 is structured to protrude beyond the high concentration impurity layer 22, and the gate electrode 25 protrudes beyond the active layer 22'. This takes into consideration misregistration of patterns that occurs in normal photolithography.

In the present invention, the insulating film pattern 2 is reversed from the mask pattern 27 of the first ion implantation.
6 is an essential element. Therefore, the insulating film pattern 26 can be formed in different ways depending on the method and material of the insulating film 26. A description will be given below based on examples.

After the first implantation, a photoresist pattern 28 is formed in a portion corresponding to the high concentration impurity layer, as shown in Figure G. Here, the insulating film pattern 26 can be obtained by a so-called lift-off method in which an insulating film 26' is formed on the entire surface of the substrate using a known technique such as a vacuum evaporation method and the photoresist pattern 28 is removed. In this example, the thickness was 3000Å by vacuum evaporation method.
A pattern of SiO ₂ film was obtained. When only the photoresist pattern 28 is dissolved with acetone, a structure as shown in Figure H is obtained, and the mask pattern 27 used for the first implantation can be used as it is as a mask pattern for forming a high concentration impurity layer. . Thereafter, the same product as in the previous example was obtained through the steps shown in Figure D and thereafter.

What should be clearly stated here is that when forming the gate electrode 25, a window of the silicon oxide (SiO ₂ ) film 26 has already been formed in the same position as the active layer 22' in the previous step. The portion where the gate electrode 25 directly contacts the active layer, that is, the shot junction, is formed in exactly the same area as the active layer 22', and has no overlap with the active layer 22''. As will be detailed later, a MESFET with excellent microwave characteristics can be obtained without unnecessary increases in capacitance.

Furthermore, the source electrode 23 and drain electrode 24 are also formed at the same position as the high concentration impurity layer 22 by the same insulating film pattern 26, and both electrodes can be formed by so-called self-alignment, simplifying the manufacturing process. It is something.

Although the example in which the field effect transistor having the structure illustrated in FIG. 3 is manufactured by the ion implantation method has been described above, it can also be manufactured by the thermal diffusion method. That is, first, a dopant with a large diffusion constant is brought into contact with the substrate surface and thermally diffused to form a deep diffusion layer corresponding to the active layer 22'' in FIG. A shallow diffusion layer corresponding to the active layer 22' in FIG. may be formed according to the embodiment described above.Of course, it is also possible to satisfy the above conditions by using the same dopant and selecting the surface impurity concentration, diffusion temperature, and diffusion time.

The shorter the length of the operating layer 22' in FIG.
Although gm of the MESFET becomes larger, which is advantageous in terms of characteristics, shortening this length is due to the limitations of microfabrication technology when shortening the length of the mask 27 in the manufacturing method illustrated in FIG. It is generally easier to shorten this mask than to shorten the length of the gate metal, so
MESFET can be created.

In the above embodiments, GaAs is used as the semiconductor crystal, but any semiconductor such as InP or other - group compound semiconductors or Si may be used as necessary.

As explained in detail above, the shot gate field effect transistor of the present invention has a large number of carriers in the active layer between the gate and the source, and has a structure in which the active layer directly below the gate electrode and the gate electrode are formed at the same position. A short-gate field effect transistor with a large gm, small gate parasitic capacitance, good high-frequency characteristics, high gate reverse breakdown voltage, and good yield can be realized using a simpler process than the conventional one.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a conventional example, FIG. 3 is a cross-sectional view of an embodiment of the present invention, and FIGS. 4A to 4H are cross-sectional views showing an example of the method for manufacturing the field effect transistor shown in FIG. 3. Figure. 21... Semi-insulating semiconductor substrate, 22... Active layer, 22'... First part of the active layer, 22''... Second part of the active layer, 22... Third part of the active layer ( (high concentration impurity layer), 23... source electrode, 2
4...Drain electrode, 25...Gate electrode, 26
...Insulating film pattern, 26'...Insulating film, 27...
...Mask pattern, 28...Photoresist pattern.

Claims (1)

[Scope of Claims] 1. A shot gate field effect transistor comprising a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate, a source electrode, a shot gate electrode and a drain electrode formed on the active layer, An insulating film is formed on the surface of the semiconductor substrate in a region sandwiched between the gate electrode and the source electrode and a region sandwiched between the gate electrode and the drain electrode, with a side portion of the gate electrode overlapping the surface of the semiconductor substrate. is formed, the active layer has first to third parts, the first part has an impurity concentration distribution in the depth direction that provides a predetermined pinch-off voltage, and the gate electrode has a The second portion is formed in a region that is in direct contact with the semiconductor substrate, and the second portion has an impurity concentration near the surface that is lower than the impurity concentration near the surface of the first portion, and the impurity concentration per unit area during doping. the number of impurities per unit area of the first portion is larger than the number of impurities per unit area of the first portion, and is formed in a region extending from the first portion toward the source electrode and a region extending toward the drain electrode in contact with the first portion. The third portion is formed directly under the source electrode and the drain electrode, overlapping the surface layer portion of the second portion, and is impurity-contained at a high enough level to establish ohmic contact with the source electrode and the drain electrode. A short gate field effect transistor characterized by having a concentration of 2 forming a deep doped layer using a first pattern formed in a gate formation region on the surface of a semi-insulating semiconductor substrate as a mask; forming a second pattern of an inorganic compound film on the surface of the substrate; using the first and second patterns as masks, forming a doped layer with a high impurity concentration on the surface of the deeply doped layer; providing a new third pattern surrounding the entire transistor area on the surface of the semiconductor substrate after removing the first pattern; and using the third pattern and the second pattern as a mask, impurity concentration near the surface. is larger than the impurity concentration near the surface of the deep doped layer, and the number of impurities per unit area during doping is smaller than the number of impurities per unit area of the deep doped layer; A method for manufacturing a short-gate field effect transistor, comprising the steps of: forming a source electrode and a drain electrode on the doped layer with a high impurity concentration, respectively, and forming a gate electrode on the shallow doped layer in the gate formation region. . 3. The step of forming the second pattern of the inorganic compound film is characterized by comprising a step of forming the inorganic compound film entirely on the deeply doped layer, and a step of removing the source formation region and the drain formation region by etching. A method for manufacturing a short gate field effect transistor according to claim 2. 4. The step of forming the second pattern of the inorganic compound film includes the steps of forming another pattern having openings in the second pattern forming area using a material using a different solvent from that of the first pattern, and A method for manufacturing a shot-gate field effect transistor according to claim 2, comprising a step of forming an inorganic compound film, and a step of melting the other pattern and lifting off an unnecessary inorganic compound film. .