JPH035713B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time base collector for a VTR that can simultaneously reproduce multi-channel video signals.

For example, when recording and reproducing a high-definition video signal with about twice the number of lines as usual on a VTR, or when using a device with a slow relative speed between the rotating head and magnetic tape, the video signal is It has been proposed to divide each track into multiple channels and to extend the time axis line by line and record them as separate tracks. When performing such multi-track recording and reproduction, it is necessary to provide a time base collector for each track to remove time axis fluctuations and compress the time axis of the reproduced signal. In the past, the time base collector for each track was operated completely independently, which resulted in the problem that the configuration of the time base collector for multi-track recording and playback was complicated and large-scale.

The purpose of this invention is to realize a time base collector in which such problems are solved.
Line address control is performed commonly for all tracks.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In FIG. 1, 1A, 1B,
Video signals reproduced simultaneously from four tracks by a four-channel rotary head and FM demodulated are supplied to input terminals 1C and 1D. At the input terminals 1A and 1B, a luminance signal is recorded which is divided into two tracks and expanded on the time axis.
Y ₁ and Y ₂ (including burst signals and synchronization signals) are respectively reproduced and supplied to input terminals 1C and 1D.
is a red signal R and a blue signal B (these are also added with a burst signal and a synchronization signal)
is supplied. These reproduced signals are supplied to write clock generation circuits 2A, 2B, 2C, and 2D, and a write clock and a write timing signal having, for example, an integer multiple of the color subcarrier frequency are formed from the burst signals contained in each, and the write clock and write timing signal are A/D converters 3A, 3B, 3C, 3D and memories 4A, 4B, 4C, 4D are operated by the write timing signal.

Further, any of the above-mentioned reproduction signals, for example, the red signal, is supplied to the synchronization separation circuit 5, and the reproduction horizontal synchronization signal PBH separated thereby is supplied to the write address generation circuit 6. For example, a 3-bit write line address is generated by the write address generation circuit 6, and this line address is commonly used for the memories 4A to 4D. In addition, the reproduced vertical synchronization signal from the synchronization separation circuit 5
PBV is supplied to latch 7, and this synchronization signal PBV
The line address at that timing is latched in the latch 7.

This latched line address is the first line address of each field and is supplied to the read address generation circuit 8. On the read side, read clock generation circuits 10A, 10B, 10C, 1 are activated based on the reference video signal supplied from terminal 9.
0D generates read clock and read timing signals and supplies them to memories 4A-4D. At the same time, the reference video signal is supplied to the synchronization separation circuit 11, where the horizontal synchronization signal REF.H and vertical synchronization signal REF.V are separated.
REF.H is supplied to the address counter of the read address generation circuit 8 as its clock input. Further, the vertical synchronization signal REF.V is supplied as a load pulse to the read address generation circuit 8,
The first line address of the field stored in latch 7 is loaded. The output of this read address generation circuit 8 is supplied as a line address to the memories 4A to 4D, and its least significant bit is used as a read enable signal for the memories 4A and 4B.

The luminance signals read out alternately from the memories 4A and 4B are time-axis compressed and have the original time axis. The data read from each of the memories 4A to 4D is sent to the dropout compensation circuit 12A,
12B, 12C, and 12D. Dropouts are detected by envelop-detecting the output of the reproduction amplifier (not shown) from the level of the detected output, and the detection result is written to the corresponding line address as a 1-bit flag. Then, among the output data read from the memories 4A to 4D, the data in the horizontal section determined to be a dropout is compensated by being replaced with the average value of the correct data in the preceding and succeeding horizontal sections.
The outputs of these dropout compensation circuits 12A and 12B are supplied to a D/A converter 13A, and a luminance signal Y is obtained at an output terminal 14A. Also,
The respective outputs of dropout compensation circuits 12C and 12D are supplied to D/A converters 13B and 13C, and a red signal R and a blue signal B are obtained at output terminals 14B and 14C, respectively.

An embodiment of the present invention having the above-described configuration will be described in further detail with reference to FIG. FIG. 2A shows a reference video signal supplied from terminal 9, FIG. 2B and FIG. 2C are reproduced from separate tracks,
The reproduced luminance signal is FM demodulated and supplied to the terminals 1A and 1B, and D in the figure shows the red signal R (same as the blue signal B) supplied to the terminal 1C.
The number assigned to each video signal indicates the line number within one field. Figure 2 E based on the horizontal synchronization signal PBH separated from the red signal R
A pulse signal having a horizontal scanning frequency as shown in FIG. Therefore, the line address number changes repeatedly from number 0 to number 7, as shown in FIG. 2G.

For example, the line number of each channel of data written to line address number 0 of memories 4A to 4D is (Y ₁ = 101, Y ₂ = 102, R = 103, B
= 103). The ²⁰ bits of the line address are
The bit ²¹ becomes the least significant bit of the address of the data of R and B, and the bit of 21 becomes the least significant bit of the address of the data of _Y1 and _Y2.The line addresses of memories 4A and 4B are shown in FIG. It changes at twice the period of . Furthermore, in this embodiment, the rising and falling edges of the ²⁰ bits are always offset by 0.5H (H: horizontal section) with respect to data R and B, and by 0.25H with respect to data _Y1 and _Y2 . is specified to be in an offset state.

In addition, the read address generation circuit 8 outputs the second
A line address for memories 4A and 4B shown in Figure H and a line address for memories 4C and 4D shown in Figure I are generated, and ²⁰ bits of this line address are used as a read enable signal as shown in Figure 2J. and memory 4A and 4B
is supplied to In the block diagram of FIG. 1, the line addresses for memories 4A and 4B and memories 4C and 4D are the same for simplicity, but in reality, as shown in FIG. 2H and FIG. There is an offset of 2H between the lines, and ultimately the line numbers read out for the luminance signal and color signal are the same.
2K and 2L show the luminance signal read out by the line address (FIG. 2H) and read enable signal (FIG. 2J). The read clock of the luminance signal has a frequency twice that of the write clock, so that the time axis is compressed. Also, from memories 4C and 4D,
As shown in Figure 2 M, the red signal R and the blue signal B
is read out. Since the dropout compensation circuits 12A to 12D cause a delay of 1H, the reproduced data is finally obtained in the same time relationship as the reference video signal, as shown in FIG. 2N. The lead clock is the reference video signal REF.
VID, and the output terminal 14
The luminance signals and color signals obtained at A, 14B, and 14C are those from which time-axis fluctuations have been removed.

As mentioned above, in order to control the write address in common for the memories 4A to 4D, it is necessary that the phase of the reproduced signal does not deviate between tracks. In the case of self-recording and playback, there is almost no phase variation between tracks, but when playing back tracks recorded on other VTRs, phase shifts may occur due to variations in the mounting positions of multiple heads between machines. becomes larger. If there is a channel with a phase shift of 0.5H or more, that channel will have a 1H shift in output, resulting in color shift. Therefore, even during compatible playback, it is necessary that the phase difference between the playback signals from each track is 0.5H or less.

Also, when generating a line address based on the pulse formed from the reproduced horizontal synchronizing signal shown in Figure 2E, if the least significant bit (2 ⁰ ) has the opposite polarity to that shown in Figure 2F. Then, the line number of each channel of data written to line address number 0 of memories 4A to 4D is
(Y ₁ = 101, Y ₂ = 102, R = 102, B = 102), and the line number between the luminance signal and color signal is
It will be shifted by 1H, so as above,
Looking at the data obtained by controlling the read line address with an offset of 2H, the line number of the chrominance signal leads by 1H relative to the luminance signal. Even in this case, if the read line address is set to an offset of 1H, the line numbers of the luminance signal and color signal can be made the same. Therefore, in the line address generation circuit 6, for example, the lowest bit 20 of the line address is always set to " ⁰ " at the timing of the horizontal synchronization signal of the luminance signals _Y1 , _Y2 .
It is stipulated that This can prevent the line numbers of the luminance signal and color signal from being shifted in output.

As understood from the description of one embodiment above,
According to this invention, when time-base fluctuations in video signals reproduced from a plurality of tracks are removed using a memory, the line address of this memory can be controlled in common for each track, unlike the conventional method. The circuit configuration can be simplified compared to the case where an address control circuit is provided for each reproduced signal of each track.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart used to explain the operation of the embodiment of the invention. 1A~1D...Input terminal for playback signal, 4A~4
D...Memory, 6...Write address generation circuit, 8...Read address generation circuit.

Claims (1)

[Claims] 1 A plurality of reproduced video signals obtained by simultaneously reproducing a plurality of tracks by a plurality of heads and whose mutual phases of synchronization signals are in a synchronous relationship are obtained by using a plurality of memories corresponding to the plurality of reproduced video signals. In the time base collector that corrects the time axis,
The playback video signal is connected to the playback video signal by a common line address formed based on a write clock formed from the playback video signal of each track and a synchronization signal separated from any of the plurality of playback video signals. Along with writing to memory,
A time base collector adapted to read the reproduced video signal from the memory by a read clock and a read line address formed from a reference signal.