JPH0357435B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device used in, for example, an electronic watch, which optically displays a pointer using a liquid crystal or the like.

Conventionally, there are analog electronic watches that have a display section that corresponds to the hands using a liquid crystal display, but because the time scales of these watches are formed by printing, the hands may not be visible to the eye due to the thickness of the glass. The problem was that the position of the scale and the scale on which it should originally be displayed appeared to be out of alignment. Further, it is also time-consuming to adjust the printing position of the scale corresponding to the display position of the pointer.

Therefore, in the present invention, a pointer-shaped display element is arranged radially, a scale display part is formed on the tip side of the display element, and the output that should light up the display element is selected for each unit of information. To provide a display device with high contrast, which eliminates the above-mentioned drawbacks and does not reduce the operating margin of a display element, by controlling the lighting of a scale display part while controlling the lighting of a scale display part in synchronization with the selection of any one of unit information. It is something.

An embodiment of the present invention will be described below based on the drawings.

In FIG. 1, 1 is a crystal oscillator and 2 is a frequency divider. 3 and 4 are a decimal counter and a hexadecimal counter that measure seconds, respectively. 5 and 6 are a decimal counter and a hexadecimal counter that measure the minute digit, respectively, and 7 and 8 are a decimal counter and a hexadecimal counter that measure the hour digit, respectively, and each counter has a binary coded decimal code. shall produce an output of 9 is a hexadecimal counter, 10 is a timing pulse generation circuit, and from the frequency divider 2, for example, 128
Timing pulses are sequentially generated at terminals P ₁ to _{P 3} in response to the Hz output pulse. 11 to 16 are gate circuits having an AND function, which are controlled by pulses sequentially generated at terminals P ₁ to _{P 3} . In the above, the gate circuits 11 to 16 constitute a selection circuit. 17 and 18 are gate circuits having an OR function, and 19 and 20 are gate circuits 17 and 1, respectively.
This is a decoder that converts the output code of 8. 21
is an output order switching circuit, and the output order of the decoder 19 is switched according to one output state of the gate circuit 18. 22 is a segment voltage setting circuit that selects the voltage to be applied to the segment electrodes, which will be described in detail later, and 23 is a common voltage setting circuit that selects the voltage to be applied to the common electrode. 24 is a flip-flop circuit, 25 is a voltage setting circuit, and the terminal
_{Potentials 0v 0 , 2v 0 and}
Generates a predetermined voltage of 3v ₀ periodically. 26 is an inverter.

FIGS. 2 and 3 show electrode patterns of a liquid crystal display device that displays hands.

In FIG. 2, reference numeral 27 indicates the arrangement of segment electrodes with 60 electrodes, and segment electrodes 27a...27a with 10 electrodes are connected to terminals e ₁ to _{e 10} of the segment voltage setting circuit 22 as shown in the figure. It's connected. Other segment electrodes have the following connection relationships. Note that the order of the segment electrodes referred to below is counted clockwise, with the segment electrode 27a connected to the terminal e ₁ being the first segment electrode. The tenth segment electrode 27a is the tenth segment electrode 27a.
The 11th segment electrode 27a and the 9th segment electrode 27a
The 1st becomes the 20th, the 20th becomes the 21st, the 19th becomes the 22nd, and the 11th becomes the 22nd...
It is connected in common with the 30th. Thereafter, segment electrodes up to the 60th are connected in the same relationship as above.

FIG. 3 shows a pattern 28 of the common electrode, and the common electrode 28 is divided into six parts on the outside, middle and inside.
d, 28b, and 28a. Note that index portions M ₁ to _{M 12} corresponding to each time scale from 1 o'clock to 12 o'clock are formed on the common electrode 28d.

Note that each dividing groove 28 of the common electrodes 28a, 28b
c...28c is between the 10th and 11th segment electrodes, between the 20th and 21st segment electrodes, between the 30th and 31st segment electrodes, and between the 40th and 41st segment electrodes in the clockwise direction. between the th segment electrodes,
Between the 50th and 51st segment electrodes and between the 50th and 51st segment electrodes.
It is configured so that it can be located between the 60th and 1st segment electrodes.

Note that a liquid crystal display device is composed of an assembly of display elements with a liquid crystal interposed between segment electrodes and a common electrode, but the configuration can be easily implemented by a person skilled in the art, and Since the present invention is not characterized by such a configuration itself, it will be omitted.

FIG. 4 is a detailed circuit diagram of the output priority switching circuit 21 and the segment potential setting circuit 22.
43 are gate circuits, 44 to 53 are semiconductor switching circuits, and 54 to 58 are inverters.

FIG. 5 is a detailed circuit diagram of the voltage setting circuit 25, in which 59 to 74 are switching circuits similar to those described above, and 75 and 76 are inverters.

FIG. 6 is a detailed circuit diagram of the common voltage setting circuit 23, in which 77-82 are AND gate circuits, 83-9
6 is a switching circuit similar to the above, 97 to 10
3 is an inverter. In the above, switching circuits 95, 96 and inverter 103 constitute a scale display circuit.

The voltage states set in this embodiment will be explained below. In FIG. 5, V ₀ is applied to terminals l ₃ and l ₄ ,
A voltage of 2V ₀ is applied to the terminals l ₂ and l ₅ , a voltage of 3V ₀ is applied to the terminals l ₀ and l ₇ , and a voltage of 0 is maintained at the terminals l ₁ and l ₆ .

The liquid crystal display device in this embodiment is lit by the cumulative application of a periodic pulse train including a maximum voltage value of | _{3V 0 |} It is assumed that the lamp will not light up.

The terminal P ₀ shown in the fifth diagram is connected to the frequency divider 2 shown in the first diagram.
A pulse train A shown in FIG. 7 is applied from terminal P ₀ of , and switching circuits 59, 61, 63 and 65 and switching circuits 60, 62, 64 and 66 are alternately turned on. The pulse train B shown in FIG. 7 which is triggered by the pulse produced at terminal P ₁ shown in FIG.
7, 69, 71 and 73 and switching circuit 6
8, 70, 72 and 74 are alternately turned on.

According to each of the above switching operations, two predetermined voltages among voltages 0, V _{0 ,} 2V ₀ and 3V ₀ are generated at the output terminals S ₀ and S ₁ and the output terminals C 0 to _{C 2} . _{Therefore ,} in the _pulse waveform _{b 1 of} the pulse train B shown in FIG.
Voltages V ₀ and 0 are generated alternately at terminal C ₁ and voltages V ₀ and 3V ₀ are generated at terminal C ₂ . In addition, in waveform b ₂ , voltage 3V ₀ is applied to terminal S ₀ and voltage V ₀ and voltage are applied to terminal S ₁ .
3V ₀ , voltage 0 on terminal C ₀ and 3V ₀ , voltage on terminal C ₁
2V ₀ and 3V ₀ , voltages 2V ₀ and 0 are generated alternately at terminal C ₂ .

FIG. 8 is a chart showing the terminal voltage CV generated at each of the terminals C ₀ to _{C 2} , the terminal voltage SV generated at each terminal S ₀ and S ₁ , and the voltage between both terminals.

Note that each of the two voltage values at terminals C ₀ to _{C 2} and each of the two voltage values at terminals S ₀ and S ₁ are generated at the same timing on the left and right sides of the drawing, and the two voltage values that are different are generated at each timing. It shows the difference in voltage values.
8A shows the voltage state when the terminal Q of the flip-flop circuit 24 shown in the first figure is "1", and FIG. 8B shows the voltage state when the terminal Q is "0".

Next, as an example, the counters 3 to 8 shown in the first diagram are
The operation of the pointer display when the time is 10:05:00 will be explained.

In this timekeeping state, the counter 3 is "0",
The counter 4 counts "0", the counter 5 counts "5", the counter 6 counts "0", the counter 7 counts "0", the counter 8 counts "5", and the counter 9 counts "5".

When a pulse is periodically generated from the terminal _P1 of the timing pulse generation circuit 10 shown in FIG. Data is input to gate circuit 18. Therefore, "0" is generated at the terminals ²⁰ to ²³ of the gate circuit 17, and "0" is generated at the terminals ²⁰ to ²² of the gate circuit 18. Therefore, "1" is produced at the terminal, "0" is produced at the terminal h, and " ₁ " is produced at the terminal X0 of the decoder 19.
Therefore, referring to FIG. 4, the gate circuit 29,
Since the output of 39 becomes "1", the voltage generated at terminal _S0 is generated at terminal _e1 . For other terminals e ₂ to e ₁₀ , switching circuits...47, 49...5
1,53 is turned on, a voltage is generated at terminal _S1 .

Next, regarding the decoder 20 shown in FIG. 6, since "1" is generated at the terminal _Y0 , the voltage generated at the terminal _C0 is generated at the terminal _K1 . In addition, in this state, the terminals of the timing pulse generation circuit 10
Since P ₃ is "0", its inverted logical value at terminal ₃ is "1", so gate circuits 77 to 8
2 is open. Therefore, the switching circuit 83 is turned on, and the voltage occurring at the terminal _C0 is generated at the terminal _g1 . Other terminals K ₂ ~ K ₆ , g ₂ ~
The voltage occurring at terminal _C1 is generated at _g6 .

Therefore, from the diagrams in Figure 8 A and B, terminal e ₁
The voltage of the difference between the voltages applied to g ₁ and k ₁ | 3V ₀
| is periodically applied to the liquid crystal, and the display element corresponding to the electrode S shown in the second diagram corresponding to the electrode is lit. Since the voltage |V ₀ | is periodically applied between the other electrodes, the display elements corresponding thereto do not light up.

On the other hand, the above timing pulse generated at terminal _P1 is
The switching circuit 95 shown in FIG. 6 is turned on, and the pulse train applied to the terminal _C2 is generated at the output terminals _m1 to _m6 . From the diagrams in Figure 8 A and B, terminal C ₂
The voltage pulse of the difference between the voltage applied to the terminal S 0 and the voltage at the terminals S ₀ and S ₁ includes a voltage |3V ₀ |.

Therefore, the display portion corresponding to the hatching G at the tip of the segment electrode 27a shown in the second figure, which faces the common electrode 28d shown in the third figure, lights up.

Next, terminal P ₂ of the timing pulse generation circuit 10
Noting that, the pulses generated periodically then open gate circuits 12 and 15 and counter 5.
The output data "5" and "0" of 6 and 6 pass through the same gate circuit.

Therefore, “1” is applied to the terminal X5 of the decoder 19,
A "1" is generated at the terminal _Y0 of the decoder 20, or "1", and h holds "0".

Therefore, the output of the gate circuit 41 shown in FIG. 4 becomes "1", the switching circuit 48 is turned on, and the voltage present at the terminal _S0 is produced at the terminal _e6 . The voltage occurring at the terminal _S1 is generated at the other terminals e1 _{to e5 and e7} to _e10 .

Moreover, from FIG. 6, the voltage generated at the terminal C0 is generated at the terminals _g1 , _k1 , and the voltage generated at the terminal _C0 is generated at the terminals g1, k1, and the voltage at the other terminals _g2 to _g6 and _K2
The voltage that appears at terminal C ₁ occurs at ~K ₆ . Therefore, the display elements constituted by the segment electrode M connected to the terminal e ₆ and the common electrode for the terminals g ₁ and k ₁ are illuminated.

Focusing on the terminal _P3 of the timing pulse generation circuit 10, the pulses periodically generated from it are as follows:
Gate circuits 13 and 16 are opened to allow the outputs of counters 7 and 8 to pass through them. This results in
Connect terminal S ₀ to terminal e ₁₀ of segment voltage setting circuit 22
A voltage is generated. Common voltage setting circuit 23
The voltage that occurs at the terminal C ₀ is generated at the terminal K _{6 of} , and the voltage that occurs at the terminal C ₁ is generated at the other terminals K ₁ to _{K 5} . Furthermore, when a pulse occurs at terminal _P3 ,
The outputs of the gate circuits 77 to 82 shown in FIG. 6 are “0”
Therefore, all terminals g ₁ to g ₆ are terminal C ₁
A voltage is generated.

Therefore, the display element is illuminated when it is constituted by the segment electrode H connected to the terminal e ₁₀ and the common electrode connected to the terminal K ₆ . As a result of the above, the display elements corresponding to the segment electrodes H, M, and S shown in the second diagram are lit, and 10:05:00 is displayed.

Next, an example of an integration display in which the previous display state is sequentially maintained will be explained. In this example, only the case where minute and second digits are displayed will be explained.

In FIG. 9, 104 is an integration type decoder, which has an operating function in which the terminal corresponding to the decimal code conversion value of the input value and the terminals before that are held at "1". Similarly, the decoder 105 is an integration type decoder, and has an operating function in which the terminal corresponding to the hexadecimal code conversion value of the input value and the terminals before that are held at "1". As an example of the above circuit configuration, an OR gate circuit is provided corresponding to each output terminal of a decoder that generates an output only to the terminal corresponding to the code conversion value, and the output of the OR gate circuit corresponding to the higher output terminal is sent to the output terminal. There is a rotating configuration where the input is one input of the OR gate circuit immediately before. 106
is a common voltage supply circuit, the details of which are shown in FIGS. 10 and 11. In Figure 10, 10
7 to 117 are switching circuits similar to those already described, 118 to 127 are AND gate circuits, and 12
8,131 is an inverter. In FIG. 11, 132-142 are switching circuits similar to those already described, 143-152 are AND gate circuits, and 153-156 are inverters. Referring again to FIG. 9, numeral 157 is a timing pulse generating circuit that alternately generates pulses to terminals P ₁ and P ₂ . Note that the same numerical values as those shown in the first diagram indicate the same functional elements.

As an example, the cumulative lighting display when the counter shown in FIG. 9 measures 2 minutes and 3 seconds will be described.
In this state, counters 3, 4, 5 and 6 have values of "5", "3", "2" and "0", respectively. Therefore, when a pulse is generated at terminal _P1 of the timing pulse generation circuit 157,
The terminals X ₀ to X ₅ of the integration type decoder 104 are "1", the terminals X ₆ to X ₉ are "0", and the terminals Y ₀ to _{Y 3} of the integration type decoder 105 are "1", the terminals
Y ₄ and Y ₅ become “0”. Looking at the terminal voltage on the segment electrode side, as shown in Figure 4, the terminal voltage
In e ₁ to _{e 4} , the voltage applied to terminal S ₁ is
The voltage applied to terminal S ₀ occurs between e ₅ and _{e 10} .
On the other hand, looking at the common electrode side, from Figure 10,
The voltage applied to terminal C ₂ is applied to terminals g ₁ to _{g 3} , the voltage applied to terminal C 0 is applied to terminal g ₄ , the voltage applied to _{terminal C 1 is} applied to terminals g ₅ and g ₆ . arise.
Furthermore, in FIG. 11, since the terminal _P2 of the timing pulse generation circuit 157 shown in FIG. 9 is in the "0" state, the voltage applied to the terminal _C1 is generated at the terminals _k1 to _k6 . Therefore, from the diagrams in FIGS. 8A and 8B, the common electrode connected to g ₁ to _{g 3} shown in the third diagram and the segment electrode electrically conductively connected to the terminals e ₁ to e ₁₀ shown in the second diagram A common electrode connected to terminal _g4 and a segment electrode electrically conductively connected to terminals _e5 to _e10 are opposed to each other. The display element lights up and displays.

Next, the timing pulse generation circuit 15 shown in FIG.
When a pulse is generated at the terminal _P2 of the integration type decoder 104, the terminals _X0 to _X2 of the integration type decoder 104 are "1", the terminals _X3 to _X9 are "0", and the integration type decoder 104 is set to "0".
Terminal _Y0 of 05 becomes "1", and _Y1 to _Y5 become "0".

From the circuit shown in the fourth diagram, the voltage applied to the terminal _S0 is generated at the terminals _e1 to _e3 , and the voltage applied to the terminal _S1 is generated to the terminals _e4 to _e10 . Also, from Figure 10,
The voltage applied to the terminal _C1 is generated at the terminals _g1 to _g6 . Furthermore, from FIG. 11, the voltage applied to the terminal _C0 is generated at the terminal _k1 , and the voltage applied to the terminal _C1 is generated at the terminals _k2 to _k6 . Accordingly, from the diagrams in the eighth diagram A and B, it is made up of a common electrode to which the terminal _k1 shown in the third diagram is connected and segment electrodes conductively connected to the terminals _e1 to _e3 . The display element is lit.

The above lighting state is shown in the hatched part shown in Figure 3, where the score display corresponding to hatching a shows the seconds, the display corresponding to hatching b shows the minutes, and the display of 2 minutes and 35 seconds is shown. Recognized.

It should be noted that the scale display is illuminated by the voltage applied when a pulse is generated at the terminal _P1 , in exactly the same manner as in the previously described embodiments.

In the above embodiments, the voltages to be applied to the segment electrodes and the common electrode were explained only in the case shown in FIGS. It's okay. Here, Sv represents the voltage waveform applied to terminals S ₀ and S ₁ , Cv represents the voltage waveform applied to terminals C ₀ , C ₁ and C ₂ , and w ₁ to _{w 6} represent the voltage waveforms applied to terminals S ₀ .S ₁ The voltage waveform of the voltage difference between the terminals C ₀ and C ₂ is shown. When the voltage waveforms w ₁ , w ₅ and w ₀ are applied between the segment electrodes and the common electrode, the display element constituted thereby is illuminated. Since these effective values are equal to 3/√2≈2.12, lighting is performed with a constant contrast no matter which lighting voltage waveform is selected.

In the above embodiment, a voltage is applied between the scale display electrodes in synchronization with the pulse generated at the terminal _P1 , but this is not necessarily the case _. The lighting voltage may be applied in synchronization with the pulse.

As detailed above, the information to be displayed is selected and output for each unit of information, and the pulse voltage to be lit on the scale display section is applied in synchronization with the selection of any unit of information. Even if the number of unit information to be displayed changes, the scale display section and the unit information can always be displayed with the same contrast, and no difference in contrast occurs between the two. In other words, in general, if the pulse voltage waveform for lighting is constant, the display state (contrast with the display element in the non-display state) of the liquid crystal changes depending on the drive cycle.
As the number of units of information to be displayed changes as described above, the time division drive cycle of each unit information changes accordingly, but the time division drive cycle of the scale display section changes as well. Therefore, no difference in contrast occurs between the two. Furthermore, by displaying the tip of the display element and the scale display section in the same cell, there is no need to adjust the positions of both.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention;
Fig. 2 is a plan view of the arrangement pattern of segment electrodes constituting the display section, Fig. 3 is a plan view of the arrangement pattern of the common electrodes of the display section, and Fig. 4 is the output priority switching circuit shown in Fig. 1. Detailed circuit diagram of Figure 5 is the detailed circuit diagram of Figure 1.
FIG. 6 is a detailed diagram of the common voltage setting circuit shown in FIG. 1. FIGS. Figure 8 is a chart showing the terminal voltage Sv of the segment electrode, the terminal voltage Cv of the common electrode, and the voltage value within one cycle of the voltage between both electrodes.
FIG. 9 is an electric circuit diagram of another embodiment, FIGS. 10 and 11 are detailed diagrams of the common voltage supply circuit shown in FIG. 9, and FIG. 12 is a terminal voltage waveform of the segment electrode.
3 is a chart showing the terminal voltage waveform Cv of Sv and the common electrode, and the voltage waveform between short electrons. 3-9...Counter, 19...Decoder, 21
...Output order switching circuit, 22...Segment voltage setting circuit, 23...Common voltage setting circuit.

Claims (1)

[Claims] 1 A plurality of segment electrodes arranged radially and circularly are provided, and fan-shaped common electrodes are arranged circularly and in three concentric circles facing each segment electrode group of the same number of segment electrodes. death,
Corresponding segment electrodes of each segment electrode group are electrically connected to each other, a liquid crystal is interposed between the segment electrodes and a common electrode, a plurality of pointer-shaped display elements and a scale display section are provided, and a timing pulse is generated. A timing pulse generation circuit is provided, a counter that outputs time data is provided, a voltage setting circuit is provided that generates a plurality of pulse voltages having potentials of 0, V ₀ , 2V ₀ , and 3V ₀ , and the above-mentioned timing pulse generation circuit A selection circuit is provided that selects the output of the counter for each unit data in synchronization with the output of the segment, and one output of the selection circuit applies the display output pulse from the voltage setting circuit to the segment electrode to be displayed. A common voltage setting circuit is provided to apply a display output pulse from the voltage setting circuit to the common electrode to be displayed by the other output of the selection circuit, and the voltage is specified by the timing pulse of the timing pulse generation circuit. A display device comprising a scale display circuit that applies a display pulse to the scale display section to display a scale only when unit data is selected.