JPH0357612B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention involves sandwiching and stacking a plurality of mechanically chamfered silicon semiconductor wafers with corrosion-resistant spacers interposed therebetween, and immersing them in an etching solution. The present invention relates to a method of manufacturing a silicon semiconductor wafer in which a chamfer etching process is performed in which only the chamfered part is etched.

(Conventional technology) The conventional method for manufacturing silicon semiconductor wafers is as follows:
As shown in FIG. 1, a slicing process A in which a silicon single crystal semiconductor ingot is sliced into thin plates using a diamond cutter or the like to obtain a silicon semiconductor wafer, and a peripheral portion of the silicon semiconductor wafer obtained by slicing is a mechanical chamfering step B in which the corners are mechanically removed, a wrapping step C in which both sides of the mechanically chamfered silicon semiconductor wafer are polished, and the wrapped silicon semiconductor wafer is immersed in an etching solution. This process consists of a full-surface etching process D in which the entire surface is etched, and a polishing process E in which one or both sides of the silicon semiconductor wafer subjected to the full-surface etching process are polished to a mirror finish.

The surface of the chamfered portion of the silicon semiconductor wafer manufactured by this conventional manufacturing method has surface roughness formed by cutting with a diamond cutter or the like. If the surface of the chamfered portion is rough, there are disadvantages in that dirt and thermal distortion occur. A common method for eliminating the surface roughness of the chamfered portion is to immerse the entire surface of the silicon semiconductor wafer in an etching solution and dissolve and remove the surface roughness with the etching solution. However, when etching the entire surface, even if the chamfer is etched, the entire surface of the silicon semiconductor wafer is etched, so if etching is continued until the surface roughness of the chamfer is eliminated, crystal loss will increase; When trying to reduce crystal loss, there was a problem in that the surface roughness of the chamfered portion could not be completely removed.

In order to solve this problem, a surface treatment method for silicon semiconductor wafers has been disclosed in which only the chamfered portion of the silicon semiconductor wafer is immersed in an etching solution before etching the entire surface (Japanese Patent Laid-Open No. 134935/1983). Public bulletin).

However, according to this method, when etching the chamfered portion, a plurality of silicon semiconductor wafers are stacked and sandwiched with their main surfaces in close contact with each other. Otherwise, the etching solution may enter between the silicon semiconductor wafers, etching the main plane of the wafer irregularly from the outer periphery without limiting the etching to the chamfer, and the main plane of the wafer may be partially reduced. ,
Or reduce the surface accuracy. These scratches are relatively deep, locally deteriorating the crystal quality of the surface layer of the wafer, and are not removed during the mirror polishing process on one side of the wafer after chamfering. This may cause defects or performance deterioration. In some cases, the presence of relatively large particles may cause wafer cracks. In addition, when the main plane is etched irregularly, even if mirror polishing is performed in a later process, the etched area will not become mirror-finished and the performance of the integrated circuit device formed in this area may deteriorate or become defective. result.

(Problems to be Solved by the Invention) The present invention solves the problem that when etching the chamfered portion of silicon semiconductor wafers, the main surfaces of the silicon semiconductor wafers that are held closely together are scratched, or the main planes are irregular from the outer periphery. It is an object of the present invention to provide a method of manufacturing a silicon semiconductor wafer that can improve the smoothness of the entire surface of the chamfered portion without being etched.

(Means for solving the problem) In order to achieve the above object, in the present invention,
A slicing process in which a silicon single crystal semiconductor ingot is sliced into thin plates using a diamond cutter or the like to obtain a silicon semiconductor wafer, and a machine that mechanically removes the peripheral corners of the silicon semiconductor wafer obtained by slicing. a wrapping step of polishing both sides of the mechanically chamfered silicon semiconductor wafer; a full surface etching step of immersing the wrapped silicon semiconductor wafer in an etching solution to etch the entire surface; A method for manufacturing a silicon semiconductor wafer comprising a polishing step of mirror-polishing one or both sides of the processed silicon semiconductor wafer, wherein the plurality of mechanically chamfered silicon semiconductor wafers are covered with a corrosion-resistant spacer. A chamfer etching process is performed in which the spacers are sandwiched and laminated and immersed in an etching solution to etch only the chamfered parts, and the spacer has approximately the same dimensions as the silicon semiconductor wafer, and its peripheral edge is uniform over the entire surface. In its cross-sectional shape, it has a linear, concave curved, convex curved slope, or a stepped structure, which is continuous from the front and back main surfaces, and the material is softer than the silicon semiconductor wafer, and when laminated by sandwiching the wafer, It is a wafer-like plate made of a plastic material that has sufficient strength and is chemically resistant.

More specifically, whether the chamfer etching process is performed before the wrapping process, or whether the chamfer etching process is performed after the wrapping process;
Alternatively, the chamfer etching process is performed after the entire surface etching process.

The entire surface etching treatment may be performed by either acid etching or alkali etching.

(Function) When etching only the chamfered portion of a silicon semiconductor wafer, the main surfaces on both sides of the silicon semiconductor wafer are not targeted, and contact with the etching solution is prevented by an appropriate cover. There is a need. In the above-mentioned Japanese Patent Application Laid-Open No. 62-134935, as a measure to prevent contact with the etching solution, a plurality of silicon semiconductor wafers are stacked directly on top of each other (without intervening spacers) and sandwiched and stacked with chucks. However, under such conditions, the main surfaces of the stacked silicon semiconductor wafers that are in contact with each other are scratched.
Alternatively, the etching liquid may penetrate into the interior from the outer periphery of the main plane and cause irregular partial etching, making it impossible to obtain a mirror surface with high surface precision even in the subsequent mirror finishing process. Part of it remains in a non-mirrored state.

In the present invention, silicon semiconductor wafers are stacked alternately using a spacer that does not corrode with an etching solution, that is, a spacer that is resistant to corrosion, preferably an elastic spacer, and is bonded to each other by applying pressure. Therefore, the etching solution is prevented from coming into contact with the main surfaces of the silicon semiconductor wafers, and since the silicon semiconductor wafers do not come into direct contact with each other, scratches are prevented, or the outer periphery of the main planes is prevented from being exposed to the etching solution. This prevents irregular etching and removal due to intrusion.

The spacer may be any spacer as long as it prevents the etching solution from entering the main surface of the silicon semiconductor wafer and effectively etches the chamfered portion, and spacers of various shapes are available as described in the examples below. Conceivable.

Furthermore, the requirements for the material of the spacer are as follows:
The spacer must be at least softer than the silicon semiconductor wafer and must have appropriate elasticity, but its strength must also be sufficient to hold the silicon semiconductor wafers when they are sandwiched and stacked. As for the material, plastics such as vinyl chloride resin, fluororesin, and other synthetic rubbers are suitable for use. The material of the spacer must have chemical resistance as described above, which is also important in order not to contaminate the silicon semiconductor wafer. In the case of acid etching, the liquid temperature is at most 40°C, but in the case of alkaline etching, higher temperatures are used, so heat resistance is also required like fluororesin.
The finish of the main surface of the spacer has a flatness at least comparable to that of a silicon semiconductor wafer, and the surface roughness does not require particularly smoothness. These materials can be appropriately selected through experiments depending on the degree of pressure and the material used for crimping, and since soft materials are easily deformed and adhere closely to minute irregularities on the main surface of the silicon semiconductor wafer, there are few problems.

The etching solution for etching the chamfer in the present invention is a known etching solution used for etching silicon semiconductor wafers, such as a mixture of hydrofluoric acid (50%): nitric acid (70%): acetic acid in a ratio of 3:5:3.
A mixed acid mixed at a ratio of .

Further, as the entire surface etching treatment (conventionally referred to simply as etching) in the present invention, any conventionally known acid etching or alkali etching can be applied.

Acid etching improves the smoothness of the microscopic surface of the silicon semiconductor wafer, but there is a problem in that the macroscopic dimensional accuracy deteriorates. In contrast,
When alkaline etching is performed, the macroscopic dimensional accuracy of the silicon semiconductor wafer remains intact, but the microscopic surface becomes rough.

Therefore, by combining alkali etching of the entire surface and chamfer etching, you can take advantage of the advantage of alkaline etching that macroscopic dimensional accuracy is not compromised, and in addition, etching the chamfer increases the smoothness of the chamfer. This has the advantage that the disadvantage of roughening of the microscopic surface due to etching is suppressed.

Furthermore, when machining and finishing the chamfered portion with a diamond grindstone, the smaller the grain size of the abrasive grains, the smoother the surface can be obtained even with a smaller amount of etching. Also,
When the abrasive grain size is reduced to about #3000, it is possible to form a microscopically smooth surface of the chamfer while accurately maintaining the dimensional accuracy of the chamfer using alkali etching. The smoothness of the chamfered portion needs to be approximately the same as that of the mirror polished surface, but this can be achieved by controlling the amount of etching removal and the abrasive grain size of the diamond grindstone. The level of smoothness required for the chamfer is to prevent crystalline deterioration of the wafer due to concentration of thermal stress during heat treatment in the integrated circuit device manufacturing process, as well as to prevent contaminants from adhering to the valleys of the microscopic irregularities of the chamfer. It must be to the extent that no residue remains.

(Example) The method of the present invention will be explained below based on FIGS. 2 to 13 of the accompanying drawings.

FIG. 2 is a flowchart showing an example of the method of the present invention. In the same figure, A and B are respectively a slicing process and a mechanical chamfering process similar to the conventional method shown in FIG. F is a chamfer etching process in which a plurality of mechanically chamfered silicon semiconductor wafers are sandwiched and stacked with corrosion-resistant spacers interposed, and then immersed in an etching solution to etch only the chamfered parts. C, D and E
This method includes a lapping process, an entire surface etching process, and a polishing process similar to the conventional method, but differs from the conventional method in that a silicon semiconductor wafer that has been subjected to a chamfer etching process is processed.

FIG. 3 is a flowchart showing another example of the method of the present invention. In the figure, A, B, and C are respectively a slicing process, a mechanical chamfering process, and a wrapping process similar to the conventional method shown in FIG. F is a chamfer etching step in which a plurality of lapped and mechanically chamfered silicon semiconductor wafers are sandwiched and stacked with corrosion-resistant spacers interposed therebetween, and then immersed in an etching solution to etch only the chamfered portions. D is an entire surface etching step similar to the conventional method, but differs from the conventional method in that the entire surface of the silicon semiconductor wafer, which has been subjected to the chamfer etching process, is immersed in an etching solution. E is also a polishing step similar to the conventional method shown in FIG.

FIG. 4 is a block diagram showing another example of the method of the present invention. In the figure, A, B, C, and D are respectively a slicing process, a mechanical chamfering process, a wrapping process, and an entire surface etching process similar to the conventional method shown in FIG. F is a chamfer etching process in which a plurality of mechanically chamfered silicon semiconductor wafers that have been fully etched are sandwiched and stacked with corrosion-resistant spacers interposed, and then immersed in an etching solution to etch only the chamfered parts. . E is a polishing step similar to the conventional method shown in FIG.

In the above steps, the slicing step A, the mechanical chamfering step B, the lapping step C, the entire surface etching step D (conventionally simply referred to as an etching step), and the polishing step E are well known,
A detailed explanation thereof will be omitted. As mentioned above, both acid etching and alkali etching can be applied as the entire surface etching treatment, but each has its advantages and disadvantages, and which etching to use is determined appropriately depending on the intended use of the final product. do it.

The chamfer etching process will now be explained with reference to FIGS. 5 to 13. FIG. 5 is an explanatory diagram showing the state of implementation of the chamfer etching process. In the figure, reference numeral 2 denotes silicon semiconductor wafers, and a plurality of silicon semiconductor wafers 2 are sandwiched and laminated to form a laminate X with corrosion-resistant spacers 6 interposed in close contact. Note that if both surfaces of the silicon semiconductor wafer 2 are wetted with a non-etching liquid or a viscous liquid, such as water, and then the spacers 6 are interposed, the adhesion between the two becomes extremely good.

The laminate X is placed between a fixed support wall 8 and a movable pressing wall 10 of a tightening device Y, which will be described later, and is tightened. It is immersed in etching solution W. In this state, only the portion of the silicon semiconductor wafer 2 that is not in close contact with the spacer 6, that is, the chamfered portion 12, is exposed in the etching solution W.
For example, as shown by the dotted line in FIG. On the other hand, the portion of the silicon semiconductor wafer 2 that is in close contact with the spacer 6 does not come into contact with the etching solution W and is therefore not etched. In this way, only the chamfered portion 12 of the silicon semiconductor wafer 2 is etched.

Corrosion-resistant spacer 6 used in the method of the present invention
Examples of the shape include the following, but it is needless to say that the shape is not limited to these examples. The most common type of spacer is a corrosion-resistant spacer 6a (FIG. 7) whose side surface is the same as that of a silicon semiconductor wafer. In this case, when arranging the silicon semiconductor wafer and the spacer, it is necessary to align the orientation flat portions, and it is convenient to use a special jig for arranging, which will be described later. A spacer 6b (FIG. 8) which is corrosive and has a tapered portion u provided around the entire circumference of the periphery may also be used. With this shape, the etching solution can easily enter the peripheral edge of the silicon semiconductor wafer, allowing for good etching. 6c (No. 9
) can also be used. This has the same effect as above. 6d with a step t all around the circumferential side of a corrosion-resistant spacer (Fig. 10)
can also be used. This also has the same effect as above. A structure 6e (FIG. 11) in which an opening or a thin wall portion h is formed in the corrosion-resistant central portion is preferable for another purpose. In this case, there is an advantage that when tightened using a tightening jig to be described later, the tightening effect is greater and the intrusion of etching liquid is reduced accordingly. It is also preferable that the spacer 6 has elasticity, since this will increase the tightening effect accordingly.

There are various cross-sectional structures of the peripheral edge of the spacer as described above, but the purpose of this is to ensure that the shape of the chamfered portion of the silicon semiconductor wafer after etching is almost uniform in the radial direction of the chamfered portion.
If you wish to inherit the cross-sectional shape of the mechanical chamfer almost as is, use 6c with a recessed part v.
is preferred. In addition, if the etching progresses particularly at the outer peripheral edge of the chamfered part and you want the outer peripheral edge to be more rounded than the shape when machine chamfered,
b is preferred. 6d can also be used in place of 6c with almost the same effect. In this manner, the method of the present invention can complement the mechanical chamfering process by appropriately adjusting the cross-sectional shape of the peripheral edge of the spacer. In particular, when chamfering the base crystal substrate of an epitaxial wafer, the angle of inclination with respect to the main surface is small, in some cases about 10°.
For this reason, the outer edge of the wafer may be extremely thin, but in this case, if chamfer etching is performed with a step structure as shown in 6d, etching will proceed faster near the transition area between the main surface and the chamfer, so the machine The cross-sectional shape when chamfering can be maintained as is.

FIG. 12 is an isolated perspective view showing an alignment jig 14 as an example of an apparatus for creating a laminate X of silicon semiconductor wafers 2 and corrosion-resistant spacers 6. The alignment jig 14 has a semi-cylindrical main body 18 which has a flat part 16 formed at the bottom corresponding to the orientation flat part of the silicon semiconductor wafer 2 and has an inner diameter that matches the outer diameter of the silicon semiconductor wafer 2. A pair of support columns 22, 22 are erected at one end of the main body portion 18, with a gap 20 in between. The laminate X can be easily formed by sequentially stacking the corrosion-resistant spacer 6 and the silicon semiconductor wafer 2 on the semi-cylindrical main body 18 from the support column 22 side while aligning them. Note that a known etching solution may be used for etching the chamfered portion, but as mentioned above, for example, hydrofluoric acid (50%): nitric acid (70%): acetic acid in a ratio of 3:5:3. Use a mixed acid. Further, as the processing conditions, for example, immersion at 35° C. for about 30 seconds is sufficient. Furthermore, the stacked body X of silicon semiconductor wafers may be left standing in the etching solution, or may be rotated in the etching solution.

Laminated body X of multiple silicon semiconductor wafers 2
As shown in FIG. 13, the tightening device Y includes a side U-shaped main body portion 32 consisting of a lower arm 26, an upper arm 28, and a connecting portion 30 connecting the base ends of the lower arm 26 and the upper arm 28. A fixed support wall 8 is provided at the tip of the lower arm 26, and a fastener 34 is attached to the tip of the upper arm 28 in a vertically movable manner and has a movable pressing wall 10 at the tip. You can use whatever you have. The stacked body X of semiconductor wafers 2 is placed between the fixed support wall 8 and the movable pressing wall 10 of the clamping device Y, and is clamped by lowering the movable pressing wall 10. The fastener 34 is attached to the upper arm 28.
Any known means may be used to attach the upper arm 28 so as to be movable up and down, but for example, a screw hole may be provided in the upper arm 28, and a thread groove may be formed in the screw hole 28 on the side surface of the fastener 34 so that the fastener 34 can be moved up and down. Just screw it in. In this case, the movable pressing wall 10
It goes without saying that the fasteners 34 are movably attached to each other so that the fasteners 34 can rotate. Note that 36 is a guide plate whose tip end is connected to the movable pressing wall 10. In addition, the guide plate 36
A recessed groove portion 38 is provided at the base end portion of the main body portion 32 to be slidably inserted into the connecting portion 30 of the main body portion 32.
Therefore, when the movable pressing wall 10 is moved up and down, the guide plate 36 also moves up and down along the connecting portion 30, and the movement of the movable pressing wall 10 is accurately guided in the vertical direction.

(Effects of the Invention) As described above, according to the method of the present invention, when etching the chamfered portion of a silicon semiconductor wafer, the main surfaces of the silicon semiconductor wafers that are closely held together are not scratched, or the wafer This has the effect that irregular partial etching does not occur on the outer peripheral surface of the main plane, and the smoothness of the entire surface of the chamfered portion can be improved.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing a conventional method for manufacturing a silicon semiconductor wafer, FIG. 2 is a flowchart showing an example of a method for manufacturing a silicon semiconductor wafer according to the present invention, and FIG. 3 is a flowchart showing a method for manufacturing a silicon semiconductor wafer according to the present invention. FIG. 4 is a flow chart showing another example of the method of manufacturing a silicon semiconductor wafer according to the present invention, FIG. 5 is an explanatory diagram showing one embodiment of the method of the present invention, and FIG. The figure is an explanatory diagram showing a state in which a chamfered portion of a silicon semiconductor wafer is etched.
11 are explanatory diagrams showing deformation of the shape of a corrosion-resistant spacer that can be used in the method of the present invention, FIG. 12 is a perspective view showing an example of an alignment jig that can be used in the method of the present invention, and FIG. 13 FIG. 1 is a perspective view showing an example of a fastener used in the method of the present invention. 2... Silicon semiconductor wafer, 6... Spacer, 8... Fixed support wall, 10... Movable pressing wall, 1
2... Chamfered portion, X... Semiconductor wafer stack,
Y...Tightening device, W...Etching liquid, H...
…container.

Claims (1)

[Claims] 1. A slicing step of slicing a single crystal silicon semiconductor ingot into thin plates using a diamond cutter or the like to obtain a silicon semiconductor wafer;
a mechanical chamfering step of mechanically removing the peripheral corners of the silicon semiconductor wafer obtained by slicing; a wrapping step of polishing both sides of the mechanically chamfered silicon semiconductor wafer; and a wrapping process. manufacturing a silicon semiconductor wafer comprising: a full-face etching step of immersing the etched silicon semiconductor wafer in an etching solution to etch the entire surface; and a polishing step of mirror-polishing one or both sides of the etched silicon semiconductor wafer. In the method,
A plurality of mechanically chamfered silicon semiconductor wafers are sandwiched and stacked with spacers interposed between them, and then immersed in an etching solution to perform a chamfer etching process in which only the chamfered parts are etched, and the spacers are attached to the silicon semiconductor wafers. It has approximately the same dimensions as the wafer, and its peripheral edge has a straight, concave curved, or convex curved slope in its cross-sectional shape that is continuous to the front and back principal surfaces throughout the entire wafer, or A method for manufacturing a silicon semiconductor wafer, which is a wafer-like plate made of a plastic material that has a stepped structure, is softer than a silicon semiconductor, has sufficient strength during the sandwiching and stacking process, and is chemically resistant. . 2. The method of manufacturing a silicon semiconductor wafer according to claim 1, wherein the chamfer etching process is performed before the wrapping process. 3. The method of manufacturing a silicon semiconductor wafer according to claim 1, wherein the chamfer etching process is performed after the wrapping process. 4. The method of manufacturing a silicon semiconductor wafer according to claim 1, wherein the chamfer etching process is performed after the entire surface etching process. 5. The method of manufacturing a silicon semiconductor wafer according to claim 1, 2, 3 or 4, wherein the entire surface etching treatment is carried out by acid etching or alkali etching.