JPH0358201B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a gain-switchable transistor circuit, especially a gain-switchable amplifier circuit that is often used in analog circuits, etc. This invention relates to a gain switching circuit that makes it possible to change the AC gain without changing the DC potential of the circuit.

(Prior Art) FIG. 1 shows a conventionally used gain switching circuit, which has a bias voltage 11 and a capacitor 10 at its base, transistors 4 and 5 at the collector of a transistor 8 which receives an input signal from an input terminal 18,
The emitters of transistors 6 and 7 are connected in common, and the collectors of transistors 4, 5, and 6 are connected to the connection points of resistors 1, 2, and 3 connected in series as loads, and the collectors of transistor 7 and resistor 3 are connected to each other. An output terminal 13 is taken out from the connection end. Resistor 9 is the emitter resistance of transistor 8 and is connected to reference potential terminal 1.
Connected to 9. Transistors 4, 5, 6,
By setting any one of the control terminals 14 to 17 connected to the base of the transistor 7 to a high level, the load resistances 1 to 3 of the transistor 8 are switched, and the AC gain is switched. However, since the base bias voltage 11 of the transistor 8 is constant, the current flowing through the load resistors 1-3 is constant, and therefore, when the load resistors 1-3 are switched by the control signals applied to the control terminals 14-17. , there was a problem that the DC potential of the output terminal 13 changed.

(Problems to be Solved by the Invention) An object of the present invention is to obtain a transistor circuit whose output DC potential does not change due to gain switching.

(Means for Solving Problems) The transistor circuit of the present invention includes a plurality of resistors connected in series between a voltage supply terminal and an output terminal, and a signal current corresponding to an input signal as well as a bias current. a first current source generated as;
a plurality of first switches for changing the number of resistors among the plurality of resistors to which an output current from the first current source is to be supplied, each having one end connected to the first current source; a plurality of first switches connected to each other, the other ends of which are respectively connected to different locations among the connection points of the output terminal and the plurality of resistors; and a second switch that generates a bias current according to the bias current source. a current source, and a plurality of second switches provided corresponding to the plurality of first switches, respectively.
a switch, each corresponding first switch supplying an output current from the first current source depending on the number of resistors in the plurality of resistors; One end of each resistor is connected to the second current source, and the other end of each resistor is connected to the second current source so as to determine the number of resistors among the plurality of resistors that supply current to keep the DC potential of the output terminal constant. A plurality of second switches each connected to a voltage supply terminal and a different connection point of the plurality of resistors, and one of the plurality of first switches in a conductive state in response to control information. and means for bringing a second switch corresponding to the first switch in a conductive state into a conductive state.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 2 is a circuit diagram showing the principle of the gain switching circuit of the present invention, and is a circuit in which the output DC potential does not change even when the AC gain is switched. That is, DC bias 3
7, a capacitor 36, and n resistors 20 (n is an integer) between the collector of the transistor 30 connected to the collector of the transistor 34 which receives the input signal through the input terminal 44 and the power supply voltage supply terminal. 21, 22, 23, 24, 25
are connected in series, resistors 20, 21, 22, 2
3, 24, and 25 are the 1st, 2nd, n/2, n/2+1, n- 1, and n-th resistors, and the magnitude of each resistance is R ₁ , R ₂ , R _o/2 , R _o/ Let ₂₊₁ +1, R _o-1 , R _o .
The first transistor 33 has its collector connected to the power supply voltage supply terminal, the second transistor 32 has its collector connected to the common connection point of the resistors 20 and 21, and the collector is connected to the common connection point of the resistors 22 and 23. and the emitters are transistors 32 and 33
The transistor 31 whose collector is common to the transistor 31 is the n/2+1st transistor, the transistor 28 whose collector is common to the transistor 31 is the n/2+2nd transistor, and the transistor 29 whose collector is connected to the common connection point of the resistors 24 and 25 is the n+1st transistor. The transistor 30 is assumed to be the (n+2)th transistor. The first to (n/2+1)th transistors have a common emitter connected to the collector of the transistor 35. The transistors from n/2+2 to n+2 have a common emitter and are transistor 34.
connected to the collector. 1st and n+
The bases of the second, second and (n+1)th transistors, and third and nth transistors are commonly connected to the control terminals C ₁ , C ₂ , and C ₃ respectively, and similarly, the bases of the (n/2+1) and The bases of the n/2+2 transistors are commonly connected to the control terminal C _o/2+1 . terminal 4
1, 42, and 43 are control terminals C ₁ , C ₂ , and _Co/2+1 . The emitters of transistors 34 and 35 are connected to a reference potential via resistors 26 and 27, respectively. The bases of transistors 34 and 35 are biased by direct voltage sources 37 and 38, respectively. Terminals 39 and 45 are a power supply voltage supply terminal and a reference potential, respectively. Terminals 40 and 44 are an output terminal and an input terminal, respectively. Now, the resistances R ₁ , R ₂ ...
...The values of R _o-1 and R _o are determined as follows.

R ₂ = R ₃ =...= R _o-1 = R... (1) R ₁ = R _o = n/2R... (2) The AC gain for the input signal input to the input terminal 44 is determined by the control terminal C. By setting any one of ₁ , C _{2 , .} The DC potential V _ODC of the output terminal 40 is determined by the power supply voltage Vcc and the resistors R ₁ ,
If the values of R ₂ , ..., R _o-1 , R _o are determined as shown in equations (1) and (2) and the collector currents of the transistors 34 and 35 are made equal to I, then the control terminals C ₁ , C ₂ , …Even if any one of C _o/2+1 is set to high level, the output terminal 40
The DC potential V _ODC of is constant as shown in equation (3).

V _ODC =Vcc-2(n-1)RI (3) That is, in the present invention, even if the AC gain is switched, the output DC potential remains constant and does not change.

In this way, in contrast to the conventional example in which the output DC potential fluctuates when the AC gain is switched, in the present invention, the output DC potential is constant. If the DC potential of the output fluctuates when switching, it will have an effect on an inconvenient circuit.

Next, a specific circuit according to an embodiment of the present invention is shown in FIG. 3 and will be described. Resistance 46, 47, 48, 49
are connected in series between the power supply voltage supply terminal 63 and the output terminal 64, the collector of the transistor 52 is connected to the common connection point of the resistors 47 and 48, the base is connected to the control terminal 67, and the emitter is connected to the collector of the transistor 58. 53 collector is resistor 4
8 and 49, the base is connected to the control terminal 66, the emitter is connected to the collector of the transistor 58, the collector of the transistor 54 is connected to the output terminal, the base is connected to the control terminal 65, and the emitter is connected to the transistor 5.
The collector of the transistor 55 is connected to the common connection point of the resistors 47 and 48, the base is connected to the control terminal 67, the emitter is connected to the collector of the transistor 59, and the collector of the transistor 56 is connected to the common connection point of the resistors 46 and 47. The base of the transistor 57 is connected to the control terminal 66, the emitter is connected to the collector of the transistor 59, the collector of the transistor 57 is connected to the power supply voltage supply terminal, the base is connected to the control terminal 65, the emitter is connected to the collector of the transistor 59, and the collector of the transistor 58 is connected to the collector of the transistor 52. ,5
3,54 common emitter and base is capacitor 6
The emitter of the transistor 59 is connected to one end of the resistor 50, the collector of the transistor 59 is connected to the common emitter of the transistors 55, 56, and 57, the base is connected to the voltage source 61, and the emitter of the transistor 59 is connected to one end of the resistor 50.
One end of the resistor 50 is connected to the emitter of the transistor 558 and the other end is connected to the reference potential, one end of the resistor 51 is connected to the emitter of the transistor 59 and the other end is connected to the reference potential, and the voltage source 60 is connected to the emitter of the transistor 558. The voltage source 61 is connected between the base of the transistor 59 and the reference potential, and the capacitor 62 is connected between the input terminal and the base of the transistor 58. Terminals 63, 64, 68, and 69 are a power supply voltage supply terminal, an output terminal, an input terminal, and a reference potential, respectively, and terminals 65, 66, and 67 are control terminals. In Figure 3, the power supply voltage is Vcc, and the values of resistors 46, 47, 48, 49, and 50 are respectively
R ₁ , R ₂ , R ₃ , R ₄ , R ₅ and transistor 58,
Let the collector currents of 59 be I ₁ and I ₂ respectively,
The DC potential V _ODC and AC gain G _AC of the output terminal 64 when any one of the control terminals 65, 66, and 67 is set to high level are as shown below.

When only the control terminal 65 is at high level V _ODC = Vcc- (R ₁ + R ₂ + R ₃ + R ₄ ) I ₁ ... (4) G _AC = R ₁ + R ₂ + R ₃ + R ₄ /R ₅ ... (5) becomes.

When only the control terminal 65 is at high level V _ODC = Vcc - {(R ₁ + R ₂ + R ₃ ) I ₁ + R ₁ I ₂ }
...(6) G _AC = R ₁ + R ₂ + R ₃ /R ₅ ...(7).

When only the control terminal 67 is at high level V _ODC = Vcc− {(R ₁ +R ₂ )I ₁ +(R ₁ +R ₂ )I ₂ }
...(8) G _AC = R ₁ + R ₂ /R ₅ ...(9).

So that V _ODC in equations (4), (6), and (8) are equal.
If R ₁ , R ₂ , R ₃ , R ₄ , I ₁ , and I ₂ are determined, even if the control terminals 65, 66, and 67 are switched to change the AC gain G _AC , the DC potential V _ODC of the output terminal 64 will be It does not change. As an example, if R ₁ = R ₄ = 2R ... (10) R ₂ = R ₃ = R ... (11) I ₁ = I ₂ = I ... (12), then (4), (6), ( V _ODC in equation 8) is V _ODC = Vcc - 6RI, and the output DC potential does not change even if the AC gain is switched. As another example, let R ₁ = R ₂ = 2R ……(14) R ₃ = R ₄ = R ……(15) I ₁ = I ……(16) I ₂ = 1/2 ……(17) V _ODC in equations (4), (6), and (8) is V _ODC = Vcc - 6RI (18), and the DC potential at the output terminal does not change even if the AC gain is switched.

As explained above, while in the conventional example the output DC potential changes when the AC gain is switched, in the present invention the DC potential at the output terminal does not change even when the AC gain is switched, so character multiplexing is possible. If the DC potential of the output fluctuates when the AC gain is switched, such as a shadow circuit in a broadcast receiver, this will have an effect on inconvenient circuits.

[Brief explanation of drawings]

FIG. 1 shows a conventionally used gain switching circuit, FIG. 2 shows a gain switching circuit showing the principle of the present invention, and FIG. 3 is a circuit diagram showing an embodiment of the invention. 1, 2, 3, 9, 20, 21, 22, 23, 2
4, 25, 26, 27, 46, 47, 48, 4
9, 50, 51...Resistance, 4, 5, 6, 7, 8,
28, 29, 30, 31, 32, 33, 34, 3
5, 52, 53, 54, 55, 56, 57, 5
8,59...transistor, 11,37,38,
60, 61, ... voltage source, 10, 36, 62 ...
Capacitor, 12, 39, 63... Power supply voltage supply terminal, 13, 40, 64... Output terminal, 18, 4
4, 68...Input terminal, 14, 15, 16, 1
7, 41, 42, 43, 65, 66, 67... control terminal, 19, 45, 69... reference potential.

Claims (1)

[Claims] 1. A plurality of resistors connected in series between a voltage supply terminal and an output terminal, a first current source that generates a signal current according to an input signal as an output current along with a bias current, and the first current source. a plurality of first switches for changing the number of resistors among the plurality of resistors to be supplied with an output current from the plurality of resistors, each having one end connected to the first current source and each other having one end connected to the first current source; a plurality of first switches respectively connected to different points among the output terminal and the connection points of the plurality of resistors; a second current source that generates a bias current according to the bias current source; A plurality of second switches provided respectively corresponding to the plurality of first switches,
said plurality of resistors, each corresponding first switch supplying a bias current from said second current source in accordance with the number of resistors in said plurality of resistors supplying an output current from said first current source; one end of each is connected to the second current source and the other end of each is connected to the voltage supply terminal and the plurality of a plurality of second switches each connected to a different point among the connection points of the resistors, and one of the plurality of first switches in response to control information, and one of the plurality of first switches is brought into a conductive state, and the second switch is brought into conduction state. and means for bringing into conduction a second switch corresponding to the first switch.