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JPH0358232B2 - - Google Patents
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JPH0358232B2 - - Google Patents

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Publication number
JPH0358232B2
JPH0358232B2 JP59132649A JP13264984A JPH0358232B2 JP H0358232 B2 JPH0358232 B2 JP H0358232B2 JP 59132649 A JP59132649 A JP 59132649A JP 13264984 A JP13264984 A JP 13264984A JP H0358232 B2 JPH0358232 B2 JP H0358232B2
Authority
JP
Japan
Prior art keywords
signal
circuit
comb filter
output
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59132649A
Other languages
Japanese (ja)
Other versions
JPS6112176A (en
Inventor
Norio Ubukata
Kasuke Iwafune
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP59132649A priority Critical patent/JPS6112176A/en
Priority to KR1019850004111A priority patent/KR900003078B1/en
Priority to IN487/MAS/85A priority patent/IN164384B/en
Publication of JPS6112176A publication Critical patent/JPS6112176A/en
Publication of JPH0358232B2 publication Critical patent/JPH0358232B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • H04N5/213Circuitry for suppressing or minimising impulsive noise
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Picture Signal Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は映像信号の雑音低減回路に係り、例え
ばヘリカルスキヤンニング方式VTRに用いられ、
特に、入力信号が小レベル、中レベルの時出力信
号周波数特性を平坦とし得、SN比を改善し得、
垂直方向解像度の劣化の少ない雑音低減回路を提
供することを目的とする。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a noise reduction circuit for video signals, and is used, for example, in a helical scanning VTR.
In particular, when the input signal is at a small or medium level, the output signal frequency characteristics can be flattened, and the SN ratio can be improved.
An object of the present invention is to provide a noise reduction circuit that causes less deterioration in vertical resolution.

従来技術及びその問題点 第5図は例えばVTRの輝度信号再生系に設け
られている従来の雑音低減回路の一例のブロツク
系統図を示す。同図において、端子1に入来した
信号a(第6図A)は高域フイルタ2にて例えば
1MHz以上の周波数の信号b(同図B)とされ、リ
ミツタ3で振幅制限されて略雑音成分e(同図C)
とされた後係数回路4を介して減算器5に供給さ
れ、ここで信号aから雑音成分を減算されて信号
d(同図D)とされて端子6より取出される。
Prior Art and Its Problems FIG. 5 shows a block system diagram of an example of a conventional noise reduction circuit provided in a luminance signal reproduction system of a VTR, for example. In the figure, a signal a (FIG. 6A) input to terminal 1 is passed through high-pass filter 2, for example.
The signal b (Figure B) with a frequency of 1 MHz or higher is amplitude limited by the limiter 3 and becomes approximately a noise component e (Figure C).
After being determined as , the signal is supplied to the subtracter 5 via the coefficient circuit 4, where the noise component is subtracted from the signal a, and the signal d (D in the figure) is outputted from the terminal 6.

このものは、エツジ部分に雑音成分が残る一
方、1MHz以下の低減雑音が残る問題点があつた。
This had the problem that while noise components remained in the edge portion, reduced noise of 1MHz or less remained.

第7図は従来のH相関雑音低減回路の一例のブ
ロツク系統図を示す。同図において、端子1に入
来した信号は1H遅延回路7にて1H遅延されて減
算器8に供給され、ここで、入力信号から減算さ
れた後リミツタ3で振幅制限されて略雑音成分と
される。減算器5において入力信号からリミツタ
3の出力が減算されて雑音成分を低減された信号
が取出される。
FIG. 7 shows a block system diagram of an example of a conventional H-correlated noise reduction circuit. In the figure, the signal input to terminal 1 is delayed by 1H in 1H delay circuit 7 and then supplied to subtracter 8, where it is subtracted from the input signal and then limited in amplitude by limiter 3 to become a substantially noise component. be done. A subtracter 5 subtracts the output of the limiter 3 from the input signal to obtain a signal with reduced noise components.

このものは、ライン相関がある場合では雑音成
分をを十分に減算し得、第6図示の回路に比して
エツジ部分に雑音成分が残ることはなく、又、低
域雑音を十分に低減し得る。然るに、SN比の改
善度に関しては論理的には3dB程度とれるとこ
ろ、例えば1H遅延回路7の特性による劣化等の
ために実際には1.5〜2.0dB程度しかとれず、第8
図Aに示す如く、入力信号が小レベルの時の出力
信号はくし形特性が顕著となり、入力信号が大レ
ベルで出力信号レベルが大の時(同図B)に比し
て垂直方向解像度が劣化する等の問題点があつ
た。
This circuit can sufficiently subtract noise components when there is line correlation, does not leave any noise components at the edge parts compared to the circuit shown in Figure 6, and can sufficiently reduce low-frequency noise. obtain. However, although theoretically the degree of improvement in the SN ratio can be improved by about 3 dB, in reality it can only be improved by about 1.5 to 2.0 dB due to deterioration due to the characteristics of the 1H delay circuit 7, for example.
As shown in Figure A, when the input signal is at a low level, the output signal has a pronounced comb-shaped characteristic, and the vertical resolution is degraded compared to when the input signal is at a high level and the output signal level is high (Figure B). There were some problems, such as:

第9図は本出願人が先に昭和58年11月28日付の
特許願「映像信号の雑音低減回路」で提案した回
路の回路図を示す。同図において、端子1に入来
した信号を加算器9,10、1H遅延回路7、及
び高域フイルタ11、係数回路12を挿入された
帰還路からなる帰還形くし形フイルタ及びイコラ
イザ13を通し、この信号を減算器14にて入力
信号から減算し、この信号をスライス回路15を
通して得た信号とイコライザ13の出力とを加算
器16にて加算して取出すように構成されてい
る。
FIG. 9 shows a circuit diagram of a circuit previously proposed by the present applicant in the patent application ``Video Signal Noise Reduction Circuit'' dated November 28, 1981. In the figure, a signal input to terminal 1 is passed through a feedback comb filter and equalizer 13 consisting of adders 9, 10, a 1H delay circuit 7, and a feedback path in which a high-pass filter 11 and a coefficient circuit 12 are inserted. , this signal is subtracted from the input signal by a subtracter 14, and the signal obtained through the slice circuit 15 and the output of the equalizer 13 are added together by an adder 16 and extracted.

このものは、特に高周波数帯域でのSN比を例
えば6〜10dB程度に大幅に改善し得、又、第1
0図Cに示す如く、入力信号が大レベルの時では
出力信号レベルを大にとり得、垂直方向解像度の
劣化が少ない。然るに、第10図Bに示す入力信
号が中レベルの時及び同図Cに示す入力信号が小
レベルの時では出力信号は夫々くし形特性をもつ
ようになり、垂直方向解像度が劣化し、くし形特
性を鋭くする分だけ第7図示の回路よりも垂直方
向解像度が劣化する等の問題点があつた。
This device can significantly improve the SN ratio, especially in the high frequency band, to about 6 to 10 dB, and also
As shown in FIG. 0C, when the input signal is at a high level, the output signal level can be high, and there is little deterioration in vertical resolution. However, when the input signal shown in FIG. 10B is at a medium level, and when the input signal shown in FIG. There were problems such as the vertical resolution being worse than the circuit shown in FIG. 7 due to the sharpness of the shape characteristics.

問題点を解決するための手段及びその作用 本発明は、入力映像信号を1H期間遅延して得
た信号と該入力映像信号とを加算して取出す第1
のくし形フイルタと、入力映像信号から第1のく
し形フイルタの出力を減算して取出す第2のくし
形フイルタと、記録時第2のくし形フイルタの出
力中比較的小レベルの信号を伸長して上記第1の
くし形フイルタの出力と加算して取出す伸長回路
と、再生時上記第2のくし形フイルタの出力を圧
縮して上記第1のくし形フイルタの出力と加算し
て取出す回路とからなる構成として上記問題点を
解決したものであり、以下、図面と共にその一実
施例について説明する。
Means for Solving the Problems and Their Effects The present invention provides a first method that adds and extracts a signal obtained by delaying an input video signal for 1H period and the input video signal.
a comb filter, a second comb filter that subtracts the output of the first comb filter from the input video signal, and expands a relatively low level signal during recording from the second comb filter. an expansion circuit that compresses the output of the second comb filter during playback and adds the output to the output of the first comb filter and extracts the output; The above-mentioned problems are solved as a configuration consisting of the following, and one embodiment thereof will be described below with reference to the drawings.

実施例 第1図は本発明回路の一実施例のブロツク系統
図を示し、同図中、第9図と同一構成成分には同
一番号を付してその説明を省略する。このもの
は、減算器14と加算器16との間に、連動のス
イツチS1,S2、スライス回路15小中レベル伸長
回路17(スライス回路15におけるスライスレ
ベル以下の小〜中レベル信号を伸長するように構
成されている)を設けたもので、その他の構成は
第9図示の回路と同様である。
Embodiment FIG. 1 shows a block system diagram of an embodiment of the circuit of the present invention. In the figure, the same components as in FIG. 9 are given the same numbers and their explanations will be omitted. This device has interlocking switches S 1 and S 2 between the subtracter 14 and the adder 16, a slice circuit 15 and a small to medium level expansion circuit 17 (which expands small to medium level signals below the slice level in the slice circuit 15). The other configuration is the same as the circuit shown in FIG. 9.

記録時、スイツチS1,S2をRec側に接続する。
帰還形くし形フイルタの出力のうちスライス回路
15のスライスレベル以下の小〜中レベル信号は
小中レベル伸長回路17にて伸長され、加算器1
6にてイコライザ13の出力と加算されて取出さ
れる。このようにすると、小〜中レベル信号もス
ライスレベルを越えて取出され、第2図の特性
に示す如く、端子6よりの垂直方向成分の信号は
スライスレベル以上では損失なく取出され、第9
図示の回路の特性に比してスライスレベル以上
では平坦となる。
When recording, connect switches S 1 and S 2 to the Rec side.
Among the outputs of the feedback comb filter, small to medium level signals below the slice level of the slice circuit 15 are expanded by a small to medium level expansion circuit 17 and sent to the adder 1.
6, it is added to the output of the equalizer 13 and taken out. In this way, small to medium level signals are also extracted beyond the slice level, and as shown in the characteristics in FIG. 2, the vertical component signal from terminal 6 is extracted without loss above the slice level.
Compared to the characteristics of the illustrated circuit, it becomes flat above the slice level.

これにより、入力信号がノイズレベル、中レベ
ル、大レベルの時の出力信号の周波数特性はくし
形特性とはならず、夫々第3図B,C,Dに示す
如く平坦となり、垂直方向解像度の劣化を生じな
い。なお、同図Aは入力信号がノイズレベル以下
の極く小レベルの場合の出力信号レベルであり、
くし形特性をもつ。
As a result, the frequency characteristics of the output signal when the input signal is at a noise level, a medium level, and a large level do not have a comb-shaped characteristic, but become flat as shown in Figure 3 B, C, and D, respectively, and the vertical resolution deteriorates. does not occur. Note that A in the figure shows the output signal level when the input signal is at an extremely low level below the noise level.
Has comb-shaped characteristics.

又、第2図の特性に示す如く、垂直方向成分
入力レベルがスライスレベル以下の場合、特性
に比してその成分が失なわれる割合が少ない。一
般に、スライスレベルは映像信号レベルに対して
十分小に選定されているので、スライス回路15
による垂直方向成分の損失は殆ど目立たない。
Furthermore, as shown in the characteristics of FIG. 2, when the vertical component input level is below the slice level, the rate at which that component is lost is small compared to the characteristics. Generally, the slice level is selected to be sufficiently small compared to the video signal level, so the slice circuit 15
The loss in the vertical component due to is hardly noticeable.

これに対して再生雑音は記録後に生じるので、
再生時にはスイツチS1,S2をPB側に接続して第
9図示の回路と同じ系路を介して雑音を低減す
る。このような信号処理を行なうと、垂直方向解
像度の劣化を第9図示のものに比して少なくし
得、帰還形くし形フイルタの大きなSN比改善度
を生かし得、大幅なSN比改善を行ない得る。
On the other hand, playback noise occurs after recording, so
During reproduction, switches S 1 and S 2 are connected to the PB side to reduce noise through the same circuit as the circuit shown in FIG. 9. By performing such signal processing, the deterioration of the vertical resolution can be reduced compared to the one shown in Figure 9, and the large degree of improvement in the S/N ratio of the feedback comb filter can be utilized, resulting in a significant S/N ratio improvement. obtain.

なお、スライス回路15の代りに小中レベル圧
縮回路でもよく、小中レベル伸長回路15の特性
と小中レベル圧縮回路の特性とを適当に選定すれ
ば、映像信号の損失を零にし得る。
Note that a small-medium level compression circuit may be used instead of the slice circuit 15, and if the characteristics of the small-medium level expansion circuit 15 and the characteristics of the small-medium level compression circuit are appropriately selected, the loss of the video signal can be reduced to zero.

又、小中レベル伸長回路17とスイツチS1との
間、或いは小中レベル伸長回路17とスイツチS2
との間に低減フイルタを接続すれば、減算器14
の出力の高域成分を低減し得、出力信号の周波数
特性は第4図に示す如く、低減では平坦、高域で
はくし形特性にし得る。
Also, between the small/medium level expansion circuit 17 and the switch S1 , or between the small/medium level expansion circuit 17 and the switch S2 .
If a reduction filter is connected between the subtractor 14
As shown in FIG. 4, the frequency characteristic of the output signal can be made flat in the reduction and comb-shaped in the high frequency range.

又、上記低減フイルタのカツトオフ周波数を適
当に選定することにより、高域くし形フイルタを
実現でき、記録時このような高域フイルタを用い
ると周知のように輝度信号の帯域を広くとり得、
帯域が広く、SN比の高い再生信号を得ることが
できる。
In addition, by appropriately selecting the cutoff frequency of the reduction filter, a high-pass comb filter can be realized, and when such a high-pass filter is used during recording, the band of the luminance signal can be widened, as is well known.
It is possible to obtain a reproduced signal with a wide band and a high SN ratio.

効 果 上述の如く、本発明になる映像信号の雑音低減
回路は、入力映像信号を1H期間遅延して得た信
号と入力映像信号とを加算して取出す第1のくし
形フイルタと、入力映像信号から第1のくし形フ
イルタの出力を減算して取出す第2のくし形フイ
ルタと、記録時第2のくし形フイルタの出力中比
較的小レベルの信号を伸長して上記第1のくし形
フイルタの出力と加算して取出す伸長回路と、再
生時上記第2のくし形フイルタの出力を圧縮して
上記第1のくし形フイルタの出力と加算して取出
す回路とより構成したため、出力信号の垂直方向
成分の損失は圧縮する際のスライスレベル以上で
生じることはなく、これにより、周波数特性はス
ライスレベル以上ではくし形特性にならずに平坦
になり、特に、入力信号が小レベル、中レベルの
時出力信号周波数特性を平坦とし得、SN比を大
幅に改善し得、垂直方向解像度の劣化が少ない等
の特長を有する。
Effects As described above, the video signal noise reduction circuit according to the present invention includes a first comb filter that adds and extracts a signal obtained by delaying an input video signal by 1H period and the input video signal, and a second comb filter that subtracts the output of the first comb filter from the signal and extracts the signal; and a second comb filter that extracts the signal by subtracting the output of the first comb filter; The output signal is Vertical component loss does not occur above the slice level during compression, and as a result, the frequency response becomes flat without becoming a comb-like characteristic above the slice level, especially when the input signal is at low or medium levels. It has features such as flat output signal frequency characteristics, significantly improved S/N ratio, and little deterioration of vertical resolution.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は夫々本発明回路の一実施例
のブロツク系統図及び垂直方向成分入力レベル対
垂直方向の出力レベル/入力レベル比特性図、第
3図は本発明回路の動作説明用出力信号周波数特
性図、第4図は本発明回路において記録時に低域
フイルタを用いた場合の出力信号周波数特性図、
第5図及び第6図は夫々従来回路の一例のブロツ
ク系統図及び動作説明用信号波形図、第7図及び
第8図は夫々従来回路の他の例のブロツク系統図
及び出力信号周波数特性図、第9図及び第10図
は夫々従来回路の更に他の例のブロツク系統図及
び出力信号周波数特性図である。 1……映像信号入力端子、6……出力端子、7
……1H遅延回路、9,10,16……加算器、
11……高域フイルタ、12……係数回路、13
……イコライザ、14……減算器、15……スラ
イス回路、17……小中レベル伸長回路、S1,S2
……スイツチ。
1 and 2 are a block system diagram and a vertical component input level versus vertical output level/input level ratio characteristic diagram of an embodiment of the circuit of the present invention, respectively, and FIG. 3 is for explaining the operation of the circuit of the present invention. Output signal frequency characteristic diagram. Figure 4 is an output signal frequency characteristic diagram when a low-pass filter is used during recording in the circuit of the present invention.
5 and 6 are a block system diagram and a signal waveform diagram for explaining operation of an example of a conventional circuit, respectively, and FIGS. 7 and 8 are a block system diagram and an output signal frequency characteristic diagram of another example of a conventional circuit, respectively. , 9 and 10 are a block system diagram and an output signal frequency characteristic diagram of still other examples of the conventional circuit, respectively. 1...Video signal input terminal, 6...Output terminal, 7
...1H delay circuit, 9, 10, 16...adder,
11...High-pass filter, 12...Coefficient circuit, 13
... Equalizer, 14 ... Subtractor, 15 ... Slice circuit, 17 ... Small and medium level expansion circuit, S 1 , S 2
...Switch.

Claims (1)

【特許請求の範囲】 1 入力映像信号を1H期間遅延して得た信号と
該入力映像信号とを加算して取出す第1のくし形
フイルタと、該入力映像信号から該第1のくし形
フイルタの出力を減算して取出す第2のくし形フ
イルタと、記録時該第2のくし形フイルタの出力
中比較的小レベルの信号を伸長して上記第1のく
し形フイルタの出力と加算して取出す伸長回路
と、再生時上記第2のくし形フイルタの出力を圧
縮して上記第1のくし形フイルタの出力と加算し
て取出す回路とより構成してなることを特徴とす
る映像信号の雑音低減回路。 2 該第1のくし形フイルタは、帰還形くし形フ
イルタであることを特徴とする特許請求の範囲第
1項記載の映像信号の雑音低減回路。 3 該伸長回路は、その入力側又は出力側に低域
フイルタを設けてなることを特徴とする特許請求
の範囲第1項又は第2項記載の映像信号の雑音低
減回路。
[Scope of Claims] 1. A first comb filter that adds and extracts a signal obtained by delaying an input video signal by 1H period and the input video signal, and a first comb filter that extracts a signal obtained by delaying the input video signal by a period of 1H; A second comb filter subtracts and extracts the output of the second comb filter, and a relatively low level signal during recording is expanded and added to the output of the first comb filter. Noise in a video signal, comprising: an expansion circuit for extracting the noise; and a circuit for compressing the output of the second comb filter during playback, adding it to the output of the first comb filter, and extracting the noise. reduction circuit. 2. The video signal noise reduction circuit according to claim 1, wherein the first comb filter is a feedback comb filter. 3. The video signal noise reduction circuit according to claim 1 or 2, wherein the expansion circuit is provided with a low-pass filter on its input side or output side.
JP59132649A 1984-06-27 1984-06-27 Noise reduction circuit of video signal Granted JPS6112176A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP59132649A JPS6112176A (en) 1984-06-27 1984-06-27 Noise reduction circuit of video signal
KR1019850004111A KR900003078B1 (en) 1984-06-27 1985-06-12 Noise reduction circuit for video signal
IN487/MAS/85A IN164384B (en) 1984-06-27 1985-06-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59132649A JPS6112176A (en) 1984-06-27 1984-06-27 Noise reduction circuit of video signal

Publications (2)

Publication Number Publication Date
JPS6112176A JPS6112176A (en) 1986-01-20
JPH0358232B2 true JPH0358232B2 (en) 1991-09-04

Family

ID=15086256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59132649A Granted JPS6112176A (en) 1984-06-27 1984-06-27 Noise reduction circuit of video signal

Country Status (3)

Country Link
JP (1) JPS6112176A (en)
KR (1) KR900003078B1 (en)
IN (1) IN164384B (en)

Also Published As

Publication number Publication date
KR860000772A (en) 1986-01-30
KR900003078B1 (en) 1990-05-07
IN164384B (en) 1989-03-04
JPS6112176A (en) 1986-01-20

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