JPH0359583B2 - - Google Patents
Info
- Publication number
- JPH0359583B2 JPH0359583B2 JP32178189A JP32178189A JPH0359583B2 JP H0359583 B2 JPH0359583 B2 JP H0359583B2 JP 32178189 A JP32178189 A JP 32178189A JP 32178189 A JP32178189 A JP 32178189A JP H0359583 B2 JPH0359583 B2 JP H0359583B2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- circuit
- emitter follower
- resistor
- gate array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はゲートアレイ形マスタスライス集積
回路に係り、特にその出力段のエミツタフオロワ
回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array type master slice integrated circuit, and particularly to an emitter follower circuit in an output stage thereof.
第１図は基本ゲート回路の一例を示す回路図
で、出力段にエミツタフオロワ回路を有する
CML（Current Mode Logic）回路を示す。図に
おいて、１ａ，１ｂおよび１ｃはこれを構成する
トランジスタ、２は共通のエミツタ抵抗、３はト
ランジスタ１ａおよび１ｂの共通のコレクタ抵
抗、４はトランジスタ１ｃのコレクタ抵抗、５は
エミツタフオロワ用トランジスタ、６はそのエミ
ツタ抵抗、７ａおよび７ｂはそれぞれトランジス
タ１ａおよび１ｂのベースに接続された論理入力
端子、８はトランジスタ１ｃのベースに接続され
た基準電圧入力端子、９コレクタ電圧VCC供給端
子、１０はエミツタ電圧VEE供給端子、１１はエ
ミツタフオロワ出力端子であり、この回路の論理
動作は周知であるので説明を省略する。
Figure 1 is a circuit diagram showing an example of a basic gate circuit, which has an emitter follower circuit in the output stage.
This shows a CML (Current Mode Logic) circuit. In the figure, 1a, 1b and 1c are transistors that constitute this, 2 is a common emitter resistance, 3 is a common collector resistance of transistors 1a and 1b, 4 is a collector resistance of transistor 1c, 5 is an emitter follower transistor, and 6 is a common emitter resistance. Its emitter resistors, 7a and 7b are logic input terminals connected to the bases of transistors 1a and 1b, respectively, 8 is a reference voltage input terminal connected to the base of transistor 1c, 9 is a collector voltage V CC supply terminal, and 10 is an emitter voltage. The V EE supply terminal 11 is an emitter follower output terminal, and since the logic operation of this circuit is well known, the explanation will be omitted.
ところで、従来のゲートアレイ形集積回路では
エミツタフオロワ回路のエミツタ抵抗６の値が一
定で電流駆動能力が一定であるので、負荷回路の
容量値によつてこの論理回路の動作遅延時間に差
異を生じ、論理設計に当つて支障があつた。電流
駆動能力の異つたエミツタフオロワ回路を幾種類
かを予め作り込んで適当に組合わせて使用するこ
とも考えられるが、組み込んだ回路の如何によつ
ては無駄を生じたり、能力不足になつたりする欠
点があつた。
By the way, in the conventional gate array type integrated circuit, the value of the emitter resistor 6 of the emitter follower circuit is constant and the current driving capability is constant, so the operation delay time of this logic circuit varies depending on the capacitance value of the load circuit. There was a problem in the logical design. It may be possible to create several types of emitter follower circuits with different current drive capacities in advance and use them in appropriate combinations, but depending on the type of circuits that are incorporated, this may result in waste or lack of capacity. There were flaws.
この発明は以上のような点に鑑みてなされたも
ので、回路に無駄を生じたり能力不足になること
なく、動作遅延時間のばらつきを小さくすること
ができるゲートアレイ形集積回路を提供すること
を目的とする。 The present invention has been made in view of the above points, and an object of the present invention is to provide a gate array type integrated circuit that can reduce variations in operation delay time without causing waste or lack of capacity in the circuit. purpose.
〔課題を解決するための手段〕
この発明はゲートアレイ形集積回路の出力段に
おけるエミツタフオロワ回路部のエミツタ抵抗を
並列接続された複数個の部分抵抗で構成しその配
線パターンを変更するようにしたものである。[Means for Solving the Problems] The present invention is such that the emitter resistor of the emitter follower circuit section in the output stage of a gate array type integrated circuit is composed of a plurality of partial resistors connected in parallel, and the wiring pattern thereof is changed. It is.
負荷回路の容量値に応じてエミツタフオロワ回
路の電流値を変えられるようにすることによつ
て、動作遅延時間のばらつきを小さくする。
By making it possible to change the current value of the emitter follower circuit according to the capacitance value of the load circuit, variations in operation delay time are reduced.
第２図はこの発明の一実施例を示す回路図で、
従来例と同等部分は同一符号で示し、その説明を
省略する。この実施例ではエミツタフオロワ回路
のエミツタ抵抗を６α，６βおよび６γの互いに
独立した抵抗で構成し、それぞれの下端から端子
１２α，１２βおよび１２γを引出し、エミツタ
電源端子１０につながつた端子１３との間の接続
の如何によつてどの抵抗を選ぶか、更には並列接
続の組合わせで、各種のエミツタ抵抗値が得られ
る。
FIG. 2 is a circuit diagram showing an embodiment of this invention.
Portions equivalent to those in the conventional example are indicated by the same reference numerals, and their explanation will be omitted. In this embodiment, the emitter resistor of the emitter follower circuit is composed of 6α, 6β, and 6γ independent resistors. Terminals 12α, 12β, and 12γ are drawn out from the lower end of each, and the emitter resistor is connected to the terminal 13 connected to the emitter power supply terminal 10. Various emitter resistance values can be obtained by selecting which resistor depending on the connection, and by combining parallel connections.
従つて、上記実施例は出力端子１１につながる
負荷回路の容量値が大きいかまたは小さいかによ
つて、それぞれエミツタ抵抗値を小さくまたは大
きく設定すればよい。 Therefore, in the above embodiment, the emitter resistance value may be set to be small or large depending on whether the capacitance value of the load circuit connected to the output terminal 11 is large or small.
なお、上記説明では出力回路にエミツタフオロ
ワ回路を有するCML回路について述べたが、
CML回路に限定される理由は全くなく、出力回
路にエミツタフオロワ回路を有する論理回路に広
くこの発明は適用できる。更に、エミツタ抵抗は
３分割した例を示したが、この分割数は３分割に
限るものでないことは自明である。 In addition, in the above explanation, we talked about a CML circuit that has an emitter follower circuit in its output circuit.
There is no reason to limit the invention to CML circuits, and the present invention can be widely applied to logic circuits having emitter follower circuits in their output circuits. Further, although an example has been shown in which the emitter resistor is divided into three parts, it is obvious that this number of divisions is not limited to three parts.
以上説明したように、この発明になるゲートア
レイ形マスタスライス集積回路ではその出力段の
エミツタフオロワ回路のエミツタ抵抗を並列的に
複数個に分割しておき、配線の如何によつてエミ
ツタ抵抗値を負荷回路の容量値に応じて設定でき
るようにしたので、回路の動作遅延時間のばらつ
きを小さくすることができ、論理設計が容易にな
る。
As explained above, in the gate array type master slice integrated circuit according to the present invention, the emitter resistance of the emitter follower circuit in the output stage is divided into a plurality of parts in parallel, and the emitter resistance value is changed depending on the wiring. Since the setting can be made according to the capacitance value of the circuit, variations in the operation delay time of the circuit can be reduced, and logic design becomes easier.
第１図は従来の回路例を示す回路図、第２図は
この発明の一実施例を示す回路図である。
図において、５はエミツタフオロワ用トランジ
スタ、６α，６β，６γはエミツタ抵抗を構成す
る部分抵抗、１２α，１２β，１２γは端子、１
３はエミツタ電圧供給線端子である。なお、図中
同一符号は同一または相当部分を示す。
FIG. 1 is a circuit diagram showing an example of a conventional circuit, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the figure, 5 is an emitter follower transistor, 6α, 6β, and 6γ are partial resistors constituting the emitter resistor, 12α, 12β, and 12γ are terminals, and 1
3 is an emitter voltage supply line terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
アレイ形マスタスライス集積回路において、上記
エミツタフオロワ部のエミツタ抵抗を並列接続さ
れた複数個の部分抵抗で構成し、各部分抵抗に接
続された端子と、エミツタ基準電位を受ける端子
との間の配線パターンを変えることにより上記エ
ミツタフオロワ部の電流を変え得るようにしたこ
とを特徴とするゲートアレイ形マスタスライス集
積回路。1. In a gate array type master slice integrated circuit having an emitter follower section in the output stage, the emitter resistor of the emitter follower section is composed of a plurality of partial resistors connected in parallel, and the terminal connected to each partial resistor and the emitter reference potential A gate array type master slice integrated circuit characterized in that the current in the emitter follower section can be changed by changing the wiring pattern between the emitter follower section and the terminal receiving the current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32178189A JPH02216865A (en) | 1989-12-11 | 1989-12-11 | Gate array type master slice integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32178189A JPH02216865A (en) | 1989-12-11 | 1989-12-11 | Gate array type master slice integrated circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55131312A Division JPS5756945A (en) | 1980-09-19 | 1980-09-19 | Logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02216865A JPH02216865A (en) | 1990-08-29 |
| JPH0359583B2 true JPH0359583B2 (en) | 1991-09-11 |
Family
ID=18136354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32178189A Granted JPH02216865A (en) | 1989-12-11 | 1989-12-11 | Gate array type master slice integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02216865A (en) |
-
1989
- 1989-12-11 JP JP32178189A patent/JPH02216865A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02216865A (en) | 1990-08-29 |
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