JPH0361225B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving Problems Effects of the Invention [Summary] Plural arithmetic processing units , or in a data processing device having a plurality of arithmetic processing units including one or more memory access processing units, a transmission standby system in which a copy of the instruction selected by the instruction input unit is stored near the command transmission control unit. By providing a register QX and controlling the instruction to select and store the instruction that determines the transmission condition in the cycle following the processing cycle of each instruction, transmission control can be performed only by the contents of the transmission standby register QX. This is what I did.

[Industrial application field]

The present invention relates to an instruction control method that allows a later instruction to be executed before an earlier instruction in a data processing device, such as a vector data processing device.

With recent remarkable advances in semiconductor technology, large functional blocks of data processing devices have come to be highly integrated within a single chip or printed board.

In addition, there is a trend to shorten machine cycles in order to increase the speed of data processing devices, and logic delays between chips or printed circuit boards have begun to affect the processing capacity of the data processing devices. Ta.

On the other hand, in a vector data processing device equipped with multiple arithmetic pipelines or an arithmetic pipeline including one or more memory access pipelines, a single vector instruction is used to process a large amount of data. , if there is no factor that protects the order of a plurality of vector instructions, the processing capacity of the entire vector data processing device can be greatly improved by executing subsequent instructions in advance.

In such a vector data processing device, the instruction control section is broadly divided into an instruction input section,
It consists of an instruction sending section, which selects the instruction in the waiting registers _Q1 and _Q2 of the instruction inputting section, sends it to the instruction sending section, compares it with the preceding instruction, determines the sending condition, and then selects the instruction in the waiting registers Q1 and Q2 of the instruction sending section. If there are no factors preventing the transmission, take the vector command into the command transmission section,
It performs command control such as activating related arithmetic units. (Refer to Japanese Unexamined Patent Publication No. 57-161938 mentioned below.) In this case, if the command input section and the command transmission section are housed in separate chips or printed boards, the command input section can transmit the command. Due to the logic delay associated with the transfer of data to the instruction input section and the number of logic stages of the selection circuit for selecting either of the above-mentioned waiting registers Q ₁ or Q ₂ in the instruction input section, it is difficult to control the transmission of the instruction. It takes time,
There was a problem in that the commands from the command input section were delayed.

For this reason, the command control timing between the instruction input section and the instruction transmission section is the same, and the existence of inter-block transfer between the instruction input section and the instruction transmission section is made invisible. As a result, there has been a demand for an instruction control system that improves the processing performance of vector data processing devices.

[Conventional technology]

In general, a second operand A (a ₀ , a ₁ , ...a _o-1 ) has multiple elements, and a third operand B (b ₀ , b ₁ , ...b _o-1 ) has multiple elements.
Then, the operation is performed on the corresponding elements, and the first operand of the operation result C (c ₁ , C ₁ , ...c _o-1 )
(Here, if we perform the operation C=A+B, c _i
A data processing device that obtains the _{following equation} is called a vector data processing device.

On the other hand, a conventional general-purpose processing device in which the number of elements is limited to one (n=1) is called a slacker processing device.

FIG. 3 is a diagram showing an outline of the vector data processing device, and shows the flow of data with solid line arrows.
Dotted arrows indicate the flow of control signals.

First, the store control unit 4 stores the vector register 6.
The load processing unit 5 is for storing data from the main memory device MS1 in the main memory device MS1.
Read data from vector register 6
It is for storing in.

The vector register 6 has a plurality of vector registers that hold vector data consisting of a plurality of elements.

The above store processing section 4, load processing section 5, multiplier
MP7 and adder AD8 have a pipeline structure.

The instruction control unit 9 includes a vector register 6, a store processing unit 4, a load processing unit 5, a multiplier MP7,
Controls adder AD8 etc.

The above store processing section 4, load processing section 5, multiplier
MP7 and adder AD8 are collectively referred to as an arithmetic processing section.

Further, a vector instruction has an instruction code, a first operand specification section, a second operand specification section, and a third operand specification section. For example, a vector multiplication instruction is expressed as VM 1, 2, 3. This multiplies the contents of vector register 2 by the contents of vector register 3,
The multiplication result is stored in vector register 1.

The vector addition instruction is represented by VA 4,5,1. This adds the contents of vector register 5 and the contents of vector register 1, and stores the addition result in vector register 4.

Generally, when processing vector instructions, multiplier MP7, adder AD8, etc. are configured in a pipeline structure, and subsequent elements are input into the arithmetic pipeline before the arithmetic processing of the preceding element is completed. I try to do that.

Figure 4 is a diagram showing the processing status of the vector addition instruction in the adder AD. PRE SHUFT) Addition (ADD) Shift for normalization after addition (POST
SHIFT) Data writing (WRITE) This is a six-stage pipeline. Such instruction processing is represented by a parallelogram as shown in FIG.

Now VM 1, 2, 3 VA 4,5,1 VA 7, 8, 9 Suppose we have a vector instruction sequence called

In the normal processing at this time, processing is performed as shown in FIG. 5, which shows the normal processing of the vector instruction sequence. However, it is assumed that the vector multiplication instruction is an 11-stage pipeline and has 8 elements. In this figure, "VA 4, 5, 1" starts from time = 11 because "VA 4, 5, 1" starts from time = 11.
This is because "VM 5,1" uses the result data of "VM 1,2,3", and at least the first
This is because the addition cannot be started until the multiplication of the elements is completed.

"VA 7, 8, 9" is different from the preceding vector instruction because there is no vector register interference.
The command processing time can be shortened by executing the command before "VA 4, 5, 1".

FIG. 6 is a diagram showing instruction processing when a subsequent vector instruction is executed before a preceding vector instruction, and clearly shows how the instruction processing time is shortened.

Specifically, in the example shown in FIG. 6, it can be seen that the instruction processing time is nine cycles shorter than in the normal processing form shown in FIG. (For example, from 37 cycles to 28 cycles) In this way, if you control to change the execution order of vector instructions specified by the program,
The processing power of vector data processing devices will be significantly improved.

Therefore, an improved command control system for a vector data processing device is disclosed in Japanese Patent Laid-Open No. 161938/1983.

FIG. 7 is a block diagram illustrating an embodiment of the improved instruction control section, and FIG. 8 is a time chart illustrating the operation when an instruction is overtaken.

First, instruction information retrieved from main memory device MS1 is set in fetch register F10. The Q ₁ and Q ₂ input control circuit 11 transfers the instruction information of the fetch register F10 to the waiting register Q ₁ on the condition that the register interference check circuits 13-1 and 13-2 indicate that there is no register interference. , 12-1, or Q ₂ , 12-2.

The selector SEL14 selects the above-mentioned waiting registers _Q1 , 12- according to a control signal from a selection control circuit 19 that inverts the value of the control signal every cycle.
1, or Q ₂ , 12-2 alternately.

Next, the instruction transmission control circuit 15 causes both the register interference check circuits 18-1 and 18-2 to
Under the condition that there is no register interference, when the output of selector SEL14 is a vector addition instruction, this instruction information is stored in addition register AR1.
7, when the output of the selector SEL14 is a vector multiplication instruction, this instruction information is stored in the multiplication register.
The data is transferred to the MR 16, and at the same time, arithmetic processing unit activation information is sent out.

FIG. 8 is a time chart showing the operation when a vector instruction is overtaken in the instruction control unit 9.

In this figure, the instruction information “VM 1, 2, 3” is stored in the fetch register F at time T=0.
10, is moved to the waiting register Q ₁ , 12-1 at time T=1, and is moved to the multiplication register MR16 at T=2, thereby starting multiplication. At this time, the WRITE pre-start flag is set to "on" at the same time as the multiplication starts, and is reset to "on" when writing of the operation result to the vector register 6 starts.

The command information “VA 4, 5, 1” is at time T
At time T=1, it is set in the fetch register F10, and at time T=2, it is set in the waiting register _Q2 , 12-2.

In this case, the command transmission condition is checked in the command transmission control circuit 15, and the multiplication register MR1
The first of "VM 1, 2, 3" held in
Operand register and above waiting register
The above “VA 4,” held in Q ₂ , 12-2.
5, 1" and the third operand register is causing register interference, the waiting register
“VA 4, 5,” held in Q ₂ , 12-2
The transmission of the ``1'' command functions as if it were to wait.

At time T=2, when the instruction "VA 7, 8, 9" is set in the fetch register F10, the instruction "VA 4, 5, 1" held in the waiting registers Q ₂ , 12-2 and , fetish register F
The above "VA 7, 8, 9" held in 10
Since there is no register interference with the instruction, at time T=3, the "VA 7, 8, 9" instruction is moved to the waiting register Q ₁ , 12-1, and there is no factor that prevents the instruction from being sent. Therefore, at time T=4, the "VA 7, 8, 9" instruction is transferred to the addition register AR17 and is also transferred to the adder AD8.
It operates to start addition processing for .

In this way, the subsequent instruction overtakes the preceding instruction.

Although other overtaking systems are disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 57-161938, the following problems will be omitted here as they will only be described in terms of conditions.

[Problem that the invention seeks to solve]

Therefore, in the conventional command control method, control of issuing commands requires quite complex logic.
A problem arises in that the number of logic stages in the command generation control circuit 15 increases.

Also, since the amount of materials that make up the circuit increases, the seventh
It becomes necessary to configure the command input section and the command transmission section shown in the figure in separate blocks (for example, separate chips or printed boards) separated from each other.

If this is done, the delay time of the signal will be increased, and it will be difficult to control the command transmission within one machine cycle from the input of the command to the transmission of the command, which will further increase the number of machine cycles. There will be times when you are forced to do so.

In particular, before determining the transmission condition, the command information in the waiting registers Q ₁ , Q ₂ , 12-1, 12-2 is transferred between blocks through the selector SEL 14 until it is sent to the command transmission control circuit 15. The delay time becomes a nuisance.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide a method for eliminating the logical delay bottleneck from the waiting registers Q ₁ and Q ₂ of the instruction input section to the instruction generation control circuit.

[Means for solving problems]

FIG. 1 is a diagram showing the concept of the present invention, and FIG. 2 is a diagram showing the concept of one embodiment of the present invention in a block diagram.

In the present invention, the transmission standby register QX20
is provided near, for example, just before the command generation control circuit 15, and a route is provided to bypass the outputs of the Q ₁ and Q ₂ input control circuits 11 to the selector SEL 14, and the QX input selection control circuit 21
The selector SEL14 performs the following control for each condition.

(a) The selection control circuit 19 is the waiting register Q ₁
(hereinafter referred to as the _Q1 register) 12-1, when the _Q1 , _Q2 input control circuit 11 inputs an instruction to the _Q1 register 12-1 at a timing one cycle before selecting the fetch register (hereinafter referred to as the Q1 register) 12-1. _.

However, when it is not set in the _Q1 register 12-1, it is not set in the QX register 20 either.

(b) One cycle before the selection control circuit 19 selects the Q ₁ register 12-1, Q ₁ ,
When the Q ₂ input control circuit 11 does not input an instruction to the Q ₁ register 12-1, the Q ₁ register 1
2-1 is set in the QX register 20.

(c) The selection control circuit 19 is the waiting register Q ₂
(hereinafter referred to as register) 12-2, when the Q ₁ and Q ₂ input control circuit 11 inputs an instruction to the Q ₂ register 12-2, it inputs the instruction information of the F register 10. The instruction is selected and controlled so that it is set in the QX register 20 at the same time as the instruction is set in the _Q2 register 12-2.

However, when it is not set in the _Q2 register 12-2, it is not set in the QX register 20 either.

(d) One cycle before the selection control circuit 19 selects the Q ₂ register 12-2, Q ₁ ,
When the Q ₂ input control circuit 11 does not input an instruction to the Q ₂ register 12-2, the Q ₂ register 1
2-2 is set in the QX register 20.

The above operation is conceptually shown in Fig. 1, in which F, Q ₂ , Q ₁ , QX, MR, AR on the horizontal axis indicate the above-mentioned registers, and T1 to T1 on the vertical axis. Each time is shown, and ~ shows command information. And (a) ~ in the remarks column corresponds to the above control conditions.

As is clear from this figure, when the present invention is implemented, the contents of the QX register 20 when viewed from the instruction transmitter are the _Q1 register 12-1 selected by the selection control circuit 19, or the Q ₂ register 12
-2, and also has the characteristic that there is no delay in terms of timing.

If controlled as described above, in any case, the QX register 20 will contain either the _Q1 register 12-1 or the _Q2 register 12 for each machine cycle.
It can be seen that copies of the -2 instructions are set alternately.

In other words, the output from the QX register 20 is logically the same as the output from the selector SEL14, and also in terms of timing.

Therefore, the problem of command transmission can be speeded up by the fact that the delay time of the selector SEL 14 and inter-block transfer is not visible.

[Effect]

That is, according to the present invention, a plurality of arithmetic processing units,
Alternatively, in a data processing device having a plurality of arithmetic processing units including one or more memory access processing units, a transmission standby register that stores a copy of the instruction selected by the instruction input unit near the instruction transmission control unit. By providing QX and controlling the instruction to select and store the instruction that determines the transmission condition in the next cycle of each instruction processing cycle, transmission control is performed only by the contents of the transmission standby register QX. Therefore, there is no need to be aware of inter-block transfer from the command input section to the command transmission section, and there is an effect that the speed of command transmission control can be increased.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 2 is a diagram schematically showing an embodiment of the present invention in the form of a block diagram, in which the input control circuit 11
A bypass path for command information from to selector SEL14, QX input selection control circuit 21, and transmission standby register QX20 are functional blocks necessary to implement the present invention. Note that the same reference numerals indicate the same objects throughout the figures. Further, in this embodiment, for convenience of explanation, a register interference check circuit that is not directly related to the present invention is omitted.

Even if the present invention is implemented, the operation of controlling the transmission of commands will not change from the conventional one, so a description thereof will be omitted, and this is the main point of the present invention. The method of setting instruction information for the QX register 20 will be mainly explained.

First, the selection control circuit 19 operates the _Q1 register 12-1 and the _Q2 register 12-1 in the same way as in the conventional case.
A selection signal S for alternately selecting Q 1 and Q 2 is generated, and the selection signal S and Q ₁ , Q ₂ from the transmission control circuit 11 are
The above Q ₁ register 12-1 or Q ₂ register 12
-2, the QX input selection control circuit 21 performs the following control on the selector SEL10 based on the signal T indicating to which of the input terminals the command information from the F register 10 is input. That is, (a) _{Q 1 ,}
When the _Q2 input control circuit 11 inputs an instruction to the _Q1 register 12-1, it selects the instruction information in the F register 10, and at the same time that the instruction is set in the _Q1 register 12-1, it inputs the instruction through the bypass route. It is also controlled to be set in the QX register 20.

However, when it is not set in the _Q1 register 12-1, it is not set in the QX register 20 either.

(b) One cycle before the selection control circuit 19 selects the Q ₁ register 12-1, Q ₁ ,
When the Q ₂ input control circuit 11 does not input an instruction to the Q ₁ register 12-1, the Q ₁ register 1
Only 2-1 is set in the QX register 20.

(c) One cycle before the selection control circuit 19 selects the Q ₂ register 12-2, Q ₁ ,
When the _Q2 input control circuit 11 inputs an instruction to the _Q2 register 12-2, it selects the instruction information in the F register 10, and at the same time that the instruction is set in the _Q2 register 12-2, it inputs the instruction through the bypass route. It is also controlled to be set in the QX register 20.

However, when it is not set in the _Q2 register 12-2, it is not set in the QX register 20 either.

(d) One cycle before the selection control circuit 19 selects the Q ₂ register 12-2, Q ₁ ,
When the Q ₂ input control circuit 11 does not input an instruction to the Q ₂ register 12-2, the Q ₂ register 1
Set only 2-2 in the QX register 20.

Here, 1 selects _Q1 register 12-1.
Timing before cycle or Q ₂ register 1
It is possible to know that the timing is one cycle before selecting 2-2 by negating the selection signal S.

As described above, the present invention is characterized in that the output from the QX register is logically the same as the output of the selector SEL14, and the timing is also the same.

〔Effect of the invention〕

As described above in detail, the instruction control method of the present invention is applicable to a data processing device having a plurality of arithmetic processing units or a plurality of arithmetic processing units including one or more memory access processing units. A transmission standby register QX is provided near the instruction transmission control section to store a copy of the instruction selected by the instruction input section.
By controlling the instruction to select and store the instruction that determines the transmission condition in the cycle following the processing cycle of each instruction, transmission control is performed only by the contents of the transmission standby register QX. There is no need to be aware of the inter-block transfer from the command input section to the command transmission section, which has the effect of increasing the speed of command transmission control.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the concept of the present invention, Fig. 2 is a block diagram showing an outline of an embodiment of the invention, Fig. 3 is a diagram showing an outline of a vector data processing device, and Fig. 4 is a diagram showing an outline of a vector data processing device. The figure shows the processing status of a vector addition instruction in the adder AD, Figure 5 shows the normal processing of a vector instruction sequence, and Figure 6 shows the execution of a later vector instruction before the earlier vector instruction. FIG. 7 is a block diagram showing an example of an improved instruction control unit, and FIG. 8 is a time chart showing the operation when an instruction is overtaken. Figure. In the drawing, 1 is a main storage device MS, 3 is an arithmetic processing unit, 4 is a store processing unit, 5 is a load processing unit,
6 is a vector register, 7 is a multiplier MP, 8 is an adder AD, 9 is an instruction control unit, 10 is a fetch register F, 11 is a _Q1 , _Q2 input control circuit, 12-
1, 12-2 are waiting registers Q ₁ , Q ₂ , 1
3-1, 13-2, 18-1, 18-2 are register interference check circuits, 14 is a selector SEL, 15
is an instruction transmission control circuit, 16 is a multiplication register MR,
17 is addition register AR, VM 1, 2, 3, VA
4, 5, 1, VA 7, 8, 9 are vector instructions,
are shown respectively.

Claims (1)

[Claims] 1. In a data processing device having a plurality of arithmetic processing units or a plurality of arithmetic processing units including one or more memory access processing units, a plurality of arithmetic processing units that hold instruction information before execution of an arithmetic operation are provided. waiting registers Q ₁ , Q ₂ , 12-1, 12-2,
The plurality of waiting registers Q ₁ , Q ₂ , 12-
1, 12-2 and the new instruction information, the above-mentioned waiting registers Q ₁ , Q ₂ , 12-
Q ₁ and Q ₂ input control circuit 1 to input to 1 and 12-2
1, and the corresponding waiting registers Q ₁ , Q ₂ , 12-1,
1 from the instruction information group held in 12-2
an instruction input section consisting of a selection circuit SEL14 for selecting instruction information and a selection control circuit 19; a plurality of registers MR holding instruction information during execution of an operation;
AR, 16, 17, instruction information during execution of the operation, and the above-mentioned waiting registers Q ₁ , Q ₂ , 12-1,
12-2, and the comparison means 15 compares the waiting registers Q ₁ , Q 2 , Q ₂ ,
12-1 and 12-2, one of the instructions before execution of the operation is selected, and the instruction for which it has been confirmed that there are no factors preventing the start of execution of the operation is added to the instruction information during execution of the operation. an instruction issuing section that moves the instruction to an "empty" register among the plurality of registers MR, AR, 16, and 17 holding the instruction, and activates the arithmetic processing section corresponding to the instruction, and selects the instruction input section. The above-mentioned waiting registers Q ₁ , Q ₂ , 12-1, 12-2 are connected to the circuit SEL14.
In addition to providing means for bypassing and inputting the output of the command information F10 to be input to the selection circuit SEL1,
By inputting the instruction information selected by 4, one of the plurality of waiting registers Q ₁ , Q ₂ , 12-1, 12-2 is selected for each machine cycle. A transmission standby register QX, 20 is provided in which the same instruction information is set, and the instruction in the transmission standby register QX, 20 is compared with information on the instruction currently being executed to determine if there is a factor preventing the start of the operation. When it is confirmed that there is no such instruction, the instruction is moved to an "empty" register among the multiple registers MR, AR, 16, and 17 that hold information about the instruction being executed, and the above operation corresponding to the instruction is executed. An instruction control method characterized by activating a processing section.