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JPH0362293B2 - - Google Patents
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JPH0362293B2 - - Google Patents

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Publication number
JPH0362293B2
JPH0362293B2 JP19231385A JP19231385A JPH0362293B2 JP H0362293 B2 JPH0362293 B2 JP H0362293B2 JP 19231385 A JP19231385 A JP 19231385A JP 19231385 A JP19231385 A JP 19231385A JP H0362293 B2 JPH0362293 B2 JP H0362293B2
Authority
JP
Japan
Prior art keywords
capacitor
motherboard
electrode
grooves
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP19231385A
Other languages
Japanese (ja)
Other versions
JPS6252917A (en
Inventor
Isao Kaizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP19231385A priority Critical patent/JPS6252917A/en
Publication of JPS6252917A publication Critical patent/JPS6252917A/en
Publication of JPH0362293B2 publication Critical patent/JPH0362293B2/ja
Granted legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は2つの主表面に対向する状態で容量用
電極が形成された単板コンデンサの製造方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a single-plate capacitor in which capacitance electrodes are formed on two main surfaces facing each other.

従来の技術 上記単板コンデンサは、第3図に示す工程によ
り製造される。即ち、図イに示すようにシート成
形により名刺大のマザーボード1を作り、その対
向する2つの主表面2a,2bに図ロに示すよう
にチツプブレイクするためブレイク用溝3a…,
3b…を格子状に形成する。次いで、これを1200
〜1400℃の温度で焼成した後、前記2つの主表面
2a,2bに銀−パラジウム合金等の容量用電極
4…を図ハに示すように溝3b…を横切つて塗布
する。続いて、マザーボード1を溝3a…に沿つ
てブレイクし(以下、このブレイクを横ブレイク
という。)、図ニに示すように容量用電極4,4の
端部側と接触する状態で接続用電極5…を塗布す
る。接続用電極5も容量用電極4,4と同じ銀−
パラジウム合金等が用いられる。このように電極
4,5を塗布した状態で約800℃の温度で電極の
焼付けを行い、以後、接続用電極の表面に外装塗
料をはじくパラフイン等をコーテイングし、チツ
プブレイクし、接続用電極を除き全周面を外装塗
料(図示せず)をコーテイングするという工程を
経て図ホに示す単板コンデンサを得る。
Prior Art The above-mentioned single-plate capacitor is manufactured by the process shown in FIG. That is, as shown in Figure A, a business card-sized motherboard 1 is made by sheet molding, and its two opposing main surfaces 2a and 2b are provided with break grooves 3a for chip breaking as shown in Figure B.
3b... are formed in a grid shape. Then set this to 1200
After firing at a temperature of ~1400 DEG C., a capacitor electrode 4 made of silver-palladium alloy or the like is applied to the two main surfaces 2a, 2b across the grooves 3b as shown in FIG. Next, the motherboard 1 is broken along the grooves 3a (hereinafter, this break is referred to as a lateral break), and the connection electrodes are placed in contact with the end sides of the capacitor electrodes 4, 4, as shown in FIG. 5. Apply... The connection electrode 5 is also made of silver, the same as the capacitance electrodes 4, 4.
A palladium alloy or the like is used. With the electrodes 4 and 5 applied in this way, the electrodes are baked at a temperature of approximately 800°C.Then, the surface of the connection electrode is coated with paraffin or the like that repels the exterior paint, chip-broken, and the connection electrode is sealed. The single-plate capacitor shown in Figure E is obtained through a step of coating the entire circumferential surface with exterior paint (not shown).

発明が解決しようとする問題点 ところで、上記の製造方法によれば、マザーボ
ードをチツプブレイクする前に容量用電極を塗る
ので、ブレイク用溝3b…にも容量用電極4,4
が入り込み、そのまま溝壁面に焼付けられること
となる(第4図イ参照)。そのため、チツプブレ
イクして得た単板コンデンサにおいて第4図ロに
示すように前記溝壁面に焼付いた容量用電極の部
分が上下で対向することとなり、この間の距離l
によつてコンデンサの耐圧が著しく低下するとい
つた問題がある。この場合、ブレイク用溝内に電
極が入り込まないような塗布方法があれば上記問
題点を解消できるが、そのような塗布方法はな
く、そのためコンデンサの耐圧を低下させないた
めには、誘電体の厚みを厚くしなければならず、
小型、高容量化には適さないという欠点があつ
た。
Problems to be Solved by the Invention By the way, according to the above manufacturing method, since the capacitor electrodes are applied before chip breaking the motherboard, the capacitor electrodes 4, 4 are also applied to the break grooves 3b...
will enter and be burned into the groove wall (see Figure 4A). Therefore, in the single-plate capacitor obtained by chip breaking, the capacitance electrode portions burned into the groove wall surface face each other at the top and bottom, as shown in Figure 4B, and the distance between them is l.
There is a problem in that the withstand voltage of the capacitor is significantly lowered due to In this case, the above problem could be solved if there was a coating method that would prevent the electrode from entering the break groove, but there is no such coating method, and therefore, in order to prevent the capacitor's withstand voltage from decreasing, the thickness of the dielectric must be adjusted. must be made thicker,
The drawback was that it was not suitable for small size and high capacity.

本発明はこのような点にあつて、巧みな方法に
よりブレイク用溝内に電極が入り込まないように
して課題解決を図らんとするものである。
The present invention attempts to solve this problem by using a clever method to prevent the electrode from entering the breaking groove.

問題点を解決するための手段 本発明は、対向する2つの主表面にチツプブレ
イクするためのブレイク用溝を格子状に形成した
マザーボードを焼成した後、前記両主表面に容量
用電極を塗布焼付けし、その後チツプブレイクす
る単板コンデンサの製造方法において、前記マザ
ーボードの2つの主表面上に刻設されたブレイク
用の溝に、容量用電極を塗布する前に該容量用電
極の焼付後には除去され得る充填材を充填するこ
とを特徴としている。
Means for Solving the Problems The present invention provides a motherboard in which breaking grooves for chip breaking are formed in a lattice shape on two opposing main surfaces, and then capacitance electrodes are applied and baked on both main surfaces. In the method for manufacturing a single-plate capacitor that is then chip-broken, the capacitance electrodes are removed after baking, before the capacitance electrodes are applied to the break grooves carved on the two main surfaces of the motherboard. It is characterized by being filled with a filler that can be used.

作 用 電極の焼付後には除去され得る充填材を容量用
電極を塗布する前にブレイク用溝に充填しておけ
ば、容量用電極の焼付後にはこの充填材の存在に
よつてブレイク用溝の壁面に容量用電極が焼付く
のを効果的に防止できる。このため、容量用電極
の対向間隔チツプユニツトの2つの主表面の間隔
に等しくなり、小型、高耐圧、高容量のコンデン
サを得ることができる。
Function: If the break groove is filled with a filler that can be removed after the electrode is baked before applying the capacitor electrode, the presence of this filler will prevent the break groove from forming after the capacitor electrode is baked. It is possible to effectively prevent the capacitor electrode from sticking to the wall surface. Therefore, the facing distance between the capacitor electrodes becomes equal to the distance between the two main surfaces of the chip unit, making it possible to obtain a compact, high-voltage, high-capacity capacitor.

実施例 第1図は本発明の単板コンデンサの製造方法を
説明する工程図であり、この図に基づいて製造手
順を説明する。先ず、シート成形(工程イ)によ
りマザーボードを得、それの2つの主表面にブレ
イク用溝を形成する(工程ロ)。このときのマザ
ーボードを第2図イに示すが、その構造は第3図
ロに示したものと全く同じである。溝3a,3b
の深さはマザーボード1の厚みが1mmの場合0.3
mm程度である。但し、横溝3aより縦溝3bの方
が多少浅くしてある。これは横ブレイクの際に、
縦溝3bに沿つて割れるのを防ぐためである。
尚、マザーボード1の原料としてはチタン酸バリ
ウム等の誘電体セラミクスが用いられる。
Embodiment FIG. 1 is a process diagram illustrating a method for manufacturing a single-plate capacitor according to the present invention, and the manufacturing procedure will be explained based on this diagram. First, a motherboard is obtained by sheet molding (step A), and break grooves are formed on its two main surfaces (step B). The motherboard at this time is shown in FIG. 2A, and its structure is exactly the same as that shown in FIG. 3B. Grooves 3a, 3b
The depth of is 0.3 if the thickness of motherboard 1 is 1mm.
It is about mm. However, the vertical grooves 3b are somewhat shallower than the horizontal grooves 3a. This happens when there is a horizontal break.
This is to prevent cracking along the vertical grooves 3b.
Note that dielectric ceramics such as barium titanate are used as the raw material for the motherboard 1.

次いで、このマザーボードからなる誘電体を焼
成する。
Next, the dielectric made of this motherboard is fired.

続いて、前記マザーボード1の2つの主表面2
a,2bに形成されたブレイク用溝3a,3bに
充填材を充填する(工程ハ)。充填材は電極焼付
温度(約800℃)で焼とぶ材料を選ぶ。このよう
な材料として例えばカーボンがあげられる。充填
材をブレイク用溝3a,3b…に充填するには例
えばハケ等でマザーボード主表面にカーボンを塗
布する。この塗布によつてマザーボード主表面2
a,2b上にもカーボン付着することがあるが、
その厚みが非常に薄く、しかも電極焼付け時に焼
とぶので電極の焼付けには支障を来さない。カー
ボンがブレイク用溝3b…に充填された状態を第
2図ロに示す。6がカーボンである。カーボン6
の充填を完了すればマザーボード主表面に容量用
電極を塗る(工程ニ)。容量用電極を塗つた状態
を第2図ハに示す。容量用電極4としては従来と
同様、銀−パラジウム合金等が使用される。容量
用電極4の塗布を終えれば、横溝3aに沿つてブ
レイクし(工程ホ)、接続用電極を塗布し(工程
ヘ)、電極の焼付けを行う(工程ト)。この焼付工
程において、溝3b…にはカーボン6が充填して
あるので、容量用電極4が溝3b…内に入り込む
ことはない。一方、カーボン6は溝3b…内にい
つまでも残つていることはなく焼付完了時までに
は焼とび、溝3b…から消失する。従つて、焼付
完了した時点では第2図ニに示す如く、容量用電
極4が主表面2a,2b上にのみ焼付いた状態と
なる。
Next, the two main surfaces 2 of the motherboard 1
The break grooves 3a and 3b formed in the grooves a and 2b are filled with a filler (step c). For the filler, choose a material that burns out at the electrode baking temperature (approximately 800℃). An example of such a material is carbon. To fill the break grooves 3a, 3b, . . . with filler, carbon is applied to the main surface of the motherboard using a brush or the like. By this application, the motherboard main surface 2
Carbon may also adhere on a and 2b, but
Its thickness is very thin, and it burns off during electrode baking, so it does not interfere with electrode baking. FIG. 2B shows a state in which the break grooves 3b are filled with carbon. 6 is carbon. carbon 6
Once filling is completed, capacitor electrodes are applied to the main surface of the motherboard (Step 2). The state in which the capacitor electrode is applied is shown in Figure 2C. As the capacitor electrode 4, a silver-palladium alloy or the like is used as in the conventional case. After coating the capacitor electrode 4, a break is made along the horizontal groove 3a (step E), a connection electrode is coated (step H), and the electrode is baked (step T). In this baking step, since the grooves 3b are filled with carbon 6, the capacitor electrode 4 does not enter into the grooves 3b. On the other hand, the carbon 6 does not remain in the grooves 3b forever, but burns off and disappears from the grooves 3b by the time baking is completed. Therefore, when the baking is completed, the capacitor electrode 4 is baked only onto the main surfaces 2a and 2b, as shown in FIG. 2D.

以後は、従来と同様に接続用電極表面に外装塗
料をはじくパラフインをコーテイングし(工程
チ)、チツプブレイクし(工程リ)、外装塗料付与
させて単板コンデンサを得る(工程ヌ)。かくし
て製造した単板コンデンサは第2図ホに示すよう
に容量用電極4が主表面2a,2b上にのみ付与
され、溝3bの壁面には付与されないので、容量
用電極4,4の対向間隔がl′(>l)と長くなり、
耐圧の低下が起こらない。
Thereafter, as in the past, the surface of the connection electrode is coated with paraffin that repels the exterior paint (process 1), chip-broken (process 3), and exterior paint is applied to obtain a single-plate capacitor (process 2). In the thus manufactured single-plate capacitor, as shown in FIG. becomes long as l′ (>l),
No drop in pressure resistance occurs.

なお、上記実施例では、充填剤としてカーボン
を用い、これを容量用電極の焼付時に焼きとばす
ものを示したが、これに限らず、例えば容量用電
極の焼付温度で焼結し、かつマザーボードとは焼
成反応しない無機物質を充填剤として用い、容量
用電極の焼付後に焼結されていない無機物質を溝
内から取り除くようにしてもよい。これにより無
機物質上に付与されている容量用電極が除去さ
れ、各容量用電極が分離形成される。この例にお
いては、無機物質がマザーボードの表面に付与さ
れると、容量用電極が後に除去されてしまうの
で、溝内にのみ充填させるよう留意されなければ
ならない。
In the above embodiment, carbon is used as a filler and is burnt off when baking the capacitor electrode, but the present invention is not limited to this. Alternatively, an inorganic substance that does not react with firing may be used as a filler, and the unsintered inorganic substance may be removed from the groove after the capacitor electrode is baked. As a result, the capacitor electrode provided on the inorganic material is removed, and each capacitor electrode is formed separately. In this example, when the inorganic material is applied to the surface of the motherboard, care must be taken to only fill the grooves, since the capacitive electrodes will be removed later.

発明の効果 以上説明したように本発明に係る単板コンデン
サの製造方法によれば、電極の焼付後には除去さ
れ得る充填材をブレイク用溝に充填した状態でマ
ザーボード主表面に容量用電極を塗り、その後、
電極の焼付けを行うので、ブレイク用溝の壁面に
容量用電極が付与されるのを効果的に防止でき、
従つて容量用電極の対向間隔が2つの主表面の間
隔に等しく保たれた単板コンデンサを得ることが
でき、小型で高容量なものとなる。
Effects of the Invention As explained above, according to the method for manufacturing a single-plate capacitor according to the present invention, the capacitor electrode is applied to the main surface of the motherboard while the break groove is filled with a filler that can be removed after the electrode is baked. ,after that,
Since the electrode is baked, it is possible to effectively prevent the capacitor electrode from being attached to the wall of the break groove.
Therefore, it is possible to obtain a single-plate capacitor in which the facing distance between the capacitor electrodes is kept equal to the distance between the two main surfaces, resulting in a small size and high capacity capacitor.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の製造方法を説明する工程図、
第2図は第1図の主要工程におけるマザーボード
の加工状態を示す図、第3図は従来の単板コンデ
ンサの製造方法を示す図、第4図は従来の欠点を
説明する図である。 1…マザーボード、2a,2b…主表面、3
b,3b…ブレイク用溝、4…容量用電極、5…
充填材。
FIG. 1 is a process diagram explaining the manufacturing method of the present invention,
FIG. 2 is a diagram showing the machining state of the motherboard in the main steps shown in FIG. 1, FIG. 3 is a diagram showing a conventional method of manufacturing a single-plate capacitor, and FIG. 4 is a diagram illustrating the drawbacks of the conventional method. 1...Motherboard, 2a, 2b...Main surface, 3
b, 3b...Break groove, 4...Capacitor electrode, 5...
Filling material.

Claims (1)

【特許請求の範囲】 1 対向する2つの主表面にチツプブレイクする
ためのブレイク用溝を格子状に形成したマザーボ
ードを焼成した後、前記両主表面に容量用電極を
塗布焼付けし、その後チツプブレイクする単板コ
ンデンサの製造方法において、 前記マザーボードの2つの主表面上に刻設され
たブレイク用の溝に、容量用電極を塗布する前に
該容量用電極の焼付後には除去され得る充填材を
充填することを特徴とする単板コンデンサの製造
方法。
[Scope of Claims] 1. After firing a motherboard in which break grooves for chip breaking are formed in a lattice shape on two opposing main surfaces, capacitance electrodes are applied and baked on both main surfaces, and then chip breaking is performed. In the method for manufacturing a single-plate capacitor, a filler that can be removed after baking of the capacitor electrodes is added to the break grooves carved on the two main surfaces of the motherboard before applying the capacitor electrodes. A method for manufacturing a single-plate capacitor characterized by filling.
JP19231385A 1985-08-30 1985-08-30 Manufacture of single-plate capacitor Granted JPS6252917A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19231385A JPS6252917A (en) 1985-08-30 1985-08-30 Manufacture of single-plate capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19231385A JPS6252917A (en) 1985-08-30 1985-08-30 Manufacture of single-plate capacitor

Publications (2)

Publication Number Publication Date
JPS6252917A JPS6252917A (en) 1987-03-07
JPH0362293B2 true JPH0362293B2 (en) 1991-09-25

Family

ID=16289199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19231385A Granted JPS6252917A (en) 1985-08-30 1985-08-30 Manufacture of single-plate capacitor

Country Status (1)

Country Link
JP (1) JPS6252917A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0748410B2 (en) * 1989-02-07 1995-05-24 ローム株式会社 Method for forming electrode film in electronic component
DE602007011058D1 (en) * 2006-05-29 2011-01-20 Murata Manufacturing Co METHOD FOR PRODUCING A CERAMIC, MULTILAYER SUBSTRATE
DE602007011286D1 (en) * 2006-08-07 2011-01-27 Murata Manufacturing Co METHOD FOR PRODUCING A CERAMIC, MULTILAYER SUBSTRATE
JP4873379B2 (en) * 2008-03-31 2012-02-08 Tdk株式会社 Manufacturing method of multilayer ceramic electronic component
JP2010238989A (en) * 2009-03-31 2010-10-21 Tdk Corp Method for manufacturing laminated ceramic electronic component

Also Published As

Publication number Publication date
JPS6252917A (en) 1987-03-07

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