JPH0363794B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field to which the invention pertains] The present invention provides a method for inputting an analog signal from a detector to obtain a current output corresponding to a process amount, etc.
It relates to wire transmission circuits.

[Prior art]

Conventionally, in process instrumentation control systems and the like, a two-wire transmission method has often been used as a convenient method for transmitting signals obtained by on-site detectors to a group of receiving instruments in a control room. In this system, as shown in Figure 1, a transmitter (transmitter) 1 on site, a receiving instrument 4 in a control room 2, and a power source 3 are connected by a track 5 consisting of two wires. In this method, the DC current (e.g. 4 to 20 mA) flowing through the transmitter indicates the measured value and at the same time serves as the power supply to the transmitter 1.
It has various advantages such as simplifying instrumentation work, reducing construction costs, and improving reliability. Conventionally,
Most of the transmission circuits used in such two-wire transmission systems have a configuration in which output current and process amount input are balanced by a feedback resistor 6, as shown in FIG. However, the two-wire transmission circuit having such a configuration has a problem in that the voltage range that can be used as a power source on the transmitter side is reduced due to the voltage drop that occurs in the feedback resistor 6. Furthermore, since the compatibility with microcomputers and the like is poor, signal processing such as linear compensation becomes less accurate due to analog circuit technology.

[Purpose of the invention]

The present invention was made in order to solve the above problems, and it is possible to achieve high accuracy without feedback from the output to the process amount side, a wide voltage range that can be used as a power source on the oscillator side, and a micro The purpose is to realize a two-wire transmission circuit with excellent connectivity with a computer.

[Summary of the invention]

The two-wire transmission circuit according to the first aspect of the present invention includes an A/D conversion circuit that inputs a detection signal from a detector and generates a code output, and an A/D conversion circuit that inputs a detection signal from a detector and generates a code output, and a It has a constant current circuit that generates a weighted constant current, and a switch means that is driven by the code output of each bit to turn on and off the corresponding constant current, and the sum of the constant currents is the output current. It is characterized in that it is configured to form a variable portion corresponding to a detection signal.

A two-wire transmission circuit according to a second aspect of the present invention includes an A/D conversion circuit that inputs a detection signal from a detector and generates a code output, and an A/D conversion circuit that inputs a detection signal from a detector and generates a code output, and an A/D conversion circuit that inputs a detection signal from a detector and generates a code output. a first constant current circuit that generates a weighted first constant current; a switch means that is driven by the code output of each bit to turn on and off the corresponding first constant current; and the A/D circuit. a D/A conversion circuit that generates an analog output corresponding to the code output from the conversion circuit; and a second current that generates a second current that is proportional to the difference between the output from the D/A conversion circuit and the detection signal. The present invention is characterized in that it has a constant current circuit, and is configured such that the sum of the first constant current and the second constant current forms a variable portion of the output current corresponding to the detection signal.

[Embodiments of the invention]

The present invention will be explained in detail below using the drawings.

FIG. 2 is a principle circuit diagram showing the basic principle of a two-wire transmission circuit according to the present invention. The same parts as in FIG. 1 are given the same symbols and their explanations will be omitted. 7 is a two-wire transmission circuit, and 8 is an A/D conversion circuit that converts the code of the detection signal output from the detector in accordance with the process amount. 9 is a current generating circuit connected to terminals T ₁ and T ₂ and generates a current corresponding to the code output C ₈ of the A/D conversion circuit 8; I ₉₁ to _{I 9N} are the N of the A/D conversion circuit 8; A constant current circuit generates a constant current weighted by the magnitude corresponding to each bit of the bit code output _C8 , and _S91 to _S9N are switches that turn on and off the constant current corresponding to each bit. It is a means. 10 is connected to the terminal T ₁ and supplies a constant current (e.g.
This is a constant current circuit that supplies 4mA, etc.).

The operation of such a circuit configuration will be explained next. When the detection signal is applied to the A/D conversion circuit 8, N
The bit code output _C8 turns on and off the switch means _S91 to _S9N . As a result, the switch turned on
The sum of currents from the constant current source I _9i corresponding to S _9i (i=1 to N) flows into the line 5 . The current I _b determined by the constant current circuit 10 is always connected to the line 5 regardless of the input.
flows, and the output current I is the basic component of ₀ (active zero)
Configure. As a result, the variable portion of the output current I ₀ corresponds to the detection signal input.

FIG. 3 is a circuit diagram showing a specific embodiment of the current generating circuit 9 of FIG. 2. In FIG. 11 is terminal T ₁
12 is a constant voltage element such as a Zener diode connected to this constant current source 11, and 13 is connected to this constant voltage element 12 and terminal _T2. The switch means S ₃₁ is composed of an N-channel FET connected to
A compensation resistor that compensates for the voltage drop due to the on-resistance when S _3N is turned on; 14 is the constant current source 1;
1 and the constant voltage element 12 are connected to its non-inverting input terminal, and the operational amplifiers R ₃₁ to R _3N are connected to the inverting input terminal of this operational amplifier 14 and connected to its output terminal or inverting input terminal. The resistors S ₃₁ to S _3N are connected at one end to the other ends of the resistors R ₃₁ to _{R 3N} , and the other end is connected to the terminal T ₂ , which is a switch means consisting of an N-channel FET. . . The power supply terminals of the operational amplifier 14 are connected to T ₁ and T ₂ , and the current flowing through the power supply terminal on the terminal T ₂ side is a constant current, and the sum of this and the current flowing through the current source 11 is the output current. This is the basic amount. resistance
The resistance values of R ₃₁ to _{R 3N} are R ₃₁ :R ₃₂ :... corresponding to the weighting of each bit from the A/D conversion circuit 8.
Weights are given as follows: R _3N = 1:2:...2 ^N-1 . Further, the on-resistances of the switch means S ₃₁ to S _3N are similarly weighted.

In the current generating circuit 9 having such a configuration, the constant voltage element 1 is connected to the non-inverting input terminal of the operational amplifier 14.
A constant voltage V _C1 generated by a constant current flowing through the compensating resistor 13 and the compensating resistor 13 is applied. Since the inverting input terminal of the operational amplifier 14 becomes equal to the constant voltage V _C1 due to feedback with a gain of 1, the switching means S ₃₁ -
When S _3N is turned on, constant currents I ₃₁ to _{I 3N} corresponding to the weighting of each bit flow into the T ₂ terminal. This current is supplied to the power input terminal of the operational amplifier 14 via the T ₁ terminal, and flows from the output terminal of the operational amplifier 14 to each of the resistors R ₃₁ to R _3N . This results from terminal T ₁
The sum of the constant currents I ₃₁ to _{I 3N} flowing in response to the code input described above flows through T ₂ .

FIG. 4 is a circuit configuration diagram showing a concrete other embodiment of the current generating circuit 9 of FIG. 2, in which the influence of the on-resistance of the switching means and its variation is eliminated. 15 is a constant current source connected to terminal T ₁ and supplies current to the conversion circuit and Zener diode 16; 17 is a power input terminal connected to terminal T ₁ ,
T ₂ and the constant current source 15 and constant voltage element 1
The operational amplifiers S41a to S4Na each have one end connected to the output terminal of the operational amplifier 17, and each of the operational amplifiers _S41a to _S4Na , to which a constant voltage V _C2 at the connection point with 6 is applied to its non-inverting input terminal, has an A/D conversion signal at each gate terminal. N channels to which each bit of the code output from the circuit is connected
The switch means R _41a to _{R 4Na} constituted by FETs have one end connected to the other end of the switch means S _41a to S _4Na , and the other end connects to the terminal T ₂ , and the resistors S _41b to _{S 4Nb} Said switch means S _41a to _{S 4Na}
Switch means R _{41b to} R _4Nb have one end connected to the other end thereof, and each bit of the code output connects to a respective gate terminal, and one end thereof is connected to the other end of the switch means S _41b to S _4Nb , respectively. connection,
The other end is a compensation resistor connected to the inverting input terminal of the operational amplifier 17. This compensation resistor R _41b
~R _4Nb has a resistance value of R _41b :R _42b :...:R _4Nb =
R _41a : R _42a : ...: R _4Na .

When the code input from the A/D conversion circuit is added,
Correspondingly, switch means S _4ia and S _4ib (i=1 to
N) is turned on at the same time. The resistors R _41b to R _4Nb are provided for the purpose of ensuring that the voltage weighted proportionally to the current flowing through R _41a to R _4Na at this time becomes exactly equal to the constant voltage V _C2 by feedback. This cancels out errors caused by variations in the on-resistance of S _41a to S _4Na .

In other words, the on-resistance of the switching means _S41b ... _S4Nb is sufficiently small compared to the resistance _R41b ... _R4Nb and can be ignored, and the resistance _R41b ... _R4Nb is sufficiently large compared to the resistor _R41a ... _R4Na . Then, since the current flowing into the inverting input terminal of the operational amplifier 17 is 0, the following equation holds true.

V _P1 −V _P /R _41b・S ₁ +V _P2 −V _P /R _42b・S ₂ +… …+V _PN −V _P /R _4Nb・S _N =0 (1) However, V _P1 ...V _PN is The voltage at the points P ₁ ...P _N respectively, and S ₁ ...S _N are respectively the switch means S _41b ...
...The value is 1 when _S4Nb is on, and 0 when it is off. Solving equation (1) for voltage V _P , V _P =V _P1 /R _41b・S ₁ +V _P2 /R _42b・S ₂ +...+V _PN /R _4Nb
・S _N /S ₁ /R _41b +S ₂ /R _42b +…＋S _N /R _4Nb
(2) becomes. Also, at this time, the current I flowing through the resistor R _41a ...R _4Na is I=V _P1 /R _41a・S ₁ +V _P2 /R _42a・S ₂ +...+V _PN /R _4N
a・S _N
(3) Therefore, if we set k=R _41b /R _41a =R _42b /R _42a =...=R _4Nb /R _4Na and substitute this used in equation (3) into equation (2), we get V _P =1/k・I/S ₁ /R _41b +S ₂ /R _42b +...+S _N /R _4Nb
(4) becomes. Solving equation (4) for I, I=k・V _P・(S1/R _41b +S2/R _42b +…+S _N /R _4Nb ) =V _P (S1/R _41a +S2/R _42a +…+S _N /R _4Na ) (5). As a result, as is clear from equation (5), even if the on-resistance of the switch means _S41a ... _S4Na varies and the voltages at the points _P1 ... _PN do not have exactly the same value, the resistance R The sum of the currents flowing through _41a ...R _4Na is equal to the sum of the currents flowing when the voltages at points P ₁ ...P _N are all equal to V _P. Therefore,
A constant current determined by a constant voltage V _C2 and weighted resistance values R _41a to R _4Na is applied to the resistors R _41a , R _42a ... _{R 4Na} connected to the point P ₁ ...P _N. Time flows. In this case, the current path is the third
As in the case shown in the figure, the sum of the constant currents corresponding to the code input flows between the terminals T ₁ and T ₂ together with the basic current (active zero).

FIG. 5 is a circuit configuration diagram showing another modified example of the two-wire transmission circuit according to the present invention, which achieves a resolution higher than that of the A/D conversion circuit used.
18 is an input buffer circuit that inputs the detection signal and outputs it to the A/D conversion circuit 8; 19 is a constant voltage element such as a Zener diode that is driven by a constant current from the constant current source 10 and generates a constant voltage V _C3 ; be. Reference numeral 20 denotes a resolution compensation circuit that supplies a current that is higher than the resolution of the A/D conversion circuit 8, and is composed of a D/A conversion circuit 30 and a constant current circuit 40. In the D/A conversion circuit 30, 21 is a constant current circuit connected to the constant voltage V _C3 generated by the constant voltage element 19, and R ₅₁ to R _5N are connected to this constant current circuit 21 and are series resistance circuits. The resistors S ₅₁ to S _5N formed are switch means connected to both ends of the resistors R ₅₁ to R _5N , respectively. In the constant current circuit 40, 22 has one end of its power input terminal connected to one end of the constant voltage element 19 (point of voltage V _C3 ), the other end connected to the terminal T2, and the non-inverting input terminal of ₂₂ . An operational amplifier 23 is connected to one end A of the resistor R ₅₁ and whose output terminal is connected to the inverting input terminal, and 23 has one end of its power input terminal connected to the terminal T ₁ and the other end connected to the terminal T ₂ . , an operational amplifier that connects the output terminal of the buffer circuit 18 to its non-inverting input terminal, and its output terminal to its inverting input terminal;
_R60 is a current limiting resistor connected to both output terminals of the operational amplifiers 22 and 23.

When a detection signal is applied to the input buffer circuit 18, a code output corresponding to this detection signal is generated from the A/D conversion circuit, and a current _{I a corresponding to the code output is generated through the current generation circuit 9 as} in the above-mentioned specific example. Flows between terminals T ₁ and T ₂ . Each bit of the code output from the A/D conversion circuit 8 is output by a switch means _S51.
~S _5N is turned on and off, and accordingly, a voltage V ₂₂ corresponding to the voltage generated at point A appears at the output terminal of the operational amplifier 22. On the other hand, a signal V ₂₃ corresponding to the detection signal from the buffer circuit 18 is sent to the operational amplifier 23.
is output from. As a result, the resistor R ₆₀ receives the signal V ₂₃
The current corresponding to the difference between and V ₂₂ , that is, A/D
A current I _r corresponding to the digitization error between the output of the conversion circuit 8 and the actual detection signal flows. The path of this current I _r is as shown in the figure: terminal T ₁ → power input terminal of operational amplifier 23 → resistor R ₆₀ → output terminal of operational amplifier 22 → power input terminal → terminal T ₂
Therefore, if the value of the resistor R ₆₀ is appropriately selected, the current I _r can be added to the output current so as to complement the resolution of the current I _a flowing through the current generating circuit 9.
As a result, current can be output with high resolution using an A/D conversion circuit with a small number of conversion bits and low resolution.
You can get I ₀ .

Note that the operational amplifiers 14, 17, 23 of the above specific example
By providing a current booster such as a transistor at the output terminal of the amplifier and connecting the power input terminals of the operational amplifiers 14, 17, and 23 to both ends of the constant voltage element, the operating current, which is the base portion of the output current, and the variable portion can be separated. You can also. By doing so, the value of the basic component of the output current can be easily and accurately determined by the constant current circuit.

Furthermore, the output of the A/D conversion circuit 8 is subjected to signal processing such as linear compensation using a microprocessor.
It is also possible to easily obtain a current output corresponding to the processed signal.

In addition, because the two-wire transmission circuit shown in the above example does not have a feedback resistor in the output current path due to its circuit configuration, heat generation is not concentrated in one place but is evenly distributed, so semiconductor ICs can be used. is easy.

〔Effect of the invention〕

As described above, according to the present invention, since a feedback resistor is not used, the range that can be used as a power supply voltage on the oscillator side is wide, and a two-wire transmission circuit with high accuracy and excellent connectivity with a microcomputer is realized. can.

[Brief explanation of drawings]

Fig. 1 is a principle explanatory diagram showing the principle of a conventional two-wire transmission circuit, Fig. 2 is a principle circuit diagram of a two-wire transmission circuit according to the present invention, and Fig. 3 is a concrete diagram of a part of Fig. 2. 4 shows another embodiment, and FIG. 5 shows another modified example of the two-wire transmission circuit according to the present invention. 8...A/D conversion circuit, 30...D/A conversion circuit, 40...Second constant current circuit, _C8 ...Code output, _I91 to _I9N ...Constant current circuit, _S91 to S _9N , _S31〜
S _3N , S _41a to S _4Na , S _41b to _{S 4Nb} ... switch means.

Claims (1)

[Scope of Claims] 1. An A/D conversion circuit that inputs a detection signal from a detector and generates a code output, and generates a constant current whose magnitude is weighted corresponding to each bit of the code output. a constant current circuit, and a switch means that is driven by the code output of each bit to turn on and off the corresponding constant current, and the sum of the constant currents corresponds to the variable portion of the output current corresponding to the detection signal. A two-wire transmission circuit characterized in that it is configured to form a two-wire transmission circuit. 2. An A/D conversion circuit that inputs the detection signal from the detector and generates a code output, and a first circuit that weights the size corresponding to each bit of the code output.
a first constant current circuit that generates a constant current; a switch means that is driven by the code output of each bit to turn on and off the corresponding first constant current; and a code output from the A/D conversion circuit. D/A that generates analog output corresponding to
a conversion circuit; a second constant current circuit that generates a second current proportional to the difference between the output from the D/A conversion circuit and the detection signal; A two-wire transmission circuit characterized in that the sum of the constant currents forms a variable portion of the output current corresponding to the detection signal.