JPH0364078B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to improvement and unification of display control devices.

[Background Art] Conventionally, liquid crystals (hereinafter referred to as "LCDs") have been smaller than CRTs. For example, while a CRT could display 80 characters x 25 lines per screen, an LCD could only display 40 characters x 4 lines. For this reason, LCD display control devices and CRT display control devices are completely different.
One display control device could not share the other display control device.

By the way, in recent years, handheld computers (hereinafter referred to as "HHC") have become popular, and the display device of this HHC is an LCD due to the need for low power consumption.
A display device is used. In this case, the LCD is
The screen is divided into two in the vertical direction and placed in close contact with each other for parallel display. And H.H.C.
As the performance and functionality of LCDs continues to improve,
The display performance of is approaching that of CRT.
Therefore, in HHC, there is a demand for a display control device that can drive both LCD and CRT display devices. The reason for this request is that although LCDs and CRTs currently perform completely different display controls, LCDs and CRTs can essentially perform the same display control. This is because there is a background.

[Problems with the background art] However, in reality, first, the display specifications of the LCD are physically fixed (for example, the number of horizontal scanning lines is fixed by the LCD),
Since LCDs do not require vertical or horizontal retrace lines, they can be used for LCDs with different specifications while maintaining full software compatibility.
Similar to CRTs, there is a problem in that sufficient display control cannot be performed.

Furthermore, conventional LCDs have the problem of not being able to display gradations (halftones) and therefore not being able to display the same images as CRTs.

Furthermore, since LCDs generally have slow display clock speeds, the speed of the display control device is slow, and memory access from the CPU is also slow, resulting in lower device performance than with CRT displays. .

In addition, conventional display control devices do not allow the addition of external registers, so when configuration control is required,
There is a problem that this requires a large number of circuits.
Furthermore, when using conventional software, if the device has expanded functions, there is a problem that the expanded functions cannot be protected when the software is executed.

[Object of the Invention] The present invention has been made by focusing on the above-mentioned conventional problems, and achieves various specifications while completely maintaining software compatibility.
The purpose of the present invention is to provide a display control circuit that performs gradation display on an LCD display, achieves the same level of access as a CRT display, enables configuration control, and also provides protection when functions are expanded in conventional software. That is.

[Summary of the Invention] The present invention provides mode selection means for selecting a mode for display control of a CRT or a mode for display control of a liquid crystal, a means for executing display control of the CRT, and a means for executing display control of the liquid crystal. It has the means to do so.

[Embodiment of the Invention] FIG. 1 is a block diagram showing an embodiment of the present invention.

The LCDC 10 is an LSI that controls display on an LCD or CRT. This LCDC 10 includes a CRT controller 11 and a driver 1 that amplifies data signals.
2, an attributive graphic 13, an alpha 14, a color selector 15, a color palette 16 for performing color conversion, a composite color generator 17, and a mode select register 71. The CRT controller 11 generates a timing signal based on the set parameters. The color selector 15 is
When a color CRT is used as the display means 20, it outputs a 4-bit digital signal specifying the color. Composite color generator 17 is used to generate a Y signal and an analog
D/A conversion to create RGB signals,
It generates output signals in accordance with each mode of LCD types 1 to 3.

LCDC 10 also has an internal control register 18 and the circuitry shown in FIG.

As the display means 20, a CRT or LCD is used.

External to LCDC10 is DRAM or SRAM.
VRAM (video RAM) 30 consisting of
An address latch 31 that latches the address signal from the LCDC 10, a data latch 32 that latches the mode from the LCDC 10, a character generator 33 that converts character information into dots based on the signal from the data latch 32, and a character generator 33 that changes character information to dots based on the signal from the data latch 32. An external control register 34 for receiving data is provided.

Next, an overview of the operation of the above embodiment will be explained.

Figure 2 shows the I/O installed in the LCDC10.
FIG. 3 is a diagram showing all registers. This I/O register has multiple register functions that are different from each other.

Here, in order to display characters on the CRT serving as the display means 20, a data signal from a CPU (not shown) is once written into the VRAM via the driver 12. The CRTC 10 repeatedly reads the VRAM 30 in accordance with the synchronization and scanning of the CRT. This read data is latched in a data latch 32, converted into dots by a character generator 33 and alpha 14, converted into a color signal by a color selector 15, and sent to the CRT. Further, when it is desired to perform color conversion, the color palette 16 is used, D/A converted by the composite color generator 17, and the Y signal is sent to the CRT.

On the other hand, when an LCD is used as the display means 20, the composite generator 17 does not perform D/A conversion but performs another operation.
Controls the LCD display. This operation will be described later. Note that when using an LCD,
The signal sent to the LCD is LCDC1 in Figure 1.
0 and the display means 20,
It is shown in parentheses.

In this way, the above interface becomes
Commonly used by CRT and LCD.

D to the I/O register as an address signal.
(HEX) That is, when "1101" is sent, data "P, D6, . . . , D0" can be written as shown in the table of FIG. This data specifies a register that functions as an address for the register bank shown in FIG. Here, the above "P" is a protect bit which will be described later, but apart from this, the 7 bits "D6,...,D0" are
This is the same address as shown in FIG. 3, and the correspondence between this address and the functions of each register is also shown in FIG.

For example, the 7 bits of "D6,...,D0" in address D (HEX) in Figure 2 are "1100101".
If so, the 7-bit data in FIG. 3 functions as a register as a monitor control. In this case, bit 7 is a bit that selects the mouse or light pen as the input means,
When it is "1", the mouse is selected, and when it is "0", the light pen is selected.
Bit 6 is used as VRAM30 shown in Figure 1.
This bit selects SRAM (static RAM) or DRAM (dynamic RAM); when it is ``1'', SRAM is selected, and when it is ``0'', DRAM is selected. Bit 5 indicates that the display means 20 is LCD or CRT.
is a bit that selects , and when it is "1"
It selects LCD, and when it is "0", selects CRT.

On the other hand, if the 7 bits of "D6,...,D0)" in address D (HEX) in Figure 2 are "1100110", the 8 bit data in Figure 3 can be used as test/LCD control/raster adjust. The function of the register is demonstrated. In this case, bits 5, 4, 3, and 2 are the bits that select LCD types 1 to 3 (each of these types will be discussed below), and bits 1 and 0 are the bits that select the vertical display as described in Figure 4. This bit selects the amount of position (raster adjust).

FIG. 4 is a diagram showing a vertical display position adjustment circuit.

The vertical display position adjustment circuit 40 includes a shift register 41 and a selector 42. The shift register 41 receives a vertical synchronization signal and a horizontal synchronization signal as a clock, and outputs signals delayed by 0, 1, . . . , 5, and 6 times, respectively, of the horizontal synchronization signal. The output signal with the same timing as the input horizontal synchronization signal is the upper frame signal.
It becomes FLM (U). This upper frame signal FLM
(U) is for timing when scanning the upper liquid crystal 43 (see FIG. 4B) provided at the top of the screen in the vertical direction.

The selector 42 selects the output signal of the shift register 41 and sends it out as the lower frame signal FLM(L). The lower frame signal FLM(L) is
The timing is taken when scanning the lower liquid crystal 44 (see Figure 4B) provided at the bottom of the screen in the vertical direction, and the timing is determined relative to the display phase of the upper liquid crystal 43 according to the number of scanning lines on the screen. , which changes the display phase of the lower liquid crystal 44. In the case of the embodiment, the display phase of the lower liquid crystal 44 lags behind the display phase of the upper liquid crystal 43. In addition, the upper liquid crystal 4
3 and the lower liquid crystal 44 are arranged in close contact with each other to form one screen.

For example, as shown in Figure 4B, 640×204
When displaying a 640×200 screen using an LCD, it is necessary to lower the display portion 43d by two scanning lines as the border 43b of the upper liquid crystal 43. For this purpose, the lower frame signal FLM(L) is
There is a delay of two scan lines. This state is shown in FIG. 4A.

In FIG. 4, the raster adjust 0 signal (indicated by RAJ0 in FIG. 3) and the raster adjust 1 signal (indicated by RAJ0 in FIG.
The amount of delay of the lower frame signal FLM(U) can be controlled by changing the amount of the lower frame signal FLM(U). In other words, the raster adjust 0 signal,
Set the raster adjust 1 signal to "0, 0", "0,
1'', ``1,0'', and ``1,1'', the number of delayed lines is 0, 2, 4, and 6, respectively. By appropriately adjusting the number of delays, the upper liquid crystal 4
3 and the lower liquid crystal 44, it is possible to prevent a break in the display portion from occurring.

Figure 5 shows the composite color generator 1.
FIG. 7 is a circuit diagram showing details of FIG. This circuit 17 is
It generates display control signals when displaying a CRT and display control signals when displaying an LCD.As LCD display control signals, there are three types of control signals for LCD types 1, 2, and 3. occurs.

The D/A converter 17a is a color palette 1
This converts the R, G, and B digital signals received from 6 into analog signals, and the converted analog signals are used as display control signals for the CRT. The adder 17b inputs the R, G, and B digital signals sent from the color palette 16, and performs the calculation (4G+2R+B).
The calculation result is weighted and output as a binary value with a predetermined number of bits. The D/A converter 17c converts the output signal of the adder 17b into an analog signal and outputs it to the CRT as a Y signal (luminance signal).

Further, the thinning circuit 17d converts the duty cycle of the voltage applied to the LCD for each dot according to the brightness of the dot to be displayed on the LCD, and determines the output value for each vertical scan. (thinning). This thinning circuit 17d is
Consists of ROM and its output signal LCD type 1
(described later), and this signal is sent to the shift register 52 (see FIG. 5A).

The field counter 17e counts the vertical synchronizing signal and outputs the result in 3 bits. This 3-bit output signal and the adder 17
Based on the upper four bits of the output signal b, the thinning circuit 17d executes the above thinning operation.

The series-parallel converter 17f is the thinning circuit 1
7d output signal into a 4-bit parallel signal. The output signal of this converter 17f is
This is a display data signal for LCD type 2 (described later), and this signal is sent to the shift register 53 (see FIG. 5B).

The latch circuit 17g latches the upper 4 bits of the output signal of the adder 17d.
This outputs the brightness weighting signal of the LCD. The output signal of this latch circuit 17g is a signal data signal for LCD type 3 (described later), and this signal is sent to a shift register 54 (see FIG. 5C).

FIGS. 5A to 5C are diagrams showing how shift registers are arranged in each type of LCD segment driver.

In these figures, shift registers 52, 5
The latches existing between each of 3 and 54 and the liquid crystal 43 are omitted from illustration.

The WCK weight clock circuit exists in the CRT controller 11 and is located at address 67 (HEX) in FIG.
The weight clock WCK is created by counting down the SCK clock according to the EH bits 4 to 0 of the weight clock.

FIG. 5A shows an arrangement in which the application of the voltage is controlled for each vertical scan of the screen using the thinning circuit 17d in units of one dot. This is type 1 of LCD. That is, the number of dots in the horizontal direction of the liquid crystal 43 (for example,
320 dots) and the same number of flip-flops 52
are provided to constitute one serial shift register. This shift register includes a thinning circuit 17d.
The output signals of are sequentially applied to perform a predetermined display.

Figure 5D shows that for LCD types 1 and 2,
This shows data when 8-step gradation control is performed. That is, depending on the brightness,
When a predetermined number of fields among the eight fields are thinned out, no voltage is applied to the dots concerned. With this, the average brightness can be controlled in eight levels.

Here, a predetermined field (for example, eight fields) is used as a unit, and attention is focused on a predetermined dot between the eight fields. When it is desired to make the brightness of that dot the highest, voltages are applied to the flip-flop 52 corresponding to that dot for all eight fields. This is shown as bit "111" in FIG. 5D. When it is desired to increase the brightness to a medium level, the signal input to the flip-flop 52 corresponding to the dot is input a predetermined number of times (for a predetermined field).
Thin out only. This is shown, for example, as bit "100" in FIG. 5D. In other words, 8
Thin out 3 fields out of the fields. This thinning operation is executed by the thinning circuit 17d.

On the other hand, FIG. 5B shows a flip-flop 52, which is basically the same as the above-mentioned LCD type 1.
Instead of configuring all of the flip-flops in series to configure one shift register, one shift register is configured by a predetermined number of flip-flops 53, that is, a plurality of parallel shift registers is shown. This is type 2 of LCD. By doing this, compared to LCD type 1,
The power consumption of flip-flop 53 is reduced.
In this case as well, the principle explained in FIG. 5D is applied. In FIG. 5B, one shift register is composed of 80 flip-flops, and there are four shift registers in total (indicated by , , ).
An example in which there exists is shown. The luminance information from the thinning circuit 17d is stored in the order of . . . , and the switching is performed by the clock ECK.

In addition, in FIG. 5C, by giving the minimum unit time of the brightness width to each dot, the liquid crystal 43
Controls for applying voltage to are shown.
This is type 3 LCD. The minimum unit time of the luminance width is, for example, 1/16 of a half cycle of the alternating current signal (the time to drive one dot or the time to drive one line). We use 4 bits to do this, and each bit corresponds to 1, 2, 4,
It has a meaning of 8 times the weight width, that is, each bit is given a weight. Then, for each dot, the minimum time and the weight width are combined in 4 bits corresponding to the values to control the voltage application time.

An example of the relationship between the output signal of the latch circuit 17g and the LCD drive waveform is shown in FIG. 5E.
That is, within one horizontal scanning time, a voltage is applied to the liquid crystal according to the brightness for an integral multiple of the minimum unit time of the width of the brightness. This results in an average brightness of 16
Can be controlled in stages. In the case of Figure 5 E, +2.5V and -
A voltage is applied to the liquid crystal with a predetermined duty waveform according to an alternating current signal having a voltage of 2.5V. In the CRT controller 11, the weight weight pulse
Based on WCK, pulses W0, W1, and W3 are generated. The pulse W0 corresponds to the minimum unit time of the brightness width.The pulses W1, W2, and W3 correspond to the minimum unit time of the brightness width.
This pulse has a pulse width that is 2, 4, or 8 times that of pulse W0. When the output signal of the latch circuit 17g is "1111", it is preferable that the alternating current signal is applied throughout one horizontal scanning time;
Some gaps may exist.

That is, each display control signal of LDn (n is an integer from 0 to 7, and this LDn is digital information sent from the shift register 54 and is composed of 4 bits) shown in FIG. The above pulse W
0, W1, W2, and W3 processed by a logic circuit, the LCD is controlled. in particular,
Four AND circuits and one RO circuit are provided,
LD0 and W0 are processed by the first AND circuit,
LD1 and W1 are processed by the second AND circuit,
LD2 and W2 are processed by the third AND circuit,
LD3 and W3 are processed by the fourth AND circuit,
The output signals of the above four AND circuits are input to the above OR circuit, and based on the output signals of this OR circuit,
LCD brightness is controlled.

In this way, the intermediate brightness (halftone) of the dot
You can set multiple .

FIG. 6 is a chart showing display control signals for each display means.

This chart shows display control signals generated for each of CRT and LCD types 1 to 3. Here, VSYNC is the vertical synchronization signal, HSYNC is the horizontal synchronization signal, LC is the clock that takes the video signal from the shift register to the latch, SCK is the clock that takes the video signal into the shift register, and ECK is the clock that takes the video signal from the shift register to the latch. WCK is a weight clock that is a unit of luminance weight. B, G, R, and Y are a blue primary color brightness signal, a green primary color brightness signal, a red primary color brightness signal, and a monochrome brightness signal, respectively. Further, CH is a color phase signal, and M is an alternating current signal. Note that U and L in the figure are symbols indicating upper liquid crystal use and lower liquid crystal use, respectively.

FIG. 7 is a diagram showing the relationship between CPU time slots and display time slots.

FIG. 71 shows a CPU time slot and a CRT display time slot, both time slots occurring repeatedly with approximately the same length. On the other hand, FIG. 72 shows the CPU time slot and the LCD display time slot, and the length of the CPU time slot is set to be approximately three times the length of the LCD display time slot.

Regarding Fig. 7 2, overall, the total time of the LCD display time slot is shortened, and the CPU
The total time of the time slot is increased. This is because the access speed of an LCD is generally slower than that of a CRT, so there is no problem even if the LCD display time slot is reduced, and the free time created by this can be used as a CPU time slot. Therefore, this is to speed up the operation of the CPU.

FIG. 7A is a diagram showing a memory access speeding up circuit during liquid crystal display.

In this figure, the basic clock from the basic clock circuit 61 is transmitted to the CRT timing signal generation circuit 62 and the LCD timing signal generation circuit 63.
sent to. The CRT timing signal generation circuit 62 generates a CRT row address select signal.
Column address select signal for CRAS and CRT
Send to CCAS and selector 64. The LCD timing signal generation circuit 63 sends an LCD row address select signal LRAS and an LCD column address select signal LCAS to the selector 64.

Further, the selector 65 serves as the display means 20.
Selector 6 receives a CRT/LCD switching signal indicating whether to use CRT or LCD.
4, the row address select signal CRAS for CRT or the row address select signal LRAS for LCD is output as the row address select signal RAS, and the column address select signal CCAS for CRT or the column address select signal LCAS for LCD is output. , column address select signal
Output as CAS.

As a result, the time slot shown in FIG. 7D1 when using the CRT and the time slot when using the LCD shown in FIG. 72 are switched and used. During one cycle of repeated memory access,
There are two CPU time slots in the time slot when using a CRT, but there are three CPU time slots in the time slot when using an LCD, so the CPU processing becomes somewhat faster. In the figure, CPU indicates a CPU time slot, CRT indicates a CRT time slot, LCD indicates an LCD time slot, (E) indicates an even number, and (O) indicates an odd number.

Incidentally, FIG. 7C shows a general time slot when using a CRT. In the figure, ROW indicates a row address signal, and COL indicates a column address signal.

Figure 7B shows the CPU access during LCD display.
This is a circuit diagram that is slower than CPU access when displaying on a CRT. When this circuit sends the basic clock as is to the timing signal generation circuit 67,
When the time slot when using a CRT shown in FIG. The time slot state when using a CRT is shown in D3. The circuit shown in FIG. 7A is better than the circuit shown in FIG. 7B.
Memory access is faster when using the LCD.

FIG. 8 is a circuit diagram showing an external control register.

In the figure, internal control register 18
is provided inside the LCDC 10, and the external control register 34 is provided outside the LCDC 10. Both control registers 18 and 34 are connected to each other via a data bus. The gate 35 accepts data when the horizontal synchronization signal is present. Therefore, external control register 34 can receive data from internal control register 18 when the horizontal synchronization signal is occurring.

Various uses of the external control register 34 are conceivable; for example, it may be used to store a signal for selecting between CRT and LCD, or may be used as an external page register. Therefore, the external control register 34 has the advantage of allowing configuration control.

FIG. 8A is a time chart showing the relationship between the horizontal synchronization signal and the data bus signal. Figure 8B
FIG. 2 is a diagram showing display timing and synchronization signal timing. In this figure, the shaded part is the timing of the synchronization signal.

Note that a vertical synchronization signal may be used instead of the horizontal synchronization signal. These pulses are collectively referred to as strobe pulses.

By doing as shown in FIG. 8, there is an advantage that when the external control register 34 is provided, there is no need to increase the number of pins of the IC, and no new peripheral components are required.

FIG. 9 is a circuit diagram for protecting predetermined bits.

In the figure, the mode select register 71 is
It is shown in the LCDC 10 in FIG. 1, and receives a write strobe signal from the CPU to address 8 (HEX), and takes in and outputs eight mode selection signals corresponding to bits 0 to 7. The write strobe signal is output from port 8 (HEX) of the I/O register shown in FIG.
The output terminals of bits 6 and 7 each have
AND circuits 72 and 73 are connected.

Here, bit 6 has the meaning of extended function 160×200 color mode, and bit 7 has the meaning of
This has the meaning of standby mode.
The other ends of the AND circuits 72 and 73 are connected to port D (HEX) of the I/O register shown in FIG.
A protect bit "P" signal, which is bit 7 of the register bank address, is applied.

In other words, when the protect bit "P" is "1", bits 6 and 7 of the mode select register 71 are output as they are, and conversely, when the protect bit "P" is "0", the mode select register 71 is output as is. Bits 6 and 7 of 71 are not output. That is, if the protect bit is set, the enhanced bit is ignored.

Therefore, in the past, for example, bits 6 and 7 were not used, so it is expected that some software on the market uses bits 6 and 7 without paying attention to them. That is, in the case of the above example, bits 6 and 7 are not defined, so they may be neither "1" nor "0", and it is not known which one they are.
However, when functionality is expanded, it is generally difficult to maintain compatibility between various programs.
Even in that case, it is only necessary to set the protect bit "P" to "0", so there is an advantage that the operation for ensuring software compatibility is very easy.

[Effects of the Invention] The present invention can realize various specifications while completely maintaining software compatibility.
Since gradation display is possible on LCD display,
It can be used to the same extent as a CRT display, and
It has the advantage of enabling configuration control and furthermore, enabling protection when functions are expanded in conventional software.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a functional explanatory diagram of the I/O register, Fig. 3 is an explanatory diagram of the register bank, Fig. 4 is a circuit diagram showing the vertical display position adjustment circuit, and Fig. 4A is the relationship between data signals and frame signals. Figure 4B is a time chart showing the display status on the LCD, Figure 5
The figure is a block diagram showing the details of the composite color generator, and Figures A, B, and C are of each type.
A diagram showing the arrangement of shift registers in the LCD segment driver, Figure 5D is for LCD type 1,
2 is used, the diagram shows the relationship between the upper 3 bits of the Y signal before D/A conversion and the field, Figure 5E is a diagram showing the combination of the minimum unit time of luminance, and Figure 6 is A chart showing the display control signals for each display means, FIG. 7 is a diagram showing the relationship between the CPU time slot and display time slot, FIG. 7A is a diagram showing a memory access speeding up circuit during liquid crystal display, and FIG. 7B is a diagram showing the relationship between the CPU time slot and the display time slot. is a circuit diagram in which memory access is not accelerated when using a liquid crystal display, Figure 7C is a diagram explaining a general time slot when using a CRT, Figure 7D is a diagram showing one cycle of repeated memory access, Figure 8 is a diagram showing the external control register, Figure 8A is a time chart of the external control register, Figure 8B is a diagram showing the relationship between the horizontal synchronization signal and the data bus signal, and Figure 9 is a diagram showing the protection of specified bits. FIG. 10... LCDC, 11... CRT controller, 1
7a...D/A converter, 17b...Adder, 17
c... D/A converter, 17d... Thinning circuit, 1
7e...Field counter, 17f...Series-parallel converter, 18...Internal control register,
19...Address latch/timing generation, 20...
Display means, 30...VRAM, 34...External control register, 41...Shift register, 42...Selector, 43...Upper liquid crystal, 44...Lower liquid crystal, 5
2, 53, 54...Shift register, 71...Mode select register.

Claims (1)

[Claims] 1. An internal control register provided inside the display control IC; a data bus for display memory; an external control register provided outside the display control IC; strobe pulse generating means for generating a strobe pulse during a non-display time; and gate means for passing a data signal from the internal control register to the external control register via the data bus when the strobe pulse is being output. A display control device comprising: and; 2. The display control device according to claim 1, wherein the strobe pulse is a vertical synchronization signal or a horizontal synchronization signal.