JPH03640B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a volume control device for a piezoelectric buzzer included in electronic equipment such as an electronic watch or a small electronic computer.

Electronic devices such as electronic watches and small electronic calculators include
Some devices are equipped with a piezoelectric buzzer to generate time signals, alarm sounds, etc., or numeric keypad operation sounds. This piezoelectric buzzer is made up of a piezoelectric element attached to a diaphragm made of metal or glass, and is driven by a pulse signal to generate a sound. Furthermore, a piezoelectric buzzer has the property of producing a maximum sound when a pulse signal having a frequency equal to its resonance frequency is applied. However, in general, the above-mentioned resonance frequency changes depending on various factors, such as the support condition of the diaphragm, the mounting position of the terminal that provides the pulse signal to the piezoelectric element, and the strength of the pressing force. Buzzers are not always designed to sound at maximum volume, and the volume may need to be adjusted using a volume switch or the like.

This invention was made in consideration of the above circumstances, and its purpose is to change the frequency of a pulse signal that drives a piezoelectric buzzer in fine steps by operating an external switch, thereby
An object of the present invention is to provide a volume adjustment device for a piezoelectric buzzer, which adjusts the volume by changing the degree of deviation between the resonance frequency of the piezoelectric buzzer and the frequency of the drive pulse signal.

An embodiment in which the present invention is applied to an electronic timepiece will be described below with reference to the drawings. FIG. 1 is an overall circuit configuration diagram of an electronic timepiece. In the figure, 1 is an oscillator,
A reference frequency signal φ having a frequency of 32768 Hz generated by this oscillator 1 is input to a frequency dividing circuit 2, and is frequency-divided by this frequency dividing circuit 2 to a pulse signal 1P/S having a period of 1 second. Further, the pulse signal 1P/S is input to the time counting circuit 3 and counted, and hour, minute, and second information (time information) is obtained. The carry signal from the time counting circuit 3 is input to a date counting circuit 4 and counted, and the date counting circuit 4 obtains year, month, day, and day of the week information (date information). Furthermore, both the time information and date information obtained by the time counting circuit 3 and date counting circuit 4 are sent to a display switching circuit 5.
It is configured to be sent to the display unit 6 via the display unit 6 and displayed in a switched manner.

The pulse signal _P1 output from the one-shot circuit 7 each time the mode changeover switch SW1 is operated is 3.
The signal is inputted to a mode counter 8 consisting of a forward counter and counted. Therefore, the contents of the mode counter 8 change sequentially as "0", "1", "2", "0", etc., and the terminals corresponding to the contents "0", "1", "2"" The signals outputted from "0", "1", and "2" are input to the display switching circuit 5 and the setting control circuit 9, and the operations of the display switching circuit 5 and the setting control circuit 9 are controlled, respectively. On the other hand, when the digit selection switch SW2 and the correction switch SW3 are operated, the one-shot circuit 10,
Pulse signals P ₂ and P ₃ outputted from the setting control circuit 9 are inputted to the setting control circuit 9, and control signals C ₁ , C ₂ and C ₃ outputted from the setting control circuit 9 are inputted to the time counting circuit 3 and the time counting circuit 3, respectively. It is input to a date counting circuit 4 and an alarm time storage circuit 12. Therefore, when the content of the mode counter 8 is set to "0" (hereinafter referred to as mode "0"), 2 is input only from the terminal "0".
An "H" (high level) signal of a value logic level is output (therefore, "L" (low level) signals are output from the other terminals "1" and "2".)
This “H” signal is applied to the display switching circuit 5 and the setting control circuit 9. At this time, the time information from the time counting circuit 3 is displayed on the display section 6 by the display switching circuit 5.
is selected and displayed by the switching operation. Also, when the digit selection switch SW2 is operated while this mode is set to "0", one of the hour, minute, and second digits of the time counting circuit 3 is selected and unselected by the control signal _C1 . The entered digit is displayed on the display section 6, for example, by blinking.

At this time, when the correction switch SW3 is operated, a control signal is sent to set the desired time for the selected digit.
It is configured so that it can be set by _C1 . Further, while the content of the mode counter 8 is set to "1" (when the mode is "1"), an "H" signal is output only from the terminal "1", and the display switching circuit 5,
It is input to the setting control circuit 9. At this time, the date information is displayed on the display section 6 instead of the above-mentioned time information, and when the digit selection switch SW2 and correction switch _SW3 are operated, the year, year,
It is possible to modify the contents of desired digits among the month, day, and day of the week digits. Furthermore, when the content of the mode counter 8 is set to "2" (mode "2"), the "H" signal is output only from the terminal "2", and the display switching circuit 5 and the setting control circuit 9 is input. At this time, when the digit selection switch SW2 and correction switch SW3 are operated, the control signal _C3 is outputted, and the alarm time can be set in the alarm time storage circuit 12. In this case, the alarm time is sent to the display unit 6 via the alarm time storage circuit 12 and displayed. Further, the alarm time is inputted to the input terminal B of the matching circuit 13, and compared with the time information from the time counting circuit 3 inputted to the input terminal A of this matching circuit 13. When a match is detected, a match detection signal output from the output terminal C of the match circuit 13 is input to the alarm control circuit 14, and the alarm control circuit 1
The piezoelectric buzzer circuit 15 is driven by the pulse signal f output from 4, and an alarm sound is emitted.

By the way, in this embodiment, when the coincidence detection signal is output or the switches SW1, SW2, SW
3, the frequency of the pulse signal f outputted from the alarm control circuit 14 to the piezoelectric buzzer circuit 15 is changed, and thereby the piezoelectric buzzer circuit 1
It is configured such that the volume of the alarm sound emitted from the alarm 5 can be optimally controlled. For this reason,
Mode selection switch SW1, digit selection switch SW
Each operation signal of 2 is input to the AND gate 16,
In addition, the output of the AND gate 16 is output from the alarm control circuit 14.
At the same time, it is also input to the AND gate 17 together with the pulse signal P ₃ from the one-shot circuit 11, and the output of the AND gate 17 is further input to the alarm control circuit 14. Further, a reference frequency signal φ from the oscillator 1 is input to the alarm control circuit 14.

Next, referring to FIG. 2, the above sound alarm control circuit 1
4. Details of the piezoelectric buzzer circuit 15 will be explained. In this embodiment, the counter 20 operates as a decimal counter, and performs a counting operation by inputting the output pulses of the AND gate 17 to its input terminal. Therefore, each time the correction switch SW3 is operated while the mode changeover switch SW1 and the digit selection switch SW2 are being operated simultaneously, the AND gate 17
The contents of the counter 20 change sequentially from "0" to "1", "2", ... "9", "10" by the pulses output from the counter, and immediately change to "0" until it reaches "10".
Changes to. Further, a signal representing the contents of the counter 20 is input to a decoder 21 and decoded. Then, the contents of the counter 20 are “0”, “1”,
When "2", ... "9", "10", the corresponding output terminals of the decoder 21 are "0", "1", "2", ... "9",
An “H” signal is output from “10”, and the decoder 22,
23. On the other hand, decoders 22 and 23 are provided for counters 24 and 25, respectively. Then counter 2
4 is constituted by a quaternary counter, and performs counting operation by inputting a carry signal l, which will be described later, to its input terminal (+1). Further, the decimal number of the counter 25 changes sequentially from 22-decimal, 21-decimal, 20-decimal, . It is a counter, and performs a counting operation by inputting the reference frequency signal φ to its input terminal (+1). Therefore, the coincidence detection signal or the output signal of the AND gate 16 is
7 to the AND gate 26. When the AND gate 26 is opened, the reference frequency signal φ output from the AND gate 26 is counted by the counter 25. Further, the contents of the counter 25 are decoded by the decoder 23, and the contents of the counter 24 are further decoded by the decoder 22. In this case, when the content of the counter 20 is "0", that is, when the "H" signal is output from the output terminal "0" of the decoder 21, and when the content of the counter 24 is "0" or "1", ”,
When the contents of the counter 25 become “5”, “5”, “6”, and “6” at the time of “2” and “3”, the decoder 23
Each of the decoders 22 and 23 is configured such that the carry signal l is outputted one by one from each of the decoders 22 and 23.
Note that the carry signal l is input to the reset terminal R of the counter 25 to reset the counter 25,
At the same time, it is added to the input terminal of the counter 24 and counted as described above. As a result, the counter 25 operates as a quinary, quinary, hexadecimal, and hexadecimal counter (total 22 decimals) when the content of the counter 20 is "0", and the counter 25 also operates as a counter in quinary, quinary, hexadecimal, and hexadecimal (total 22 decimals). When the content is "3", the decoded output of the decoder 22 (the pulse signal f) is applied to the piezoelectric buzzer circuit 15, and an alarm sound is emitted. Similarly, when the content of the counter 20 is "1", the counter 25 indicates that the content of the counter 24 is "0",
As it changes from “1”, “2”, “3”, it becomes quintal, 5
Each decoder 22, 23 is configured to operate as a base, quinary, and hexadecimal (21 base in total) counter.

In exactly the same way, counter 25 is replaced by counter 20.
The decoders 22 and 23 are similarly configured to operate as 20-decimal, 19-decimal, . Further, when the content of the counter 20 becomes "10", a reset signal RS is outputted from the decoder 21, and this reset signal RS is applied to the reset input terminal R of the counter 20 to reset the counter 20. .

On the other hand, when the pulse signal f is input to the piezoelectric buzzer circuit 15, it is amplified by the amplifier 30.
It is added to the base of the NPN transistor 31.
Further, a resonant circuit 34 is connected between the collector of the transistor 31 and the power terminal (+), which is formed by connecting a diaphragm 32 to which a piezoelectric element is attached and a coil 33 in parallel. Further, the emitter of the transistor 31 is connected to a power supply terminal (-). Therefore, the piezoelectric buzzer circuit 15 is driven by the pulse signal f to emit an alarm sound.

Next, the operation of the above embodiment will be explained. Oscillator 1
always generates a reference frequency signal φ, and this reference frequency signal φ is applied to the frequency dividing circuit 2 and the alarm control circuit 14. On the other hand, the frequency dividing circuit 2 generates the signal 1P/S once every second and inputs it to the time counting circuit 3, so that the time counting circuit 3 and the date counting circuit 4 execute time counting operation, and these circuits 3 , 4 are provided to a display switching circuit 5. When the content of the mode counter 8 is set to "0" by operating the mote changeover switch SW1, the above time information is selected by the display changeover operation of the display changeover circuit 5, and the display section 6
will be displayed. Further, when the content of the mode counter 8 is "1" and the mode "1" is set, date information is selected and displayed on the display section 6. Further, when the content of the mode counter 8 is "2" and the mode "2" is set, the alarm time set in the alarm time storage circuit 12 is selected and displayed on the display section. Also, when any of the modes "0", "1", and "2" is set, the time displayed on the display section 6 can be changed by operating the digit selection switch SW2 and the correction switch SW3. The contents of the desired digits of information, date information, and alarm time can be corrected while visually viewing the display unit 6.

Next, when the alarm time set in the alarm time memory circuit 12 is reached and an alarm sound is emitted from the piezoelectric buzzer circuit 15, the volume of the alarm sound is controlled by operating the switches SW1 to SW3. The operation will be explained with reference to the time charts of FIGS. 2 and 3. When the alarm time and the time information match and a coincidence detection signal is output from the coincidence circuit 13, the AND gate 26 is opened and the reference frequency signal φ is input to the input terminal of the counter 25 and counted. Assuming that the content of the counter 20 is "0" when the coincidence detection signal is output,
An “H” signal is output only from the output terminal “0” of the decoder 21 and is applied to the decoder 22.
Also, at this time, since the content of the counter 24 is "0", an "H" signal is output from the output terminal "0" of the decoder 22 and is applied to the decoder 23.
After outputting the coincidence detection signal, the counter 25 receives 5
When the first reference frequency signal φ is input and its content becomes "5", the first carry signal l is output from the decoder 23, resetting the counter 25 and changing the content of the counter 24 to "1". . Therefore, this time, the "H" signal starts to be output from the output terminal "1" of the decoder 22, and when five more reference frequency signals φ are input to the counter 25 and the content becomes "5", 2 The first carry signal l is output, the counter 25 is reset, and the content of the counter 24 becomes "2".
Therefore, next, the "H" signal starts to be output from the output terminal "2" of the decoder 22, and then
When the reference frequency signal φ is inputted and its content becomes "6", the third carry signal l is outputted, the counter 25 is reset, and at the same time the content of the counter 24 becomes "3" and the decoder 22 An "H" signal begins to be output from the output terminal "3". Then, when six more reference frequency signals φ are input and the contents of the counter 25 become "6", 4
The first carry signal l is output, and the counter 25
is reset and the contents of the counter 24 change to "0", returning to the initial transistor state, that is, the state at the time of outputting the coincidence detection signal. During the above operation, the pulse signal f of the "H" signal is output only during the period when the content of the counter 24 is "3".
This pulse signal f drives the piezoelectric buzzer circuit 15 to emit an alarm sound. FIG. 3B shows the contents of the counter 24, the base number of the counter 25, and the output states of the carry signal 1 and the pulse signal f during the above-described operation. That is, after the coincidence detection signal is output, as the contents of the counter 24 sequentially change from "0" to "1", "2", "3", and "0", the counter 25 changes from quinary to quinary, 6
The counter 25 operates as a decimal and hexadecimal counter, and only during the period when the content of the counter 24 is "3", the pulse width ("H" signal period) is 183.1 μsec. pulse signal f
is what is output. Since this one-cycle operation is repeated in the same way thereafter, the pulse signal f having the above-mentioned output waveform is repeatedly output, and the alarm sound continues to be emitted.

By the way, in order to adjust the volume of this alarm sound, press the mode changeover switch SW1 and the digit selection switch SW2 at the same time, and operate the correction switch SW3 once, and one pulse signal will be output from the AND gate 17. It is applied to the input terminal (+1) of the counter 20. Therefore, the counter 20 is incremented by 1 and becomes "1", and an "H" signal is output from the output terminal "1" of the decoder 21 and given to the decoder 22. Therefore, the above switch SW
While SW1 and SW2 are being pressed simultaneously, the output of the AND gate 16 becomes "H" and the AND gate 26 is opened. Therefore, the reference frequency signal φ is input to the counter 25 and counting begins, and when the first five reference frequency signals φ are counted by the counter 25, the first carry signal l is output and the counter 25 is reset. At the same time, the contents of the counter 24 are incremented by 1 and become "1". Further, when the reference frequency signal φ is outputted five times, five times, and six times, the second, third, and fourth carry signals l are outputted, and the counter 25 is reset each time, and the counter 25 is reset each time. 24 is +1 and becomes “2”,
It changes to “3” and “0”. Then, while the content of the counter 24 is "3", a pulse signal f of "H" is output and an alarm sound is emitted. The above operation completes one cycle of operation, and the same operation is repeated thereafter. FIG. 3C explains the operation in this case. That is, as the contents of the counter 24 sequentially change from "0" to "1", "2", "3", and "0", the counter 25 changes from 5 to 5
Operates as a decimal and hexadecimal counter (therefore, 21
The pulse signal f having a pulse width (“H” signal period) of 183.1 μsec is output only during the period when the content of the counter 24 is “3”.
The pulse signal f output in the case of Fig. 3 C
The frequency is higher than that of the pulse signal f in the case shown in FIG. 3B, and the degree of deviation from the resonance frequency of the piezoelectric buzzer changes, so the volume changes as well as the sound quality of the alarm sound.

The content of the counter 20 is set to “2” by the same operation.
In this case, the counter 25 operates as a decimal counter, and therefore the frequency of the obtained pulse signal f becomes higher than that in the case shown in FIG. 3C, which further changes the volume of the emitted alarm sound. In this case, as shown in Figure 3 D, the pulse width of the pulse signal f is 152.6 μsec, and the duty of the pulse signal f is smaller than in the case of Figure 3 C, so the volume also changes due to this. . Further, when the contents of the counter 20 are sequentially changed to "3", "4", ..., "9", pulse signals f shown in Fig. 3 are obtained, and the frequency gradually increases. get high,
The pulse width also changes, and alarm sounds with different volumes are emitted sequentially. Further, when the content of the counter 20 becomes "10", a reset signal RS is output, and the counter 20 is reset and returns to the initial state.
The alarm sound based on the pulse signal f shown in FIG. 3B starts to be emitted again. Therefore, if the user of an electronic watch listens to the alarm sound that is emitted with the volume changing sequentially through the series of operations described above,
It is possible to arbitrarily set the alarm sound at a desired volume.

FIG. 4 shows the pulse width (“H”) of the input pulse signal f in the piezoelectric buzzer circuit 15.
This explains the change in induced voltage depending on the magnitude relationship of signal period). That is, when the pulse width is large as shown in a of FIG. 4, a larger induced voltage is generated than when the pulse width is small as shown in b of FIG.
Therefore, a loud alarm sound is generally emitted.

In the above example, the volume of the alarm sound emitted when the coincidence detection signal is generated is adjusted. Therefore, by changing the contents of the counter 20 one by one and opening the AND gate 26, the volume of the alarm sound can be sequentially changed in the same way and the alarm sound can be heard.

In the above embodiment, the present invention was applied to an electronic watch, but the present invention is not limited to electronic watches, but can be applied to various electronic devices such as a small electronic calculator equipped with a piezoelectric buzzer that can emit a sound by operating keys on a keyboard. is equally applicable.

As explained above, this invention has a configuration in which the frequency of a pulse signal that drives a piezoelectric buzzer is defined by a count base number for counting a reference signal, and the count base number is changed by operating an external operation switch. The frequency of the driving pulse signal is finely changed by operating an external operation switch to adjust the degree of deviation between the frequency and the resonant frequency of the piezoelectric buzzer, and the volume of the piezoelectric buzzer is thereby adjusted, so the operation is simple. You can set the volume of the alarm sound to any value.

[Brief explanation of the drawing]

Fig. 1 is an overall circuit diagram of an embodiment in which the present invention is applied to an electronic watch, Fig. 2 is a detailed circuit diagram of an alarm control circuit and a piezoelectric buzzer circuit, and Fig. 3 is an operation during volume adjustment. Time chart explaining,
FIG. 4 is a time chart explaining the operation of the piezoelectric buzzer circuit. DESCRIPTION OF SYMBOLS 1... Oscillator, 2... Frequency dividing circuit, 3... Time counting circuit, 4... Date counting circuit, 5... Display switching circuit, 6... Display section, 8... Mode counter, 9...
... Setting control circuit, 12 ... Alarm time storage circuit, 13 ... Matching circuit, 14 ... Sound emission control circuit,
15... Piezoelectric buzzer circuit, 20, 24, 25...
Counter, 21, 23...decoder, SW1...
Mode changeover switch, SW2...digit selection switch, SW3...correction switch.

Claims (1)

[Claims] 1. In a piezoelectric buzzer driven by a pulse signal, the means for obtaining the pulse signal is configured with a variable count base and a means for counting a reference signal of a predetermined frequency based on the count base and outputting the pulse signal. At the same time, an external operation switch is provided for changing the count base of the means, and by operating the external operation switch, the count base of the pulse signal output means is changed to determine the degree of deviation of the frequency of the pulse signal from the resonant frequency of the piezoelectric buzzer. A volume control device for a piezoelectric buzzer, characterized in that the volume of the piezoelectric buzzer is adjusted by changing the volume of the piezoelectric buzzer.