JPH0364877B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a dot pattern reduction device.

A dot printer or a dot display is often installed as a terminal device in a computer system. In this case, the same dot pattern is not necessarily given to all devices. That is, for example, there is often a desire to supply a 24x24 dot pattern to a printing device and a 16x16 dot pattern to a display device. This is to set the pattern size appropriately. In this case, memory must be prepared for each size of one pattern (characters such as kanji). However, this is too uneconomical, and therefore, only one dot pattern memory (for each dot pattern) is prepared to match the maximum dot pattern size required by the terminal device. A dot pattern of a desired size is obtained by reducing the maximum dot pattern to an arbitrary size.

Various reduction methods have been proposed for this purpose, and representative examples include: Row/column selection method using rows and columns as processing units; Proportional placement method using each dot as a unit (Both methods include: Journal of the Institute of Electronics and Communication Engineers '77/10Vol.J60-D No.10, page 801~
(See page 808). There are also methods that combine the : method, and methods that preserve the original character shape quality by adding correction processing. However, the above method has some disadvantages in character balance, the above method tends to result in somewhat uneven line widths, and the above methods and (2) have the disadvantage of complicating processing.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a dot pattern reduction device which alleviates the above-mentioned problems, is easy to implement in hardware, and is capable of high-speed processing.

In accordance with the above object, the present invention converts a basic dot pattern represented by an n×n' (n, n' are natural numbers) dot matrix into m×m' (m, m' are natural numbers, n>m, n'>
m') When converting into a reduced dot pattern represented by a dot matrix, the n x n' dot matrix is divided into a plurality of first sub-matrix groups, and the m x m' dot matrix is divided into the same number of second sub-matrix groups. After dividing into submatrix groups, the first
The present invention is characterized in that corresponding sub-matrices in the second sub-matrix group are dot-converted according to a predetermined logical function.

The present invention will be described below with reference to the drawings.

FIG. 1A is 24× to be reduced according to the present invention.
FIG. 3 is a diagram showing an example of a 24-dot pattern. Also,
FIG. 1B is a diagram showing the dot pattern of FIG. 1A reduced to a 16×16 dot pattern in accordance with the present invention. As is clear from these Figures 1A and 1B, the kanji dot pattern "Peng" is
The glyphs are reduced without deteriorating the quality.
This reduction conversion was made possible by dividing the basic dot pattern (Fig. 1A) into the first submatrix group, and dividing the reduced dot pattern (Fig. 1B) into the same number of second submatrix groups. This is because the conversion was done in response to these submatrices. This will be explained diagrammatically. FIG. 2A is a diagram showing an arbitrary first submatrix when the dot pattern in FIG. 1A is divided, and FIG. 2B is a diagram showing an arbitrary second submatrix when the dot pattern in FIG. 1B is divided. It is a diagram. In other words, Figure 2A shows the dot pattern in Figure 1A.
One of the images equally divided into 24×24/3×3 pieces is shown. FIG. 2B is a submatrix obtained by reducing the submatrix of FIG. 2A to 4/9 (not limited to this).
Note that a ₁₁ to _{a 33} of the first sub-matrix each represent basic unit dot data, and b ₁₁ to b ₂₂ of the second sub-matrix also represent reduced unit dot data.

After defining the submatrix group like this,
Transfer the basic dot data of a ₁₁ to _{a 33} to the basic dot data of b ₁₁ to b ₂₂ . In this case, 9 dot data are converted to 4 dot data taking into account the preservation of character shape quality.
Certain rules must also be defined. As this certain rule, in the present invention, the following condition 1 is used.
~5 is determined. That is, the conditions for determining the black and white pattern of the second submatrix by looking at the black and white pattern of the first submatrix are as follows: Condition 1: Preserve the linearity and slope of vertical and horizontal straight lines.

Condition 2: Preserve the straightness and slope of the straight line in the diagonal direction (45°, 135°).

Condition 3: A straight line of 1 dot width must not be thicker than 2 dots wide.

Condition 4: One straight line (thickness doesn't matter) must not become two or more separate straight lines (with a white line in between).

Condition 5: Preserve the continuity of lines (including curves). (Note that a "line" refers to three or more black dots connected together.) Figure 3 is a pattern diagram illustrating various conditions for reduction conversion, and the arrow ↓ in the figure indicates conversion. do. Also, the 3x3 submatrix is the first submatrix (Figure 2A), and the 2x2 submatrix is the second submatrix (Figure 2B).
It is. Also, black dots in the black and white pattern are ×
It is marked. The dotted line x mark 3 in FIG. 3 means either the top or bottom. In addition, the same 5 is × of other adjacent submatrix
is also drawn.

Therefore, the logical function (f) that satisfies the above conditions 1 to 5 is
I will explain about it. The general formula can be expressed as equation (1) using the basic unit dot data a ₁₁ to a ₃₃ as variables.

b ₁₁ = f ₁₁ (a ₁₁ , a ₁₂ , a ₂₁ , a ₂₂ ) b ₁₂ = f ₁₂ (a ₁₂ , a ₁₃ , a ₂₂ , a ₂₃ ) b ₂₁ = f ₂₁ (a ₂₁ , a ₂₂ , a ₃₁ , a ₃₂ ) b ₂₂ = f ₂₂ (a ₂₂ , a ₂₃ , a ₃₂ , a ₃₃ )...(1) Further, the logical function is determined in detail by taking into account the above conditions 1 to 5 as follows.

First, the relationship for satisfying conditions 1, 3, 4, and 5 can be expressed by equation (2) regarding a vertical straight line.

b ₁₁ ←a ₁₁・a ₂₁ +a ₁₂・a ₂₂ b ₁₂ ←a ₁₃・a ₂₃ b ₂₁ ←a ₂₁・a ₃₁ +a ₂₂・a ₃₂ b ₂₂ ←a ₂₃・a ₃₃ …(2) Part (2) In the formula, "." means logical product, "+" means logical sum, and "←" means conversion. For example, dot data _b11 becomes logic "1" (black) in the following case. In other words, both a ₁₁ and a ₂₁ are black, or both a ₁₂ and a ₂₂ are black, or a ₁₁ ~
This is the case when all a ₂₂ are black. Below, b ₁₂ , b ₂₁ and
The same applies to b ₂₂ . However, it is assumed that the vertical line at the center of the first sub-matrix is converted to the left-hand vertical line of the second sub-matrix (the reverse may of course be determined).

Similarly, the equation for satisfying conditions 1, 3, 4, and 5 regarding horizontal straight lines can be expressed as equation (3).

b ₁₁ ←a ₁₁・a ₁₂ +a ₂₁・a ₂₂ b ₁₂ ←a ₁₂・a ₁₃ +a ₂₂・a ₂₃ b ₂₁ ←a ₃₁・a ₃₂ b ₂₂ ←a ₃₂・a ₃₃ …(3) Next, condition 2 The formula to satisfy is (4) and
It can be expressed by equation (5). Equation (4) is an equation to preserve the linearity and slope of a straight line in the diagonal direction within a submatrix, and equation (5) is an equation to preserve the linearity and slope of a straight line in the diagonal direction between adjacent submatrices (45°, 135° ) is a formula for preserving the linearity and slope of the straight line.

b ₁₁ ←a ₁₁・a ₁₂ +a ₁₂・a ₂₁ b ₁₂ ←a ₁₂・a ₂₃ +a ₁₃・a ₂₂ b ₂₁ ←a ₂₁・a ₃₂ +a ₂₂・a ₃₁ b ₂₂ ←a ₂₂・a ₃₃ +a ₂₃・a ₃₂ …(4) b ₁₁ ←a ₁₁ b ₁₂ ←a ₁₃ b ₂₁ ←a ₃₁ b ₂₂ ←a ₃₃ …(5) To summarize the relationships of equations (2) to (5) above, ). Conversely, satisfying Equation (6) means satisfying Conditions 1 to 5 above, which ultimately becomes the final logical function determined by Equation (6).

b ₁₁ = a ₁₁ + a ₁₂ (a ₂₁ + a ₂₂ ) + a ₂₁・a ₂₂ b ₁₂ = a ₁₃ + a ₂₃ (a ₁₂ + a ₂₂ ) b ₂₁ = a ₃₁ + a ₃₂ (a ₂₁ + a ₂₂ ) b ₂₂ = a ₃₃ + a ₂₃ a ₃₂ ...(6) Confirm that this equation (6) satisfies the above equations (2) to (5) for dot data b ₁₁ (the same applies to the others).
Let me prove it.

b ₁₁ ←a ₁₁・a ₂₁ +a ₁₂・a ₂₂ (from equation (2)) b ₁₁ ←a ₁₁・a ₁₂ +a ₂₁・a ₂₂ (from equation (3)) b ₁₁ ←a ₁₁・a ₂₂ +a ₁₂・a ₂₁ (from equation (4)) +)b ₁₁ ←a ₁₁ (from equation (5)) b ₁₁ ←a ₁₁ +a ₁₁・a ₂₁ +a ₁₂・a ₂₂ +a ₁₁・a ₁₂ +a ₂₁・a ₂₂ +a ₁₁・a ₂₂ +a ₁₂・a ₂₁ =a ₁₁ (1+a ₂₁ +a ₁₂ +a ₂₂ ) +a ₁₂ (a ₂₂ +a ₂₁ )+a ₂₁・a ₂₂ =a ₁₁ +a ₁₂ (a ₂₂ +a ₂₁ )+a ₂₁・a ₂₂
(Same as equation (6)) (Note: a ₁₁ (1 + a ₂₁ + a ₁₂ + a ₂₂ ) is a ₁₁ regardless of a ₂₁ , a ₁₂ , and a ₂₂ due to the existence of 1.) In other words, for example, dot data b For ₁₁ , a ₁₁ is black, a ₁₂ is black, and a ₂₁ or
It is considered black when the following conditions are met: a ₂₂ is black, a ₁₂ and a ₂₂ are both black, and other dot data b ₁₂ , b ₂₁ ,
and b ₂₂ are also dot-converted according to the logical function shown in equation (6) above.

Since the logic function described above refers to the sub-matrix having the structure shown in FIGS. 2A and 2B, it can be further generalized and explained as follows. For example, when converting an n×n' dot pattern to an m×m' dot pattern. However, n = n' (square), m = m' (square)
and n=n'=l・(k+1), m=m'=
l・k (n, n′, m, m′, l・k are all natural numbers)
Let us consider the case of In other words, l(k+1)×l(k+1)
The basic dot pattern matrix of l・k×l・
This is a case of converting to a k reduced dot pattern matrix. In this case, the formula for satisfying the above conditions 1 to 5 is the formula (7), where k is an even number of 2 or more.
The formula becomes

In the above equation (7), the suffixes i and j are at arbitrary positions on the matrix (11 to 11 in Figures 2A and 2B).
33 indicates the person in charge). Furthermore, the bracket in the right column of formula (7) defines the positional conditions when setting the left column. The idea is as follows.

First, the relationship for satisfying the above-mentioned conditions 1, 3, 4, and 5 can be expressed by equation (8) regarding a vertical straight line.

This is an attempt to reduce the two straight lines at the center of the basic dot pattern matrix to one, and to map the other lines as they are.

Similarly, the equation for satisfying conditions 1, 3, 4, and 5 regarding horizontal straight lines can be expressed as equation (9).

Next, equations for satisfying condition 2 can be expressed as equations (10) and (11). Equation (10) is an equation to preserve the linearity and slope of the straight line in the diagonal direction within a submatrix, and equation (11) is an equation to preserve the linearity and slope of the straight line in the diagonal direction between adjacent submatrices (45°, 135° ) is a formula for preserving the linearity and slope of the straight line.

Equation (10) attempts to make the corresponding dots on the reduced dot matrix black if two diagonally adjacent dots on the basic dot matrix are both black. In addition, Equation (11) is expressed by the four corners (not only the vertices) on the basic dot matrix
If one dot is black in the whole (with corners cut into triangles), the corresponding dot on the reduced dot matrix will be made black.

Thus, equation (7) becomes equation (8), (9), (10), and (11).
It is a collection of formulas.

Equation (12) shows a modified solution of Equation (7) above. However, similarly to the above, k is an even number of 2 or more.

Furthermore, for odd numbers where k is 3 or more, the (13th)
It can be expressed as the formula.

In addition, the dot pattern of 12 rows and 12 columns is numbered (13).
An example of reduction conversion based on the formula will be described later (with reference to FIG. 6).

Figure 4A is 20× to be reduced according to the present invention.
FIG. 3 is a diagram showing an example of a 15-dot pattern. Also,
FIG. 4B is a diagram showing the dot pattern of FIG. 4A reduced to a 15.times.10 dot pattern in accordance with the present invention. As is clear from these Figures 4A and 4B, the kanji dot pattern "Tomi" is
The glyphs are reduced without deteriorating the quality.
As mentioned above, this reduction conversion method is based on the application of logical functions to a group of submatrices.

FIG. 5A is a diagram showing an arbitrary first submatrix' when the dot pattern in FIG. 4A is divided, and FIG. 5B is a diagram showing an arbitrary second submatrix' when the dot pattern in FIG. 4B is divided. FIG. That is, FIG. 5A shows one of the dot patterns of FIG. 4A divided into 20×15/3×4 dots. FIG. 5B is a submatrix obtained by reducing the submatrix shown in FIG. 5A to 1/2 (but not limited to this). In addition, the first submatrix
c ₁₁ to _{c 43} each represent basic unit dot data, and d ₁₁ to _{d 32} of the second submatrix also represent unit dot data after reduction. In this case, since 12 dot data are converted into 6 dot data taking into consideration preservation of character shape quality, conditions similar to conditions 1 to 5 described above are required.

Condition 1: Preserve the linearity and slope of vertical and horizontal lines.

Condition 2: A straight line with a width of 1 dot must not be thicker than the width of 2 dots.

Condition 3: A single straight line (thickness doesn't matter) cannot be converted into two or more separate straight lines (with white lines in between).

Condition 4: Preserve the continuity of lines (including curves).

(Note that a "line" refers to a line made up of three or more black dots.) Therefore, if we define a formula that satisfies Conditions 1 to 3 regarding a vertical straight line, we get formula (14).

d ₁₁ ←c ₁₁・c ₂₁ +C ₁₂・c ₂₂ d ₁₂ ←c ₁₃・c _{23 d 21 ←c 21・c 31 +c 22 ・ c 32 d 22 ←} c ₂₃・c ₃₃ d ₃₁ ←c ₃₁・c ₄₁ +c ₃₂ c ₄₂ d ₃₂ ←c ₃₃ ·c ₄₃ (14) Also, the equation that satisfies conditions 1 to 3 regarding the horizontal straight line is equation (15).

d ₁₁ ←c ₁₁・c ₁₂ d ₁₂ ←c ₁₂・c ₁₃ d ₂₁ ←c ₂₁・c ₂₂ +c ₃₁・c ₃₂ d ₂₂ ←c ₂₂・c ₂₃ ＋c ₃₂・c ₃₃ d ₃₁ ←c ₄₁・c ₄₂ d ₃₂ ←c ₄₂ ·c ₄₃ (15) Next, the equation that satisfies the continuity of the curve within a submatrix and between different adjacent submatrices, that is, the condition 4 above, is equation (16).

d ₁₁ ←c ₁₁ ＋c ₁₂・c ₂₁ d ₁₂ ←c ₁₃ ＋c ₁₂・c _{23 d 21 ←c 21 ＋ c 31} d ₂₂ ←c ₂₂・c ₃₃ ＋c ₂₃・c ₃₂ d ₃₁ ←c ₄₁ ＋c ₃₁・c ₄₂ d ₃₂ ←c ₄₃ +c ₃₃ ·c ₄₂ (16) Thus, the logical function finally obtained from the above equations (14) to (16) is equation (17).

d ₁₁ = c ₁₁ + c ₁₂ (c ₂₁ + c ₂₂ ) d ₁₂ = c ₁₃ + c ₁₂・c ₂₃ d ₂₁ = c ₂₁ + c ₃₁ + c ₂₂・c ₃₂ d ₂₂ = c ₂₃ (c ₂₂ + c ₃₂ + c ₃₃ ) + c ₃₃ (c ₂₂ + c ₃₂ ) d ₃₁ = c ₄₁ + c ₄₂ (c ₃₁ + c ₃₂ ) d ₃₂ = c ₄₃ + c ₃₃・c ₄₂ …(17) For example, looking at dot pattern d ₁₁ , the following expansion results in the pattern (17) It can be seen that d ₁₁ of the equation is obtained.

d ₁₁ ←c ₁₁・c ₂₁ +c ₁₂・c ₂₂ (from equation (14)) d ₁₁ ←c ₁₁・c ₁₂ (from equation (15)) +) d ₁₁ ←c ₁₁ +c ₁₂ c ₂₁ (from equation (15)) (From formula (16)) d ₁₁ ←c ₁₁・c ₂₁・c ₁₂・c ₂₂ +c ₁₁・c ₁₂ +c ₁₁ +c ₁₂・c ₂₁ =c ₁₁ (c ₂₁ +c ₁₂ +1) +c ₁₂ (c ₂₂ +c ₂₁ ) = c ₁₁ + c ₁₂ (c ₂₂ + c ₂₁ ) (same as equation (17)) Figure 6 shows a dot pattern of 12 rows and 12 columns (the dots marked with an X indicate black dots) in 9 rows.・
In reducing the dot pattern to 9 rows, the 12
Divide the dot pattern of rows and 12 columns into 9 submatrix groups (therefore, each submatrix consists of 4 rows and 4 columns, that is, dot data of a ₁₁ to a ₄₄ ), and calculate the above equation (13). By creating the following logical formula based on the formula and converting each of the above sub-matrices into a second sub-matrix consisting of dot data of 3 rows and 3 columns, that is, _b11 to _b33 , according to the logical formula, the above can be obtained. This figure shows the conversion result when a dot pattern is reduced.

Here, in this example, in the above equation (13),
Considering that i and j that make up b _ij are both 1 to 3, and that n:m=l・(k+1):l・k=12:9, so that k=3, the following The logical formula is established.

That is, b ₁₁ ←a ₁₁ +a ₁₂・a ₂₁ +a ₁₁・a ₂₂ +a ₁₁・a ₂₁ +a ₁₁・a ₁₂ b ₁₂ ←a ₁₃ +a ₁₃・a ₂₂ +a ₁₂・a ₂₃ +a ₁₂・a ₂₂ +a ₁₃・a ₂₃ +a ₁₂・a ₁₃ b ₁₃ ←a ₁₄ + _{a 14}・a ₂₃ +a ₁₄・a 24 +a ₁₃・a ₁₄ b ₂₁ ←a ₂₂・a ₃₁ +a ₂₁・a ₃₂ +a ₂₁・a ₃₁ +a ₂₁・a ₂₂ +a ₃₁・a ₃₂ b ₂₂ ←a ₂₃・a ₃₂ +a ₂₂・a ₃₃ +a ₂₂・a ₃₂ +a ₂₃・a ₃₃ +a ₂₂・a ₂₃ +a ₃₂・a ₃₃ b ₂₃ ←a ₃₄ +a ₂₄・a ₃₃ +a ₂₃・a ₃₄ +a ₂₄・a ₃₄ +a ₂₃・a ₂₄ +a ₃₃・a ₃₄ b ₃₁ ←a ₄₁ +a ₃₂・a ₄₁ +a ₃₁・a ₄₂ +a ₃₁ .a ₄₁ a ₄₁・a ₄₂ b ₃₂ ←a ₄₃ +a ₃₃・a ₄₂ +a ₃₂・a ₄₃ +a ₃₂・a ₄₂ +a ₃₃・a ₄₃ +a ₄₂・a ₄₃ b ₃₃ ←a ₄₄ +a ₃₃・a ₄₄ +a ₃₄・a ₄₄ +a ₄₃・a _44In other words, for example, regarding b ₁₁ above , i=
1, since j=1 and k=3, the above (13)
In the formula, a _ij (i.e. a ₁₁ ) that satisfies the condition in brackets,
a _i,j+1・a _i+1,j (i.e. a ₁₂・a ₂₁ ), a _ij・a _i+1,j+1
(i.e. a ₁₁・a ₂₂ ), a _ij・a _i+1,j (i.e. a ₁₁・a ₂₁ )
Alternatively, when a _ij ·a _i,j+1 (that is, a ₁₁ ·a ₁₂ ) is black, it is considered black, and the above logical formulas are similarly derived for b ₁₂ to b ₃₃ below.

Now, rearranging the above logical formula, b ₁₁ ←a ₁₁ +a ₁₂・a ₂₁ b ₁₂ ←a ₁₃ +a ₁₂・(a ₂₃ +a ₂₂ ) b ₁₃ ←a ₁₄ b ₂₁ ←a ₂₁・a ₃₁ + (a ₂₂ +a ₃₂ )・(a ₂₁ +a ₃₁ ) b ₂₂ ←a ₂₃・a ₃₂ +(a ₂₃ +a ₃₂ )・(a ₂₂ +a ₃₃ ) +a ₂₂・a ₃₃ b ₂₃ ←a ₃₄ +a ₂₄・(a ₂₃ +a ₃₃ ) b ₃₁ ←a ₄₁ +a ₃₁・a ₄₂ b ₃₂ ←a ₄₃ +a ₄₂・(a ₃₂ +a ₃₃ ) b ₃₃ ←a ₄₄ , and each corresponding submatrix divided into the above nine pieces according to the above logical formula By performing dot conversion between the dots, a pattern of extremely high quality, that is, a similar pattern shape (in this example, a straight line shape with an inclination of 45°) as shown in Fig. 6, is guaranteed. Various types of dot pattern reduction can be performed. An example of the configuration of a logic gate circuit that realizes the above logical formula will be described later (Chapter 8).
Figure).

FIG. 7 is a block diagram showing an embodiment of a dot pattern reduction apparatus according to the present invention. In this figure, the dot pattern reduction device 1 can be roughly divided into:
It consists of a basic dot pattern memory 2, a dot pattern converter 3, and a reduced dot pattern memory 4. Among these, the part that characterizes the present invention is the dot pattern converting section 3.

First, the basic dot pattern memory 2 has n rows.
It stores basic dot patterns expressed in a dot matrix of n' columns (n, n' are natural numbers), and the pattern data illustrated in the upper columns of Figures 1A, 4A, and 6, respectively. Remember.

Next, the reduced dot pattern memory 4 has m rows.
It holds a reduced dot pattern represented by a dot matrix of m' columns (m, m' are natural numbers, n > m, n'>m'), and is shown in Figures 1B, 4B, and 6. The pattern data illustrated in each example is held in the lower column.

Now, the dot pattern converter 3 converts the basic dot pattern into the reduced dot pattern, but according to the embodiment of the present invention, the pattern data division 5 and N (not shown in the figure for simplicity) are used. (showing an example where N=4) logic gate circuits 6 and N (showing an example where N=4) second sub-matrix holding memories 7 provided corresponding to each logic gate circuit 6
and a pattern data distribution writing section 8. First, the pattern data dividing section 5 inputs the basic dot pattern from the basic dot pattern memory 2 and divides the basic dot pattern into n×n'/N (N is n×n' and m× The dot matrix is divided into N first sub-matrices each consisting of dots (common divisor of m') and output. Referring to the example in Figure 6,
n x n' = 12 x 12 (= 144), m x m' = 9 x 9 (= 81)
, and N=9 can be set as the common divisor N. In other words, the upper column in Figure 6 (basic dot pattern) is divided into 9 first sub-matrices (9 in the upper column in Figure 6 surrounded by a square with a dotted line).
part). Therefore, each of the first sub-matrices is composed of a dot matrix consisting of 12×12/9 (=16) dots.

The N logic gate circuits 6 have the same logic gate configuration, and each receives the N first sub-matrices divided by the pattern data division section 5 as inputs. According to the example of FIG. 6 described above, nine first sub-matrices are input.

The N second sub-matrix holding memories 7 are
N second sub-matrices are provided corresponding to each of the logic gate circuits 6 and each constitutes a dot matrix consisting of m×m'/N dots. The output of the logic gate circuit 6 is temporarily held. According to the example shown in FIG. 6 above,
Nine logic gate circuits 6 are provided, nine second
A submatrix is constructed (nine square parts surrounded by dotted lines in the lower column of FIG. 6). The nine second sub-matrices are composed of m×m'/N dots, that is, 9×9/9 (=9) dot matrices.

The pattern data distribution writing section 8 writes each of the second sub-matrix data read from each of the second sub-matrix holding memories 7.
Distributing the pattern data forming the submatrix to predetermined positions in the reduced pattern memory 4, and
Write. That is, referring to the bottom column of Figure 6,
For example, the pattern data of the second sub-matrix located at the upper left in the figure is
The pattern data of the second submatrix located at the upper center in the figure is read from the submatrix holding memory 7 and distributed and written to the corresponding positions in the reduced pattern memory 4.
The data is read from the submatrix holding memory 7, distributed and written to the corresponding positions in the reduced pattern memory 4, and in the same way, the pattern data of the 9th submatrix located at the lower right in the same figure is The data is read from the second sub-matrix holding memory 7 and distributed and written to the corresponding positions in the reduced pattern memory 4.

Here, each of the logic gate circuits 6 is connected to each of the second logic gate circuits.
A dot pattern made up of m×m'/N dots forming a sub-matrix has a similar shape to a dot pattern made up of n×n'/N dots forming the corresponding first sub-matrix. Logic gates are constructed based on certain established rules. Regarding certain predetermined rules, various concrete examples have already been explained in detail using mathematical formulas, but the aim is to
As shown in the figure or FIG. 6, the dot pattern of each second sub-matrix is made to be substantially similar to the dot pattern of each corresponding first sub-matrix. An example is shown in FIG.

FIG. 8 is a diagram showing an example of a logic gate circuit, and particularly shows a logic gate circuit 6 that is a concrete embodiment of the example described with reference to FIG. Note that since all logic gate circuits 6 perform dot conversion under the same rules, they all have the same logic gate configuration. In this figure, a ₁₁ to _{a 44} are supplied from the pattern data dividing section 5, and b ₁₁ to b ₃₃ are output to nine second sub-matrix holding memories 7, respectively.
The logic gate sections 11 to 17 in this figure are respectively the sixth
It forms the logical formula explained in the example in the figure,
Corresponds to "1" to "7" below. In addition, “0”
However, it is just a wiring and does not constitute a logic gate section.

“1” b ₁₁ ←a ₁₁ +a ₁₂・a ₂₁ “2” b ₁₂ ←a ₁₃ +a ₁₂・(a ₂₃ +a ₂₂ ) “0” b ₁₃ ←a ₁₄ “3” b ₂₁ ←a ₂₁・a ₃₁ + (a ₂₂ + a ₃₂ )・(a ₂₁ + a ₃₁ ) “4” b ₂₂ ←a ₂₃・a ₃₂ +(a ₂₃ + a ₃₂ )・(a ₂₂ + a ₃₃ )
+a ₂₂・a ₃₃ “5” b ₂₃ ←a ₃₄ +a ₂₄・(a ₂₃ +a ₃₃ ) “6” b ₃₁ ←a ₄₁ +a ₃₁・a ₄₂ “7” b ₃₂ ←a ₄₃ +a ₄₂・(a ₃₂ +a ₃₃ ) “0” b ₃₃ ← a ₄₄ Note that “・” is AND logic, and “+” is OR logic.

As described above, according to the present invention, by using a plurality of the same logical functions (the above-mentioned equation (6) or equation (17)),
Since a plurality of submatrices can be processed in parallel at the same time, it is obvious that high-speed processing can be performed. Furthermore, since reduction conversion is simply applied to the logical function, this can be realized with a logic gate circuit and can be easily implemented in hardware. Furthermore, strict similarity is guaranteed for at least a certain pattern (horizontal straight line or vertical straight line).

As explained above, according to the present invention, a dot pattern reduction device has been realized which overcomes the various drawbacks of the prior art described above, has the advantages of being easy to implement in hardware, and capable of high-speed processing due to parallel simultaneous processing. be done.

[Brief explanation of drawings]

FIG. 1A is 24× to be reduced according to the present invention.
FIG. 1B is a diagram showing an example of a 24-dot pattern, in which the dot pattern of FIG.
Diagram showing the case of reduction to a dot pattern, 2nd A
The figure shows an arbitrary first sub-matrix when the dot pattern in Fig. 1A is divided, Fig. 2B shows an arbitrary second sub-matrix when the dot pattern in Fig. 1B is divided, and the third The figure is a pattern diagram illustrating various conditions for reduction conversion, and Figure 4A is a pattern diagram that should be reduced based on the present invention.
FIG. 4B is a diagram showing an example of a 20×15 dot pattern, in which the dot pattern of FIG.
Figure 5A is a diagram showing the arbitrary first sub-matrix' when the dot pattern in Figure 4A is divided, Figure 5B is the diagram when the dot pattern in Figure 4B is divided. Figure 6 shows the arbitrary second submatrix ' in the case where the dot pattern with 12 rows and 12 columns is divided into 9 submatrices and reduced to a dot pattern with 9 rows and 9 columns. Diagram showing conversion results, 7th
The figure is a block diagram showing an embodiment of the dot pattern reduction device according to the present invention, and FIG. 8 is a diagram showing an example of a logic gate circuit. 1... Dot pattern reduction device, 2... Basic dot pattern memory, 3... Dot pattern converter,
4...Reduced dot pattern memory, 5...Pattern data division section, 6...Logic gate circuit, 7...Second sub-matrix holding memory, 8...Pattern data distribution and writing section,,'...First sub-matrix,,
′...Second submatrix.

Claims (1)

[Scope of Claims] 1. A basic dot pattern memory 2 that stores a basic dot pattern represented by a dot matrix with n rows and n' columns (n and n' are natural numbers); ′ is a natural number, n>m, n′>m′)
In a dot pattern reduction device 1 comprising: a reduced dot pattern memory 4 that holds a reduced dot pattern represented by a dot matrix; and a dot pattern converter 3 that converts the basic dot pattern into the reduced dot pattern. , the dot pattern conversion section 3 inputs the basic dot pattern from the basic dot pattern memory 2, and converts the basic dot patterns into n×n'/N (N is n×n' and m× a pattern data dividing unit 5 which divides and outputs a dot matrix consisting of dots (common divisor of m′) into N first sub-matrices and outputs the same logic gate configuration; N logic gate circuits 6 each receiving the N first sub-matrices divided by the data dividing unit 5; constitutes N second sub-matrices forming a dot matrix consisting of m×m'/N dots, and temporarily holds the output of each corresponding logic gate circuit 6. memory 7; pattern data distribution for distributing and writing pattern data forming each of the second sub-matrices read from each of the second sub-matrix holding memories 7 to predetermined positions in the reduced dot pattern memory 4; and a writing section 8, in which each of the logic gate circuits 6 is connected to each of the second logic gate circuits.
A dot pattern made up of m×m'/N dots forming a sub-matrix has a similar shape to a dot pattern made up of n×n'/N dots forming the corresponding first sub-matrix. A dot pattern reduction device characterized by configuring a logic gate based on certain rules.