JPH0364886B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This is a method for accelerating addition operations, in which multiple inputs consisting of a predetermined number of bits are added to the adder, the intermediate result of the upper bit part is taken out, and the subsequent upper bits are By processing and checking the partial operation in a separate operation unit, the propagation time between the upper bit part and the lower bit part in the addition operation processing of the input can be balanced, and the clock cycle can be shortened. It becomes possible.

[Industrial application field]

The present invention relates to an addition operation circuit including an adder,
For example, the present invention relates to an addition operation processing method for speeding up the adder in a method for converting a virtual address into an execution address using a DAT (dynamic address translation) command.

One method for information processing systems is the virtual storage method, which converts the virtual address into a real address using an arithmetic circuit while executing a DAT (dynamic address translation) command. This method generates the

The above method is called dynamic address translation (hereinafter referred to as DAT), and is executed by a DAT command. That is, conversion to a real address is performed by operating a plurality of inputs consisting of several tens of bits corresponding to a virtual address in an addition operation circuit including an adder, and performing a parity check on the inputs.

Accurate and high-speed conversion is an important factor in speeding up information processing systems.

[Conventional technology]

FIG. 3 is a block diagram for explaining the conventional example, and FIG. 4 is a diagram for explaining the operation of the conventional example.

Figure 3 shows a block diagram of a circuit that converts data into a real address based on data input by a DAT command from a higher-level device or a higher-level program. Register C that stores the specified address
1 and the multiple inputs input when issuing the DAT command to generate predetermined data and parity.Adder 2 normally faces register C1 and has a flag in adder select register ((AS1)7. If it is connected to the adder 2 side, the multiplexer (below
A register D4 stores the output from MPX3 and outputs it to the parity check unit 5. Checks are performed by comparing the parity of the output of the register D4 with the parity predicted from the adder input data. a parity check section 5; and a register E6 that stores the contents of the register D4 checked by the parity check section 5 and outputs it as an address of a predetermined memory (not shown).
and set a flag with the DAT command,
It consists of an adder select register (AS1) 7 that switches the MPX3 to the adder 2 side. still,
In this example, it is assumed that both inputs consist of 32-bit data and 4-bit parity.

FIG. 4 shows an operation diagram when a flag is set in the adder select register (AS1) 7.

That is, when a flag is set in the adder select register (AS1) 7 by the DAT command,
MPX3 switches the connection to the register C1 side to the adder 2 side.

At this time, the adder 2 performs an addition operation on the input, and stores the predetermined data and parity generated as a result in the register D4 through the MPX3 in synchronization with a predetermined clock. When the predetermined data and parity stored in the register D4 are output, the parity check section 5 checks the normality of the predetermined data using the parity, and stores the checked data in the register E6.

[Problem that the invention seeks to solve]

As mentioned above, when calculating the virtual address input to adder 2 and converting it to a real address,
Although it does not take much time to check the result of an operation, since it takes time to propagate a carry during the addition process in adder 2, the lower bits are determined faster and the higher bits are determined later.

On the other hand, the cycle of the clock for setting register D4 must match the longest circuit propagation time, and cannot be shortened to less than the time required for the most significant bit of adder 2 to be determined. In recent devices, which are increasing in number, there is a problem in that there is a limit to the speeding up of addition operation processing.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating an embodiment of the invention.

The block diagram of this embodiment shows the register C1, adder 2, MPX3, register D4, and
Parity check unit 5, register E6, adder select register (AS1) 7, adder select register (AS2) 8 that controls connection switching of MPX12, intermediate result data of adder 2 (for example, upper
16 bits), an arithmetic section 10 that performs an addition operation on the upper bit part stored in the register S9, and a parity check section 11 that performs a parity check on the operation result of the arithmetic section 10. The MPX 12 is connected to the D4 side and is switched to the parity check section 11 side under the control of the adder select register (AS2) 8.

Note that the parity check section 5 is configured to perform a parity check on the data stored in the register E6.

[Effect]

Addition operations are performed on multiple inputs consisting of a predetermined number of bits input to the adder, and the final result is stored in register D for the lower bit part that is determined quickly, and the intermediate result of the upper bit part that is more than the middle of the total number of bits that is determined later. By storing it in register S once, sending it to another arithmetic unit, and performing a parity check with the remaining operations in the next clock cycle, the propagation time between registers can be balanced, and the clock This makes it possible to shorten the cycle.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 and 2.

FIG. 2 shows a diagram explaining the operation in the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

For example, an input consisting of 32 bits is input to the adder 2, and the upper bit part consisting of middle bits and above, which is the intermediate result of the operation, and the output of the carrier read head (CLA) for carry operation are registered. It is taken out and held in S9.

At this time, it is assumed that the DAT command has been issued, a flag has been set in the adder select register (AS1) 7, and the MPX3 has been switched to the adder 2 side. Furthermore, MPX3 is register C1.
32 bits when selecting , 16 when selecting only the lower bit part consisting of the middle bit of adder 2 and below
Only the bits will be selected.

Also, MPX12, which will be described later, selects 32 bits from register D4 when selecting register C1, and concatenates 16 bits from MPX3 and 16 bits from parity check section 11 when selecting the adder 2 side. The selection is made based on the

In the next cycle, the value of the adder select register (AS1) 7 of the previous cycle is shifted, a flag is set in the adder select register (AS2) 8, and the MPX 12 is switched to the parity check section 11 side.

In this cycle, the remaining addition processing for the upper bit portion (16 bits) held in the register S9 is performed by the arithmetic unit 10, and the result checked by the parity check unit 11 is stored in the register E6 via MPX12.

The check in parity check section 11 is MPX.
Only the addition part excluding MPX3 and MPX12 is checked, and then the contents stored in the register E6 are parity checked in the parity check section 5 including MPX3 and MPX12, and then sent out as, for example, a real address.

Also, the timing from when input is input to adder 2 until it is stored in register E6 is the same as in the block diagram shown in FIG. The propagation time between D4 and register S9 is balanced, and the clock cycle itself can be shortened.

〔Effect of the invention〕

According to the present invention as described above, the carry propagation time is determined late in the adder portion, and the situation where cycle time over occurs is eliminated, and the cycle time itself can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the embodiment of the present invention, and FIG. 3 is a block diagram for explaining a conventional example.
FIG. 4 shows diagrams explaining the operation of the conventional example. In the figure, 1 is register C, 2 is adder,
3 and 12 are MPX, 4 is register D, 5 and 11 are parity check sections, 6 is register E, 7 is adder select register (AS1), 8 is adder select register (AS2), 9 is register S, 10 is The arithmetic units are shown respectively.

Claims (1)

[Scope of Claims] 1. An addition operation circuit comprising an adder 2 that performs an addition operation on inputs (,) consisting of a predetermined number of bits, and a parity check section that parity-checks the operation result of the adder 2, wherein the adder 2 storage means 9 for storing the intermediate calculation results for a predetermined upper bit part in the adder 2; means 4 for storing the calculation results for the remaining lower bit parts in the adder 2; a calculation means 10 for performing all calculations; a parity check means 11 for performing a parity check on the calculation results of the calculation means 10; and a high-order part of the checked calculation results from the parity check means 11 and the storage means. Selection means 1 for concatenating and extracting the lower part of the calculation result from 4.
2 is provided, and the calculation for the lower bit part and the calculation for the upper bit part in the adder 2 up to the middle are performed in one cycle, and the remaining calculation for the upper bit part and the calculation result for the upper bit part are performed in one cycle. An addition calculation processing method characterized in that a parity check is performed in the next cycle.