JPH0364958B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS dynamic memory device. 64k-bit dynamic RAM (random access memory), which is said to be the gateway to VLSI, uses a single 5V power supply and uses micro MOS transistors. Here, when miniaturizing MOS transistors, an important issue is channel leakage current in the gate voltage region below the threshold voltage V _th . This is usually called the subthreshold leakage current _ILEAK . This current changes exponentially with respect to the gate voltage V _G as shown below.

I _LEAK ∝exp(V _G ) Therefore, a small amount of noise generated inside the chip or a change in the threshold voltage V _th of the transistor causes a significant change in the leakage current. In particular, in the case of dynamic type circuits, charges are often stored in floating nodes, and this has a significant effect.

In the 64k-bit dynamic RAM mentioned above, a peculiar pause characteristic failure due to this type of leakage current has recently occurred. This is a phenomenon in which the reference potential within the dummy cell decreases as the pause time increases.
Therefore, the reference signal used to sense the memory cell connected to the first accessed word line after the pause ends drops. As a result, "0" data among the memory contents of the cell is sensed incorrectly and destroyed. This inconvenience is an essential problem caused by miniaturization of transistors.
This worsens the dynamic RAM's pause characteristics, making it difficult to manufacture the product.

The present invention was made in view of the above circumstances, and
The generation timing of the reference potential is set so that it is independent of the leakage current allowed in the circuit elements.
It is an object of the present invention to provide a MOS dynamic storage device that improves pause characteristics and can perform reliable memory operations by configuring a circuit that operates immediately after RAM is activated.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In the MOS dynamic RAM shown in FIG. 1, a 1-bit memory cell 10 is composed of a MOS transistor _T1 and a MOS capacitor _C1 , and a plurality of memory cells 10 are arranged in a matrix. Reference numeral 11 denotes a sense amplifier that detects the data stored in these memory cells 10 via the bit line BL when reading data. A word line WL is wired to the gate of the MOS transistor _T1 of each memory cell 10 so as to intersect with the bit line BL. Further, a dummy cell 12 for supplying a reference signal is connected to the terminal end of each bit line BL, and a reference potential generation circuit 13 is attached to these dummy cells 12. This reference potential generation circuit 13 is for writing into the dummy cell 12 a potential that is approximately 1/2 of the maximum potential and minimum potential that can be written into the memory cell 10.

A specific circuit of the reference potential generation circuit 13 and dummy cell 12 is shown in FIG. This dummy cell 12
is a read transistor _T2 whose gate is connected to the read signal φ _DWL and whose drain is connected to the bit line BL, and whose gate is connected to the write signal φ ₃ .
A write transistor T ₃ whose drain is connected to the reference potential generation circuit 13, and one end connected to the sources of both transistors T ₂ and T ₃ ,
It has a dummy cell capacitor C _D whose other end is connected to a power supply V.

Further, the reference potential generation circuit 13 has a gate connected to the signal _φ1 , a source connected to the power supply V _CC , and a drain connected to the node A.
a transistor T ₄ connected to, respectively, a transistor whose gate is connected to the signal φ ₁ , whose source is connected to the ground potential V _SS , and whose drain is connected to the node B, respectively.
T ₅ , a transistor T ₆ whose gate is connected to the signal φ ₂ and whose source and drain are connected to nodes A and B, respectively, and a first capacitive element C _H connected between the node A and the power supply V. and a second capacitive element C _L connected between the node B and the power supply V. The drain of the write transistor T ₃ of the dummy cell 12 is connected to either node A or node B of this circuit 13 .

Next, the operation of the circuit configured as described above will be explained in the third section.
This will be explained with reference to the time chart shown in the figure. The pause is performed in an inactive area for the memory. During this pause, the external drive signals that drive the memory are at high level, as shown in the figure, and the signals φ ₁ and φ ₃
is at a boosted potential higher than the supply voltage V _CC . However, the signals φ ₁ and φ ₃ are in the entire period (inactive region)
Although it is desirable that the voltage be at the boosted potential throughout the entire period, it is sufficient if the voltage is at the boosted potential during a part of the period, if not the entire period. Further, at this time, the signals φ ₂ and φ _DWL are at the ground potential V _SS . During this pause period (inactive region), the above-mentioned signals φ ₁ and φ ₃ cause the transistors T ₄ and T ₃ to turn on, so that the power supply potential V _{CC is written to the nodes A and C, and the power supply potential V CC} is written to the nodes B and D. Ground potential V _SS is written in transistors T ₅ and T ₃ .
In other words, even if there is leakage from the circuit elements of the dummy cell 12 and the reference potential generation circuit 13 during the pause period, the node A, regardless of the leakage current,
Each level will be held in B, C, and D.

Next, when entering the active area for the memory, the third
As shown in the figure, the external drive signal for driving the memory is at a low level, and first the signal φ ₁ falls to the ground potential V _SS to turn off transistors T ₄ and T ₅ , thereby turning off the node A , B are each potential
Disconnect from V _CC and V _SS . Starting here, node A,
B, C, and D are in a floating state. Next, the signal φ ₂ becomes high potential, which causes the transistor to
_T6 turns on, shorting nodes A and C and nodes B and D. At this time, the charges stored in nodes A and C flow into nodes B and D, and each node A,
The potentials of B, C, and D become equal, and a reference potential is generated. Next, the signal φ ₃ falls from the high potential to the ground potential to turn off the transistor T ₃ , thereby confining the reference potential generated at the nodes C and D within the dummy cell 12 . After this is completed, the read signal φ _DWL rises to the boosted potential level, so
Transistor _T2 turns on and applies the reference potential to bit line BL as a reference signal. That is, in the reference potential generation circuit 13, the maximum potential that can be written into the memory cell 10 described above is written into the first capacitive element _CH during the inactive period, the minimum potential is written into the second capacitive element _CL during the inactive period, and the maximum potential that can be written into the memory cell 10 is written into the first capacitive element C At the beginning of the period, the electric charges of the first and second capacitive elements C _H and C _L are divided to obtain a potential of approximately 1/2, and this is generated as a reference potential. Therefore, in this circuit 13, the reference potential is generated after the external drive signal is activated (after the signal generation is completed), within the active region for the memory, and completed before the memory cell 10 is accessed. There will be.

FIG. 4 shows an operation time chart according to another embodiment of the present invention. In this case, the signals φ ₁ ,
Boosting of _φ3 is performed after entering the active region. In this way, the reference potential generation circuit can be made resistant to fluctuations in the power supply potential during the pause period.
In actual case, nodes A, B, C, and D are in a floating state and are therefore affected by the movement of signals φ ₁ , φ ₂ , and φ ₃ . When designing in consideration of this influence, it is better to make the first capacitive element C _H larger than the second capacitive element C _L.

In the embodiment described above, the potential generation circuit 13 is formed in such a configuration that the storage capacitance of the dummy cell 12 is added to the first and second capacitive elements C _H and _CL . The storage capacity of this dummy cell 12 and the storage capacity of the memory cell 10 may be designed to be approximately equal.
Further, in the above embodiment, the dummy cell 12 is placed at the end of the bit line BL for convenience, but it is not necessarily limited to this, and may be placed between the sense amplifier 11 and the memory cell 10, or at any other position. Furthermore, in the above embodiment, one reference potential generation circuit 13 is arranged for every two dummy cells, but it is also possible to arrange one for every four dummy cells, and one reference potential generation circuit 13 is arranged for every dummy cell of the entire chip. You may place them separately. This combination is a matter of design selection based on effective use of chip area, balance of power consumption, and other factors. Further, in the above embodiment, an open bit line method is described in which the bit lines BL are opened on both sides of the sense amplifier 11, but this may be a folded bit line method in which the bit lines BL are opened in the same direction.

A significant advantage obtained by the present invention is for the manufacture of dynamic RAM. In other words, conventionally, the dummy cell had to hold the reference potential during the pause period, and if there was even a slight leak, the reference potential would fluctuate, so strict measures were taken to prevent leaks during the manufacturing process. Quality control is required. However, according to the present invention, since the generation of the reference potential is made independent of the pause period, the manufacturing margin is greatly expanded.
Specifically, the threshold voltage of transistors T ₄ and T ₅
Control of V _th , channel length, etc. can be made more relaxed, thereby making it possible to reduce manufacturing costs. Also,
The manufacturing yield can be significantly improved, and it is expected that the product yield will be approximately doubled. In addition, the method of writing to the dummy cell by making the dummy cell capacity equal to the memory cell capacity and using the intermediate potential as a reference potential has been thought to be advantageous for reducing manufacturing yield due to IC pattern processing accuracy. . However, as mentioned above, it had the drawback of being weak against poses. By applying the present invention, since the potential is generated separately from the pause period, it is possible to make better use of the above-mentioned advantages, and it is possible to create products that are resistant to variations in pattern processing, resulting in improved product yield. This can contribute to reducing costs.

Another great effect of the present invention is on the characteristics of RAM. First of all, since the pose characteristics can be greatly improved, the performance of the product can be improved, thereby increasing the added value of the product.
Second, since the voltage is written at an intermediate potential between the cell's maximum and minimum write voltages, it is resistant to SLEW or BUMP phenomena, where the power supply is different in write mode and read mode. It will have characteristics.

As explained above, according to the present invention, the circuit configuration is such that the generation timing of the reference potential is immediately after the activation of the RAM so that it has no relation to the leakage current allowed in the circuit element, so the pause characteristic It is possible to provide a MOS dynamic storage device that can improve memory performance and perform reliable memory operations.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a MOS dynamic memory device according to an embodiment of the present invention, FIG. 2 is a detailed circuit configuration diagram of the reference potential generation circuit and dummy cell shown in FIG. 1, and FIG. FIG. 4 is an operation time chart for explaining the operation of the circuit according to another embodiment of the present invention. 10...Memory cell, 11...Sense amplifier,
12...Dummy cell, 13...Reference potential generation circuit, BL...Bit line, WL...Word line, T1 _{to T6 ...} Transistor, _C1 ...MOS capacitor, C _D ...Dummy cell capacitor, C _H ... ...first capacitive element, C _L ...second capacitive element.

Claims (1)

[Scope of Claims] 1. A memory section in which a plurality of 1-bit memory cells each including a memory cell MOS transistor and a memory cell MOS capacitor and storing data are arranged in a matrix, and data is read from each memory cell in the memory section. a sense amplifier that detects the data to be detected; and a first sense amplifier connected between a predetermined potential and the first node.
a capacitive element, a second capacitive element connected between the predetermined potential and a second node, a first MOS transistor whose source is connected to the maximum write potential and whose drain is connected to the first node, whose source is connected to the minimum write potential; a second MOS transistor whose drain is connected to the second node; and a third MOS transistor whose source and drain are connected between the first node and the second node; a reference potential generation circuit that generates a reference potential equivalent to approximately half of the above, a dummy cell capacitor, a fourth MOS transistor whose source and drain are connected between the dummy cell capacitor and the first node or the second node, and the dummy cell. It has a fifth MOS transistor whose source and drain are connected between the capacitor and the sense amplifier, and temporarily stores the reference potential generated by the reference potential generation circuit and transmitted via the fourth MOS transistor. , and a dummy cell that supplies the sense amplifier as a reference signal via the fifth MOS transistor, and when data is read from each memory cell of the memory section, the first MOS transistor and the first MOS transistor are connected to each other.
The 2MOS transistor and the fourth MOS transistor are made conductive, and the maximum potential and the minimum potential are written in the first and second capacitive elements, respectively, and then the first MOS transistor and the fourth MOS transistor are made conductive.
The 2MOS transistor is made non-conductive to separate the first node and the second node from the maximum potential and the minimum potential, respectively, and then the third MOS transistor is made conductive to separate the first node and the second node from the maximum potential and the minimum potential, respectively.
The reference potential is generated at the node, and then the fourth MOS transistor is made non-conductive to accumulate the reference potential in the dummy cell capacitor, and then the fifth MOS transistor is made conductive so that the reference potential is accumulated in the dummy cell capacitor. The reference potential is transmitted to the sense amplifier, and the generation of the reference potential is completed after generation of the external drive signal and before the memory cell is accessed.
MOS dynamic storage device. 2. Claims characterized in that a difference is provided between the capacitance values of the first capacitive element and the second capacitive element in the reference potential generation circuit, and the capacitance of the first capacitive element is made larger than the capacitance of the second capacitive element. As stated in paragraph 1
MOS dynamic storage device. 3 For the dummy cell capacitor and the memory cell
MOS according to claim 1, characterized in that the capacitance values of the MOS capacitors are made substantially equal.
Dynamic storage device. 4. When the first MOS transistor is made conductive to write the maximum potential to the first capacitive element, a drive signal supplied to the gate of the first MOS transistor is set to a higher potential than the write maximum potential. A MOS dynamic storage device according to claim 1.