JPH0364973B2 - - Google Patents
Info
- Publication number
- JPH0364973B2 JPH0364973B2 JP5429782A JP5429782A JPH0364973B2 JP H0364973 B2 JPH0364973 B2 JP H0364973B2 JP 5429782 A JP5429782 A JP 5429782A JP 5429782 A JP5429782 A JP 5429782A JP H0364973 B2 JPH0364973 B2 JP H0364973B2
- Authority
- JP
- Japan
- Prior art keywords
- time
- capacitor
- comparator
- voltage
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 26
- 230000003111 delayed effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Description
【発明の詳細な説明】
本発明は、オフ遅延回路に関するもので、特に
外部の有接点スイツチによりオフ遅延回路のリセ
ツトおよび遅延開始を行う形式の改善に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an off-delay circuit, and more particularly to an improvement in the manner in which the off-delay circuit is reset and delayed by an external contact switch.
従来のものは、第1図に示すように、電源1,
2間にコンパレータ10を接続し、基準電圧端子
11に分圧抵抗8,9を接続し、入力電圧端子1
2に、限時抵抗6の一端を接続すると共に限時コ
ンデンサ5と限時抵抗7とで放電回路を形成し、
抵抗4と有接点スイツチ3を介して電源1に接続
し、コンパレータ10の出力端子には分圧抵抗1
6,17を接続し、かつトランジスタ18のベー
スに接続し、出力リレー19と共に電源1,2間
に接続したものである。 In the conventional type, as shown in Fig. 1, the power supply 1,
A comparator 10 is connected between the input voltage terminal 1 and the voltage dividing resistors 8 and 9 are connected to the reference voltage terminal 11.
2, connect one end of the time-limiting resistor 6, and form a discharge circuit with the time-limiting capacitor 5 and the time-limiting resistor 7,
It is connected to the power supply 1 through a resistor 4 and a contact switch 3, and a voltage dividing resistor 1 is connected to the output terminal of the comparator 10.
6 and 17 are connected to each other, and connected to the base of a transistor 18, and connected together with an output relay 19 between power supplies 1 and 2.
かかる構成の従来の遅延回路にあつては、電源
1,2が印加されると、基準電圧端子の電圧V1
>入力電圧端子の電圧V2の関係であるので、出
力端子13はLレベルなので出力リレー19は動
作しない。次にリセツトのため有接点スイツチ3
を閉路すると抵抗4を介して限時コンデンサ5が
充電され、電圧V1<電圧V2に達するとコンパレ
ータ10の出力端子13がHレベルに反転し、ト
ランジスタ18がオンして出力リレー19が動作
する。そして遅延動作開始のため有接点スイツチ
3を開路すると、限時コンデンサ5の電荷が限時
抵抗6,7によつて所定時間充電し、再び電圧
V1>電圧V2になつたとき出力リレー19が遅延
復帰動作をするものである。ところでこの放電時
間T1は当所の充電々荷量により決定されるもの
であつて、第2図に示す電圧曲線Aは正常な場合
でその放電時間T1が得られるものであるが、有
接点スイツチは有接点であるからその接触抵抗が
変動しやすく、特に抵抗4は限時コンデンサ5へ
の字電を急速に行なわせるため低抵抗値に設定し
てあるから有接点スイツチ3の接触抵抗値の増大
が限時コンデンサ5の当初充電々荷量を低下させ
るように作用し、第2図の電圧曲線Bのように低
下し、その放電時間T2も短縮されることとなつ
て、結局正確なオフ遅延時間が得られない欠点が
あつた。 In the conventional delay circuit having such a configuration, when the power supplies 1 and 2 are applied, the voltage at the reference voltage terminal V 1
>The voltage at the input voltage terminal is V2 , so the output terminal 13 is at L level, so the output relay 19 does not operate. Next, turn on contact switch 3 to reset.
When the circuit is closed, the time-limiting capacitor 5 is charged via the resistor 4, and when the voltage V 1 <voltage V 2 is reached, the output terminal 13 of the comparator 10 is inverted to H level, the transistor 18 is turned on, and the output relay 19 is operated. . Then, when the contact switch 3 is opened to start the delay operation, the electric charge in the time-limiting capacitor 5 is charged by the time-limiting resistors 6 and 7 for a predetermined period of time, and the voltage increases again.
When V 1 >voltage V 2 , the output relay 19 performs a delayed recovery operation. By the way, this discharge time T 1 is determined by the amount of charge at our facility, and the voltage curve A shown in Figure 2 shows the discharge time T 1 obtained in a normal case. Since the switch is a contact point, its contact resistance is likely to fluctuate.In particular, the resistance value of the resistor 4 is set to a low value in order to quickly conduct electricity to the time-limited capacitor 5, so the contact resistance value of the contact switch 3 is The increase acts to reduce the initial charge amount of the time-limiting capacitor 5, and the voltage decreases as shown in the voltage curve B in Fig. 2, and the discharge time T2 is also shortened. There was a drawback that delay time could not be obtained.
本発明は上記従来の問題に着目してなされたも
ので、以下第3図を参照して本発明の実施例を説
明する。 The present invention has been made in view of the above-mentioned conventional problems, and an embodiment of the present invention will be described below with reference to FIG.
電源E1,E2間に限時抵抗Rtと限時コンデンサ
Ctを直列接続し、限時コンデンサCtを電圧比較
用の半導体集積回路であるコンパレータICの入
力電圧端子2に接続してあり、電圧E1,E2間の
分圧抵抗R1,R2の中点を基準電圧端子1に接続
し、同コンパレータICの出力端子3は出力リレ
ーRyを介して電源E1に接続してある。 A time-limiting resistor Rt and a time-limiting capacitor are connected between power supplies E1 and E2.
Ct are connected in series, and the time-limiting capacitor Ct is connected to the input voltage terminal 2 of a comparator IC , which is a semiconductor integrated circuit for voltage comparison . The point is connected to the reference voltage terminal 1, and the output terminal 3 of the comparator IC is connected to the power source E1 via the output relay Ry.
限時コンデンサCtへの充分な充電々荷を供給
するトランジスタQ2と抵抗R6を限時抵抗Rtに並
列接続し、同トランジスタQ2のベースは、抵抗
R5を介して電源E1へ、更にコンデンサC1を介し
て電源E2に接続してあり、遅延リセツト及び限
時開始用の有接点スイツチS(例えばマイクロス
イツチその他のもの)を保護用の抵抗R7を介し
て限時コンデンサCtに並列接続してある。 A transistor Q 2 that supplies sufficient charge to the time-limiting capacitor Ct and a resistor R 6 are connected in parallel to the time-limiting resistor Rt, and the base of the transistor Q 2 is connected to the resistor
It is connected to the power supply E 1 through R 5 and to the power supply E 2 through a capacitor C 1 , and is connected to a resistor for protecting the contact switch S (e.g. micro switch or other) for delayed reset and timed start. It is connected in parallel to the time-limiting capacitor Ct via R7 .
このように構成したオフ遅延回路は、まず電源
E1,E2間に電源が印加されているもので、コン
パレータICの基準電圧端子1の電圧V1が上昇す
ると共に抵抗R5,トランジスタQ2のエミツタ、
ベース、コンデンサC1を通じてトランジスタQ2
のベース電流が流れトランジスタQ2の増巾効果
によつて、抵抗R6、トランジスタQ2のエミツタ、
コレクタを通して、限時コンデンCtへ充電々流
が流れて入力電圧端子2の電圧V2も上昇し、電
圧V2>電圧V1となるまで十分な充電が行われる
よう、抵抗R5、コンデンサC1の値が決定して
ある。そして電圧V2の方が大となるからコンパ
レータICの出力端子3はHレベルとなつて、出
力リレーRyは動作しない。 The off-delay circuit configured in this way is first connected to the power supply.
A power supply is applied between E 1 and E 2 , and as the voltage V 1 at the reference voltage terminal 1 of the comparator IC rises, the resistor R 5 , the emitter of the transistor Q 2 ,
Transistor Q 2 through the base, capacitor C 1
The base current flows through the resistor R6 , the emitter of transistor Q2 ,
A charging current flows to the time-limited capacitor Ct through the collector, and the voltage V 2 at the input voltage terminal 2 also rises, and the resistor R5 and capacitor C 1 are connected so that sufficient charging is performed until the voltage V 2 >voltage V 1 . The value has been determined. Since the voltage V2 is higher, the output terminal 3 of the comparator IC becomes H level, and the output relay Ry does not operate.
次にリセツト即ち出力リレーRyを外部端子か
ら投入状態に駆動するため、有接点スイツチSを
閉路すると限時コンデンサCtの充電々荷は、保
護用なので低抵抗値の抵抗R7を介して有接点ス
イツチSにより速やかに放電され、電圧V2<電
圧V1となり、第4図タイムチヤートに示すよう
にコンパレータICの出力端子3がLレベルに反
転して出力リレーRyが動作する。ここでもし有
接点スイツチSの接触抵抗が増加していたとして
も出力リレーRyの投入時間が遅れることはあつ
ても、正確さを要求される後述のオフ遅延時間精
度には、有接点スイツチSの閉路時間が充分ある
用途においては何等影響しない。 Next, in order to reset the output relay Ry to the closed state from the external terminal, when the contact switch S is closed, the charge of the time-limiting capacitor Ct is transferred to the contact switch via the low-resistance resistor R7 since it is for protection. The voltage V 2 becomes less than the voltage V 1 , and as shown in the time chart of FIG. 4, the output terminal 3 of the comparator IC is inverted to the L level and the output relay Ry is activated. Here, even if the contact resistance of the contact switch S increases, the turn-on time of the output relay Ry may be delayed; There is no effect in applications where there is sufficient closing time.
そして限時を開始するため、有接点スイツチS
を再び開路すると、トランジスタQ2のベース電
流はコンデンサC1が充電完了されているため流
れずトランジスタQ2はオフ状態なので、限時抵
抗Rtのみを介して限時コンデンサCtに充電され、
所定の限時々間が経過後に、電圧V2>電圧V1と
なり、出力リレーRyはオフ遅延動作を終了して
復帰する。このようにオフ遅延時間は、有接点ス
イツチSの接触抵抗の変化には全く影響を受けな
いこととなつて、正確なオフ遅延時間tが得られ
る。 Then, in order to start the time limit, the contact switch S
When the circuit is opened again, the base current of transistor Q 2 does not flow because capacitor C 1 has been fully charged, and transistor Q 2 is in the off state, so the time-limiting capacitor Ct is charged only through the time-limiting resistor Rt.
After a predetermined period of time has elapsed, the voltage V 2 becomes greater than the voltage V 1 and the output relay Ry completes the off-delay operation and returns. In this way, the OFF delay time is completely unaffected by changes in the contact resistance of the contact switch S, and an accurate OFF delay time t can be obtained.
本発明は以上説明した構成としたことにより、
リセツト動作時に有接点スイツチSを閉路し、限
時開始時に開路するものであるから、例え有接点
スイツチSの接触抵抗に変動があつたとしても、
オフ遅延動作時には開路させるものであるから全
く無関係なものとなるから、常に正確なオフ遅延
時間が得られるのである。 By having the configuration described above, the present invention has the following features:
Since the contact switch S is closed during the reset operation and opened when the time limit starts, even if the contact resistance of the contact switch S fluctuates,
Since the circuit is opened during the off-delay operation, it is completely irrelevant, so that an accurate off-delay time can always be obtained.
第1図乃至第2図は従来例を示し、第1図は回
路図、第2図は充放電曲線図である。第3図乃至
第4図は本発明の実施例を示し、第3図は回路
図、第4図はそのタイムチヤート図である。
E1,E2……電源、Rt……限時抵抗、Ct……限
時コンデンサ、IC……コンパレータ、R1,R2…
…分圧抵抗、1……基準電圧端子、2……入力電
圧端子、3……出力端子、R5,R6,R7……抵抗、
C1……コンデンサ、S……有接点スイツチ、Q2
……トランジスタ。
1 and 2 show a conventional example, with FIG. 1 being a circuit diagram and FIG. 2 being a charge/discharge curve diagram. 3 and 4 show an embodiment of the present invention, with FIG. 3 being a circuit diagram and FIG. 4 being a time chart thereof. E 1 , E 2 ... power supply, Rt ... time limit resistor, Ct ... time limit capacitor, IC ... comparator, R 1 , R 2 ...
...Voltage dividing resistor, 1...Reference voltage terminal, 2...Input voltage terminal, 3...Output terminal, R5 , R6 , R7 ...Resistor,
C 1 ... Capacitor, S ... Contact switch, Q 2
...transistor.
Claims (1)
し、基準電圧端子に分圧抵抗を接続したコンパレ
ータの入力電圧端子に前記限時コンデンサを接続
し、リセツト時に閉路し限時開始時に再開路する
有接点スイツチを前記限時コンデンサに並列接続
し、前記有接点スイツチの閉路前に限時抵抗を短
絡して限時コンデンサをコンパレータの基準電圧
より高く急速充電するトランジスタを限時抵抗に
並列接続するとともに前記限時コンデンサの充電
完了後は前記トランジスタをオフ状態とするコン
デンサをベースに接続し、前記コンパレータの出
力端子と電源間に出力リレーを接続してなり、前
記有接点スイツチを閉路により限時コンデンサを
急速放電してコンパレータを反転させて出力リレ
ーを投入しかつ再開路による限時コンデンサの充
電完了に伴うコンパレータの再反転により出力リ
レーを遅延復帰させてなることを特徴とするオフ
遅延回路。1 Connect a time limit resistor and a time limit capacitor in series to the power supply, connect the time limit capacitor to the input voltage terminal of a comparator with a voltage dividing resistor connected to the reference voltage terminal, and create a contact switch that closes at reset and reopens at time limit start. A transistor is connected in parallel to the time-limiting capacitor and quickly charges the time-limiting capacitor to a voltage higher than the reference voltage of the comparator by short-circuiting the time-limiting resistor before closing the contact switch, and after the charging of the time-limiting capacitor is completed. is connected to the base of a capacitor that turns off the transistor, and an output relay is connected between the output terminal of the comparator and the power supply, and the contact switch is closed to quickly discharge the time-limited capacitor and reverse the comparator. The off-delay circuit is characterized in that the output relay is turned on and the output relay is returned with a delay by re-inverting the comparator upon completion of charging of the time-limited capacitor by restarting the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5429782A JPS58172834A (en) | 1982-03-31 | 1982-03-31 | Off delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5429782A JPS58172834A (en) | 1982-03-31 | 1982-03-31 | Off delay circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58172834A JPS58172834A (en) | 1983-10-11 |
| JPH0364973B2 true JPH0364973B2 (en) | 1991-10-09 |
Family
ID=12966630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5429782A Granted JPS58172834A (en) | 1982-03-31 | 1982-03-31 | Off delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58172834A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0740437B2 (en) * | 1986-11-19 | 1995-05-01 | 日本電気株式会社 | Delay circuit |
-
1982
- 1982-03-31 JP JP5429782A patent/JPS58172834A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58172834A (en) | 1983-10-11 |
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