JPH036599B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to reducing the access time of memory cells in random access memories. The preferred embodiment described herein is for a circuit comprised of 64K CMOS static RAM.

Some of the delay in reading a memory cell in a static RAM includes cell selection time. This cell selection time corresponds to the time required to operate the address buffer and decoder, and the subsequent word line delay.
The subsequent delay is the cell read time. This cell read time corresponds to the time required to operate the sense amplifier and output buffer. In a 16K static RAM, the defined cell selection time is approximately 68% of the total delay time, and the cell read time is the remaining 32%.

As static RAM density increases,
The total access time occupies a large proportion of the cell read time. Considering 65K static RAM, the cell selection time is approximately 58% of the total delay time.
%, and the cell readout time is approximately 42% of the total delay time.
It is. The reason why the cell read time is such a high percentage of the total delay time is that the memory cell transistors are weaker, the bit line signals are smaller, and there is a larger bit line to bit line capacitance.

The purpose of the invention is to shorten the cell readout time.

The present invention provides a bit line load for a semiconductor memory comprising a bit line clamp circuit coupled to the bit line and a substantially constant current source coupled to the bit line and the bit line clamp circuit.

The invention also relates to a semiconductor memory including such a bit line load.

In one embodiment, column sense amplifiers are also provided that use switched compensated current sources to maximize gain and improve data line level stability. Separate read and data paths are added. Sneak capacity is added to reduce the capacity due to unselected columns.
capacitance).

Hereinafter, the present invention will be explained in detail with reference to the drawings.

Referring first to FIG. 1, a column circuit for a typical memory cell of the bistable flip-flop type is shown. Basically, FIG. 1 shows a bit line load circuit 10, a memory cell 12, and bit lines 14, 16.
, word line 18 for the row, and data write line 2
0, 22, separate data read lines 24, 26,
A column amplifier 40 is shown. A column includes a plurality of memory cells, and a plurality of such columns are provided with such circuitry in memory. However, as described later, the current source load is shared.

A bit line circuit 10 is associated with the memory cell 12 to allow a differential voltage to quickly develop on the bit lines 14, 16 and to stabilize the cell by preventing the bit line voltage from dropping too low. To be able to maintain the degree. Also,
Circuit 10 (with reference voltage V _R1 ) provides high voltage gain independent of transistor characteristics. In circuit 10, the clamp formed by transistor 30 is connected to P-channel transistor 32.
cooperates with a current source formed by and a reference voltage V _R1 . The sources of N-channel transistor 30 and P-channel transistor 32 are connected to bit line 14.
and its drain is coupled to an operating voltage source. In this case the operating voltage source is V _CC at 5.0 volts. The gate of transistor 30 is coupled to voltage source V _CC . The gate of transistor 32 is coupled to reference voltage V _R1 . This reference voltage is a variable voltage generated on the chip. The circuit that generates the reference voltage V _R1 is an N-channel circuit that occurs in CMOS.
Compensates for changes in transistors and P-channel transistors. This will be explained with reference to FIG. However, the reference voltage V _R1 is a DC voltage that changes depending on the ambient conditions. Reference voltage V _R1
provides a voltage that provides a relatively constant current source to the bit line, depending on the parameters of the transistor. Circuit 10 each having a current source and a clamp
In this embodiment, each of the two bit lines 14, 16
provided for.

P-channel transistors are not generally used as current sources in the semiconductor field. Instead, N-channel or depletion transistors are used with each gate coupled to a bit line. Such a connection results in little clamping and no tracking. The present invention combines the features of bit wire clamping with tracking to provide an improved device.

To read the memory cell, a transistor 3 whose source-drain path is coupled to the bit line pair
An equalization signal is applied which causes 4 to become conductive. This equalizes the bit line to about 4.0 volts. At this time,
P-channel transistor 32 with respect to circuit 10
is conductive and the threshold voltage of transistor 30 is approximately 1.5 volts.
0 is configured, the clamp configured by transistor 30 is not yet activated. Therefore, in this configuration, transistor 30 will not become conductive until approximately 1.5 volts below bit line V _CC . Therefore, while the gate and source of transistor 30 are high, the bit line is made equal to approximately 4 volts, and 4 volts does not provide an adequate voltage transition for transistor 30; does not become conductive. Therefore, at this time, transistor 3
2 becomes a substantially constant current source relatively independent of voltage. Memory cell 12 modulates the current flowing through one bit line. Since this current source provides a nearly constant current, the bit line voltage must vary significantly. As the bit line voltage changes, the voltage difference between bit lines 14 and 16 is read. A delta of about 0.1 volt is sufficient to read the cell.

When the balanced clock is turned off, one bit line moves toward V _CC as a result of the P-channel transistor on that bit line being conductive. The other bit line moves towards ground level for operation of memory cell 12. As the voltage on the bit line drops toward ground, at some point there is a sufficient voltage difference to cause clamp transistor 30 to become conductive. This occurs when the voltage on the bit line is approximately 3.5 volts. The memory cell drops the bit line to about 3 volts, but the clamp prevents the bit line voltage from dropping below that. (The cell has been read before this happens.)
By preventing the voltage on the bit line from dropping too low, the risk of sudden changes in the stored contents of the memory cell is greatly reduced.

The lower part of FIG. 1 shows the column read and write circuits. As you can see from this diagram, write line 2
0 and 22 are separate from the readout lines 24 and 26. In this figure, the column selection signal is Yn. When this signal Yn is high, a column is selected for reading and writing. Differential column amplifier 40 is shown to include input transistors 42, 44, and N-channel transistor 46 and P-channel transistors 48, 50, which serve as current sources for these input transistors. The gates of transistors 48 and 50 are connected to a second reference voltage.
Connected to V _R2 . The transistors 48 and 50 are
It functions as a nearly ideal current source load that supplies a nearly constant current independent of the voltage to the read line.

Transistors 52 and 54 are switching transistors that function as control circuits. These transistors connect the gate of transistor 46 to
Switches between voltage V _R3 and ground potential depending on the state of signal Yn. When the signal Yn is at a low level, the gate of the transistor 46 is at a low level because the transistor 54 conducts the path to ground. Furthermore, when the signal Yn is at a low level, the transistor 56 also becomes conductive and the circuit point 60 becomes conductive.
Pulled down to within one threshold of V _CC . Transistor 56 is a clamp transistor that holds node 60 at V _CC minus V _to when signal Yn is low.

While reading from the cell, the data write line 20
and its complementary data write line 22 are held at voltage V _CC . The bit line voltage drives column sense amplifier 40. Thereby, the data readout lines 24, 2
An output signal is generated at 6. Their output signals are detected by a main readout amplifier (not shown).

To write to memory cell 12, data write line 2 is pulled down by a driver circuit that pulls down the selected bit line through transistor 62 or 64.
0 or 22 is pulled close to ground potential.

P-channel transistors 48, 50 for data read lines 24, 26 are transistors 4
It is shared by several columns each having a column amplifier device as indicated by 2, 44, 46, 52, 54, 56.

The circuit of FIG. 1 is a P-channel transistor 66.
Also included. A column selection signal Yn is applied to the gate of this transistor. This transistor is for stray paths. In large capacity RAMs, data read lines 24, 26 are coupled to transistors 42, 444 in each column. Consider a column other than the column containing the cell to be read. For each of those selected columns, when the word line 18 for the addressed memory cell goes high, it not only couples the addressed memory cell to its bit line, but also connects the addressed memory cell to its bit line. Coupling the memory to each corresponding bit line. As a result, each column along word line 18 has a bit line 14 or 16 at a voltage of _VCC . The bit lines 14, 16 correspond to the corresponding transistors 42, 4.
Connected to gate 4. As a result, in each unselected column, the gate of transistor 42 or 46 will be at voltage V _CC . Therefore, the data read line 24 or 26 is connected to the voltage V _CC minus V _to
(V _to represents the threshold of an N-channel transistor), transistor 42 or 46 becomes conductive. This occurs for each column that is not selected. As a result, the data read line 24 or 2
6 is coupled to node 60 in all unselected columns, which significantly increases the capacitive load on the data read lines and reduces the speed of the RAM.

To solve this problem, each column includes a transistor 66. The gate-drain path of this transistor couples bit lines 14,16. The gate of transistor 66 is coupled to column select signal Yn. When a column is selected, its signal Yn is high. Transistor 66 is shown as a P-channel device, so when a column is selected (signal Yn high), transistor 66 for the selected column is non-conductive. However, transistors 66 in unselected columns become conductive.
Since each memory cell 12 along an active word line normally pulls down the voltage on one of the bit lines 14, 16 of its own column, when transistor 66 in that column becomes conductive, that memory cell pulls down both bit lines 14, 16. Pull the line below V _CC . To this end, all unselected column transistors 42, 44
is kept non-conducting and the extra capacitance is eliminated, eliminating the problems associated with that extra capacitance.

The reference voltage for the preferred implementation described herein is generated by the circuit shown in FIGS. Each circuit receives a chip selection signal CS. Each of these circuits also includes a P-channel transistor and an N-channel transistor to mimic the variation in characteristics of the transistors in the circuit shown in FIG. The circuits shown in FIGS. 1-4 are all fabricated on one chip.

In FIG. 2, the chip select signal CS is on line 80.
is combined with When signal CS is low, the output 81 of the inverter formed by transistors 90 and 92 is high. This high level output causes P channel transistors 84, 86
is rendered nonconductive and N-channel transistor 88 is rendered conductive. For this purpose, the source-drain path of transistor 88 connects circuit point 87.
potential is lowered to ground level. Circuit point 87 is connected to N-channel transistors 96, 98, 1
Since they are coupled to the gate of 00, those transistors are rendered non-conductive.

Additionally, when signal CS is low, P-channel transistor 82 is rendered conductive and the level at node 83 is pulled down to voltage V _CC . The source-drain path of transistor 82 is at circuit point 8
3 to the voltage V _CC . Circuit point 83
is coupled to the gate of P-channel transistor 94, so transistor 94 is rendered non-conductive. Transistors 94, 96, 98, 10
Since the zeros dissipate power, their transistors are rendered nonconductive when the chip select signal is low. When those transistors are non-conducting, the P-channel transistors 102
and N-channel transistors 104, 106, 1
08 keeps circuit point 85 near a voltage of about 3 volts (when V _CC is 5 volts). Transistor 102~
Since 108 is a low power transistor, power consumption is low. Circuit point 85 provides a reference voltage V _R1 .

When the chip select signal goes high, transistor 82 is rendered non-conductive. Then, since the output 81 of the inverter constituted by transistors 90 and 92 becomes low level, transistors 84 and 86 become conductive, and transistor 8
8 becomes non-conductive. Then, circuit point 83,
87 is connected to circuit point 85. To this end, P-channel transistor 94 is rendered non-conducting;
Transistors 96, 98, and 100 are rendered conductive. This circuit configuration results in a self-biased inverter, with output point 85 connected to input points 83 and 87. The output circuit point 85 is R
A reference voltage is provided that traces a P-channel transistor, which is modeled by channel transistor 94. Furthermore, the memory cell bus transistor 6
8, 70 are modeled by transistors 96, 98, 100. Therefore, the output V _R1 tracks the P-channel and N-channel transistors, thereby allowing the bet lines 14, 16 to be biased independently of the characteristics of the transistors. If the characteristics of P-channel transistor 32 of FIG. 1 change, the characteristics of transistor 94, which is formed on the same chip as that transistor, will also change to compensate for the load on the bit line.
The same thing applies to transistors 68, 70 and 96.
~100 also applies.

Preferably, the reference voltage V _R1 drives multiple columns. In the embodiment described herein, two reference voltage generators as shown in FIG. 2 are used for the 64K CMOS static RAM.

Figure 3 shows the reference voltages V _R2 and V _R3 for the column amplifiers.
The circuit that gives . The chip select signal in the reference voltage generator of FIG. 3 is applied to an inverter 114 comprised of transistors 116 and 118. When the chip select signal is low, the output 120 of inverter 114 is high. Output 120 is provided to the gates of the P-channel transistors and the gates of the N-channel transistors in stages 110 and 112. Therefore, when the chip select signal is at a low level, P-channel transistor 1
28 is rendered nonconductive and N-channel transistor 130 is rendered conductive, pulling node 134 through the source-drain path of transistor 130 to ground. Also, when the chip selection signal CS is at a low level, the transistors 122, 124, 126, 128, 13 in the stage 110
The current path through the source-drain path of V _CC to As is cut off.

When chip select signal CS is high, node 120 is high, which causes transistor 128 to conduct and transistor 130 to conduct.
is made non-conducting. Then circuit point 134
The voltage at transistors 122, 124,
26 and 128 to a potential determined by their relative dimensions. Therefore, when signal CS is high, current flows in stage 110 from the power supply V _CC to ground.

In stage 110, instead of using a single P-channel transistor to mimic the characteristics of a P-channel transistor, multiple channel transistors 122, 124, 126, 128 are used. This is to ensure that the transistors are biased into the linear region. Biasing in this manner minimizes the drain-source voltage of each of those transistors.
Transistors 48 and 50 of FIG. 1 are also biased in the linear region. Therefore, the reference voltage V _R2
correctly traces the characteristics of a P-channel transistor.

The stage 112 shown in FIG. 2 uses one less P-channel transistor;
It is the same as stage 110. The reason is that the reference voltage
This is because V _R3 is higher than the reference voltage V _R2 . This eliminates the need for extra transistors to keep all the transistors used in the linear region.

In the example described here, V _CC is 5 volts, the reference voltage V _R1 is approximately 3 volts, and the reference voltage V R1 is approximately 3 volts.
V _R2 is approximately 1.7 volts and reference voltage V _R3 is approximately 2.2 volts. This circuit provides a protection circuit that allows each component to still operate when V _CC is below the predicted 5 volt level. Such a protection circuit is shown in FIG. The protection circuit includes a circuit 134 having a P-channel transistor 136. When the voltage V _CC becomes low, the data read line 24
tends to drop to too low a level. The reason is that transistors 48, 50
This is because the current is biased toward the saturated region rather than the linear region.

To prevent this from happening,
Circuit 134 mimics column amplifier 40. As voltage V _CC decreases, circuit point 138 in circuit 134
The voltage drops before the voltage drops on the data read lines 24 and 26. Since the gate of transistor 140 is driven by V _R3 instead of reference voltage V _R2 , node 138 drops in voltage before data read line 24 drops in voltage. To this end, before transistors 48, 50 (FIG. 1) enter saturation as V _CC falls, transistor 140
is definitely placed in the saturated region. When node 138 goes low, transistor 136 becomes conductive, preventing data read line 24 from dropping to too low a level. Voltage V _CC is 3
If the protection circuit shown in FIG. 4 is not used, the data read line 24 will be approximately
Drops to volts. However, by using the protection circuit shown in FIG. 4, data read line 24 is maintained at approximately 2 volts.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a bit line load circuit for a semiconductor memory and some column circuits including column read and write circuits with control circuits; FIG. 2 shows the reference voltages used in the circuit of FIG. Figure 3 is a circuit diagram of a reference voltage generator that supplies two other types of reference voltages used in the circuit of Figure 1, Figure 4 is a low power supply voltage protection circuit. FIG. 10...Bit line load, 12...Memory cell, 1
4, 16... Bit line, 24, 26... Data read line, 30... Bit line clamp, 32, 46... Current source, 34... Balancing means, 40... Differential amplifier, 52,
54...Switching means.

Claims (1)

[Scope of Claims] 1. A memory array, a plurality of column line pairs 14 and 16, a plurality of word lines 18, each cell having a cross-coupled N-channel transistor pair, and the column line pair and the word line a plurality of multi-transistor memory cells 12, including one located at and connected to a corresponding column line, and a plurality of biasing means each connected to a corresponding column line, each said biasing means being a P-channel transistor 32 and an N-channel transistor 30 operating as a clamp, each transistor having a source-drain path connected between the supply voltage and the corresponding column line, and by specific biasing means. and a control circuit 10 in which the biasing means 10 is arranged so as to limit voltage swings on each column line because the column lines 14 and 16 are drawn to ground, the P channel the transistor is connected to operate as a current source, and the control circuit is connected to the supply voltage input terminal for each biasing means connected to a column line pair.
It further comprises a reference voltage circuit VRI connected to VCC and having an output connected to the gate of said P-channel transistor 32, said reference voltage circuit compensating for the effects of changes in environmental conditions within the integrated circuit device. A CMOS integrated circuit device comprising compensation means 96, 98, 100 for the purpose of 2. The compensation means of the reference voltage circuit comprises transistor elements 96, 98, 100 sized to mirror transistor elements of the bias means 10 and the memory cell 12, thereby compensating for environmental conditions within the device. The CMOS integrated circuit device according to claim 1, characterized in that: 3. The reference voltage circuit includes a first P-channel transistor 102 having a drain connected to a first supply voltage, and a source connected in series between the source of the first P-channel transistor and a reference potential. 3. Three connected N-channel transistors 96, 98, 100 having /drain paths.
CMOS integrated circuit device. 4. The CMOS integrated circuit device according to claim 1 or 2, wherein the reference voltage circuit includes a self-bias inverter having a P-channel transistor 90 and an N-channel transistor 92. 5. The reference voltage circuit comprises a P-channel transistor and an N-channel transistor to provide a first reference voltage that varies to compensate for changes in environmental conditions within the semiconductor memory cell. The CMOS integrated circuit device according to item 1 or 2. 6. A CMOS according to claim 1, wherein each memory cell comprises four N-channel transistors, two of which are connected in a cross-coupled latch circuit.
Integrated circuit device. 7 The first P-channel transistor 102
has a source-drain path connected between the first power supply voltage VCC and the output terminal of the reference voltage circuit, and the three N-channel transistors are connected between the reference potential and the output terminal. 4. The CMOS integrated circuit device of claim 3, further comprising a source-drain path coupled in series therebetween. 8. The CMOS integrated circuit device according to claim 1, wherein the reference voltage circuit applies a non-zero voltage to the gate electrode of the P-channel transistor 32 of the plurality of bias means. 9. The semiconductor memory includes a plurality of column transistors 42, 44 each having a gate connected to a corresponding column line 14, 16, each selectively coupling each data read line to a common node 60 between an associated pair of input transistors. a coupled data readout line pair 24, 26, such that each column has a column line pair, each common node being in selectively coupled relationship with said data readout line; The circuit further includes a current source load 4 coupled to the data readout line and a second reference voltage circuit VR2 that varies to compensate for changes in the environmental conditions within the integrated circuit device.
9. The CMOS integrated circuit device according to claim 1, further comprising: 8,50. 10 Further comprising a plurality of parasitic capacitance reducing means 66 each coupled between each of the column line pairs 14 and 16, the parasitic capacitance reducing means 66 is configured to reduce the number of columns selected in the memory cells between the column line pairs in response to a column selection signal Yn. 10. The CMOS integrated circuit device of claim 9, wherein the pair of column lines are coupled together such that the readout line is separable from each of the common nodes except for a common node. 11 data readout line pairs 24, 26 associated with a plurality of column line pairs, and a third data readout line pair for each column coupled to said data readout line and that changes to compensate for changes in transistor characteristics due to changes in ambient temperature.
each differential amplifier array 46, 56, 52, 54 connected to a third reference voltage circuit providing a reference voltage of
11. The CMOS integrated circuit device according to claim 1, further comprising a column circuit comprising a column circuit.