JPH0366857B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal receiving circuit used for signal transmission using power distribution lines.

An example of a transmission system using power distribution lines is shown in FIG. In Fig. 1, 1 is a main transformer installed in a distribution substation, and power from this main transformer 1 is stepped down to low voltage from a high voltage distribution line 2 through a pole transformer 4, and is then transferred to a low voltage distribution line. 5 to the consumer 7. In addition, signal transmission and reception is carried out by the central equipment 3 installed in the distribution substation.
This is performed between the relay device 6 installed near the pole transformer 4 and the terminal device 8 installed near the customer 7.

In such a signal transmission system, a frequency shift signal (hereinafter referred to as FS) is sent from the relay device 6 to the central device 3.
When transmitting a signal (referred to as a signal), an example of a signal receiving circuit of the central device 3 is shown in FIG.

In FIG. 2, reference numeral 9 denotes a feeder current transformer (hereinafter referred to as feeder CT) provided on the high-voltage distribution line 2. 10 is an input circuit for converting the output of the feeder CT9 into an appropriate signal voltage for the subsequent circuit; 11
is a bandpass filter (hereinafter referred to as BPF) that passes only the above FS signal band, 12 is an amplifier, and 13 is FS
This is a known FS demodulation circuit that demodulates a signal.

Next, its operation will be explained. Relay device 6
The FS signal injected into the lower voltage side of the pole transformer 4 is transmitted to the high voltage distribution line 2 via the pole transformer 4 and detected by the feeder CT9 of the distribution substation. The signal detected by this feeder CT9 is
After being converted into a signal suitable for the electronic circuit by the input circuit section 10, the commercial power frequency is converted by the BPF 11.
Noise, which is a fundamental wave and harmonics of 50 or 60 Hz, is removed, and the output from the BPF 11 is amplified by an amplifier 12 and then demodulated by an FS demodulation circuit 13.

In a signal transmission system using a power distribution line as a signal transmission path as described above, the ratio between the magnitude of the signal injected at the relay device 6 and the magnitude of the signal received at the central device 3 is determined by the characteristics of the power distribution line. That is, the signal transmission ratio may vary greatly depending on the frequency. In other words, the frequency of the signal wave of the FS signal is f _L ,
When f _H is assumed, a phenomenon occurs in which even if the signal magnitudes of f _L and f _H on the signal injection side are equal, the magnitudes of f _L and f _H on the receiving side are significantly different. Therefore, the second
In the conventional signal receiving circuit as shown in the figure, the BPF
If an imbalance occurs in the amplitudes of f _L and f _H as input signals of BPF 11, the duration of frequency components with large amplitudes will become longer in the output of BPF 11.
The duration of frequency components with small amplitude becomes shorter.
When this FS signal is demodulated, the time width of the signal differs from the waveform of the source, causing demodulation distortion, which has the disadvantage of generating code errors.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and aims to provide a signal receiving circuit that can correct the unbalance of a received signal and obtain an output without demodulation distortion. .

An embodiment of the present invention will be described below with reference to FIG. In FIG. 3, 14 is a correction circuit inserted between the stages of the BPF 11 and the amplifier 12 to correct the unbalance of the received signal, and 15 is the BPF mentioned above.
11 is an AC/DC conversion circuit that converts the AC output into DC; 16 is a signal detection circuit that determines the presence or absence of a received signal based on the output of the AC/DC conversion circuit 15; 17
18 is an analog/digital conversion circuit (hereinafter referred to as an A/D conversion circuit) that digitizes the output of the AC/DC conversion circuit 15, and a microprocessor 18 that controls unbalance correction.

Next, the operation will be explained. As shown in FIG. 4, the FS data signal from the relay device 6 has a detection signal B for unbalance level detection for a fixed time period, which is made up of f _H and f _L , added before the data signal A. When a signal is transmitted from the central device 6, the central device 3 receives the detection signal B before receiving the data signal. This detection signal B is first BPF1
1 removes noise components from the signal and inputs it to the AC/DC conversion circuit 15. And AC/DC conversion circuit 1
5 converts the detection signal, which was an alternating current, into a direct current proportional to the input, and outputs it to the signal detection circuit 16. This signal detection circuit 16 is set to generate an output when the output of the AC/DC conversion circuit 15 exceeds a certain value, and this set value is set to be lower than the received signal level from the relay device 6. It is set. Therefore, in a standby state where no signal is transmitted from the relay device 6, the signal detection circuit 16 does not generate an output. When the detection signal from the relay device 6 is received in this way, the signal detection circuit 16 generates an output, and the output is sent to the microprocessor 18.
This activation signal causes the microprocessor 18 to perform an unbalance correction operation. The operation is performed as follows. That is, when the activation signal is generated by the signal detection circuit 16, the microprocessor 18 uses the A/D conversion circuit 17 to measure the magnitude of the f _H signal of the detection signal B shown in FIG. 4, and stores it. Next, f _L of the detection signal B shown in FIG.
When the signal is received, the output of the FS demodulation circuit 13 is inverted. This inverted signal is sent to the microprocessor 18.
The microprocessor 18 measures and stores the magnitude of the f _L signal in the same manner as the f _H signal. Microprocessor 18 memorized
The ratio of both the f _H and f _L signals is calculated, and a control output is generated to the unbalance correction circuit 14 according to the result of this calculation. The unbalance correction circuit 14 is constructed as shown in FIG. 5a, and 14a to 14d are each constructed of filters having characteristics as shown in FIG. 5b. Reference numeral 14e denotes a changeover switch controlled by the microprocessor 18, which is normally located in the illustrated state and is switched to a position corresponding to the control output by the control output from the microprocessor 18. For example, when the ratio f _H :f _L becomes 1:3, the microprocessor 18 generates an output that selects the filter 14a. As a result, the 1:3 unbalanced FS signal A becomes a 1:1 balanced signal and is transmitted through the amplifier 12.
The signal is applied to the FS demodulation circuit 13 to perform normal demodulation.
When all FS signals are completed, the signal detection circuit 16 outputs no output, and the microprocessor 18 returns the changeover switch 14e to its original position.

In the above embodiment, the detection signal is measured by A/D.
Although the conversion circuit 17 and microprocessor 18 were used, the configuration of the integration circuit and multiplication circuit, etc.
A circuit that can measure and calculate signal levels may also be used.
Moreover, the unbalance correction filters 14a to 14d in FIG. 5 have f _L :f _H of 1:2, 1:3, and 2:
The ratio is 1:3:1, but this can be increased to 1:4, 1:5...1:n depending on the distribution line situation, and there is also a system that allows fine control such as 1:2.5. It's okay. Furthermore, although the correction circuit shown in FIG. 5 is of a type in which filters are arranged in parallel and switched, the values of resistors and capacitors constituting the filter circuit may also be directly switched. In the above embodiment, the case where the signal is transmitted from the relay device 6 to the central device 3 has been shown, but when using the FS signal in a transmission system using power distribution lines,
This signal receiving circuit can be used in any case.

As described above, according to the present invention, the levels of the two-frequency detection signal provided at the front stage of the FS data signal are measured, and the filter with the opposite characteristic output is selected based on the ratio, thereby creating an imbalance in the FS data signal. This method corrects the error rate and obtains a normal demodulated signal, and has the effect of significantly reducing the bit error rate in demodulation.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional transmission system using power distribution lines, Fig. 2 is a block diagram showing a signal receiving circuit in the conventional transmission system,
FIG. 3 is a block diagram showing an embodiment of the signal receiving circuit according to the present invention, FIG. 4 is an explanatory diagram showing the signal format used in the present invention, and FIG.
The figure is a block diagram showing an unbalance correction circuit in the signal receiving circuit of the present invention. In the figure, A...data signal, B...detection signal, 1
1...Band pass filter, 13...FS demodulation circuit,
14...Unbalance correction circuit, 15...AC/
DC conversion circuit, 16... Signal detection circuit, 17...
A/D conversion circuit, 18...microprocessor.
In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A device for receiving an FS data signal in which a fixed time detection signal consisting of both signal frequencies of the FS signal is added to the front stage of the data signal, comprising: a measurement circuit for measuring the level of the detection signal; A signal receiving circuit comprising: an arithmetic circuit that calculates the ratio of both signals based on the measurement results of the measurement circuit; and a correction circuit that corrects the FS data signal to a constant level based on the arithmetic results. 2 Connected to the above correction circuit via an amplifier
2. The signal receiving circuit according to claim 1, further comprising an FS demodulation circuit. 3. The signal receiving circuit according to claim 1 or 2, wherein the correction circuit is constituted by an inverse characteristic filter.