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JPH0367397B2 - - Google Patents
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JPH0367397B2 - - Google Patents

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Publication number
JPH0367397B2
JPH0367397B2 JP8625682A JP8625682A JPH0367397B2 JP H0367397 B2 JPH0367397 B2 JP H0367397B2 JP 8625682 A JP8625682 A JP 8625682A JP 8625682 A JP8625682 A JP 8625682A JP H0367397 B2 JPH0367397 B2 JP H0367397B2
Authority
JP
Japan
Prior art keywords
signal
frequency
pass filter
supplied
variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8625682A
Other languages
Japanese (ja)
Other versions
JPS58202682A (en
Inventor
Hiroshi Yasuda
Shinichi Tamura
Takeshi Hachimori
Toshiro Terauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP57086256A priority Critical patent/JPS58202682A/en
Publication of JPS58202682A publication Critical patent/JPS58202682A/en
Publication of JPH0367397B2 publication Critical patent/JPH0367397B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00Conversion of analogue values to or from differential modulation
    • H03M3/02Delta modulation, i.e. one-bit differential modulation
    • H03M3/022Delta modulation, i.e. one-bit differential modulation with adaptable step size, e.g. adaptive delta modulation [ADM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)

Description

【発明の詳細な説明】 本発明は音声信号、映像信号等の情報信号を符
号化して伝送するのに使用されるクロツクレート
を可変できる様にした波形符号化装置に関し、特
に簡単な構成で良好なクロツクレートの可変を可
能とし、平均ビツトレートを下げることができる
様にし、信号伝送品質を高めることができる様に
したものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform encoding device that is capable of varying the clock rate used to encode and transmit information signals such as audio signals and video signals, and particularly has a simple configuration and good performance. This makes it possible to vary the clock rate, lower the average bit rate, and improve signal transmission quality.

従来クロツクレートを可変できる様にした波形
符号化装置として第1図に示す如きものがある。
即ち、1は送信装置を構成する波形符号化装置、
2は受信装置を構成する復号装置、3a及び3b
は夫々伝送路を示す。この波形符号化装置1は情
報信号入力端子1aに供給される情報信号をカツ
トオフ周波数fVが後述する制御信号CSにより後述
する可変クロツク発生器7のクロツク信号の周波
数の1/2の周波数に制御される如く構成された可
変ローパスフイルタ4を介して波形符号化器を構
成する適応デルタ変調器5に供給すると共にこの
情報信号入力端子1aに供給される情報信号を実
効的周波数帯域幅を検出するバンド幅検出回路6
に供給し、このバンド幅検出回路6の出力側に入
力情報信号の実効的周波数帯域幅に応じた直流電
圧の制御信号CSを得、このバンド幅検出回路6の
出力側に得られる制御信号CSを電圧可変形発振回
路より構成された可変クロツク発生器7の発振周
波数制御端子に供給すると共にこの制御信号CS
可変ローパスフイルタ4のカツトオフ周波数制御
端子に供給してこの可変ローパスフイルタ4のカ
ツトオフ周波数fVを制御し、又この可変クロツク
発生器7の出力側に得られるクロツク信号を適応
デルタ変調器5に供給し、この適応デルタ変調器
5に於いてこのクロツク信号により標本化等を行
い、このクロツク信号により符号化を行う様にな
されている。この従来の波形符号化装置1の適応
デルタ変調器5の出力端子5aに得られるデルタ
変調信号及びバンド幅検出回路6の出力端子6a
に得られる制御信号CSを伝送路3a及び3bを介
して復号装置2に伝送し、この復号装置2の情報
信号入力端子2aに得られるデルタ変調信号を適
応デルタ変調復号器8に供給して復調し、この適
応デルタ変調復号器8の出力側に得られる復調信
号を可変ローパスフイルタ9を介して復調信号出
力端子9aに供給し、又この復号装置2の制御信
号入力端子2bに得られる制御信号CSをその出力
側に得られるクロツク信号を適応デルタ変調復号
器8に供給する電圧可変形発振回路より構成され
た可変クロツク発生器10に供給すると共にこの
制御信号CSを可変ローパスフイルタ9のカツトオ
フ周波数fVを制御する制御端子に供給し、この可
変ローパスフイルタ9のカツトオフ周波数fVを可
変クロツク発生器10のクロツク信号の周波数の
1/2の周波数とする如くする。
2. Description of the Related Art Conventionally, there is a waveform encoding device as shown in FIG. 1 which has a variable clock rate.
That is, 1 is a waveform encoding device that constitutes a transmitting device;
2 is a decoding device that constitutes a receiving device; 3a and 3b;
indicate the respective transmission paths. This waveform encoding device 1 converts the information signal supplied to the information signal input terminal 1a into a cut-off frequency fV that is half the frequency of the clock signal of the variable clock generator 7, which will be described later, using a control signal CS , which will be described later. The effective frequency bandwidth of the information signal supplied to the information signal input terminal 1a is supplied to the adaptive delta modulator 5 constituting the waveform encoder via the variable low-pass filter 4 configured to be controlled. Bandwidth detection circuit 6
A DC voltage control signal C S corresponding to the effective frequency bandwidth of the input information signal is obtained at the output side of this bandwidth detection circuit 6, and a control signal obtained at the output side of this bandwidth detection circuit 6 is supplied to C S is supplied to the oscillation frequency control terminal of a variable clock generator 7 constituted by a voltage variable oscillator circuit, and this control signal C S is supplied to the cut-off frequency control terminal of the variable low-pass filter 4. The cutoff frequency fV of the variable clock generator 7 is controlled, and the clock signal obtained at the output side of the variable clock generator 7 is supplied to the adaptive delta modulator 5, and the adaptive delta modulator 5 performs sampling, etc. using this clock signal. , and encoding is performed using this clock signal. The delta modulated signal obtained at the output terminal 5a of the adaptive delta modulator 5 of this conventional waveform encoding device 1 and the output terminal 6a of the bandwidth detection circuit 6
The control signal C S obtained in the above is transmitted to the decoding device 2 via the transmission lines 3a and 3b, and the delta modulation signal obtained at the information signal input terminal 2a of the decoding device 2 is supplied to the adaptive delta modulation decoder 8. The demodulated signal obtained at the output side of the adaptive delta modulation decoder 8 is supplied to the demodulated signal output terminal 9a via the variable low-pass filter 9, and the control signal obtained at the control signal input terminal 2b of the decoding device 2 is supplied to the demodulated signal output terminal 9a. The signal C S is supplied to a variable clock generator 10 constituted by a voltage variable oscillator circuit which supplies the clock signal obtained at its output to an adaptive delta modulation decoder 8, and this control signal C S is passed through a variable low-pass filter 9. A cutoff frequency fV of the variable low-pass filter 9 is supplied to a control terminal for controlling the cutoff frequency fV, so that the cutoff frequency fV of the variable low-pass filter 9 is made to be half the frequency of the clock signal of the variable clock generator 10.

斯る従来の波形符号化装置1及び復号装置2に
於いては入力情報信号の周波数帯域を検出して可
変クロツク発生器7,10の発振周波数及び可変
ローパスフイルタ4,9のカツトオフ周波数fV
制御しているので、入力情報信号中に高域成分が
ないときには可変クロツク発生器7,10の発振
周波数が低くなり、平均ビツトレートを下げるこ
とができ、これにより信号伝送品質を高めること
ができると共に可変ローパスフイルタ4,9のカ
ツトオフ周波数fVも低くなり、量子化ノイズを減
らすことができる。
In the conventional waveform encoding device 1 and decoding device 2, the frequency band of the input information signal is detected to determine the oscillation frequency of the variable clock generators 7 and 10 and the cutoff frequency fV of the variable low-pass filters 4 and 9. Therefore, when there is no high-frequency component in the input information signal, the oscillation frequency of the variable clock generators 7 and 10 is lowered, and the average bit rate can be lowered, thereby improving the signal transmission quality. The cutoff frequency fV of the variable low-pass filters 4 and 9 is also lowered, and quantization noise can be reduced.

然しながら斯る従来の波形符号化装置1及び復
号装置2としては主情報信号であるデルタ変調信
号の伝送路3aの外にバンド幅検出回路6の出力
側に得られる制御信号CSを伝送する伝送路3bを
必要とし、それだけ構成が複雑となる欠点がある
と共にバンド幅検出回路6としてはFFT(高速フ
ーリエ変換器)等を必要としその構成が複雑とな
る欠点があつた。
However, the conventional waveform encoding device 1 and decoding device 2 have a transmission method in which the control signal C S obtained at the output side of the bandwidth detection circuit 6 is transmitted outside the transmission path 3a of the delta modulated signal, which is the main information signal. There is a disadvantage that the circuit 3b is required, which complicates the configuration, and that the bandwidth detection circuit 6 requires an FFT (Fast Fourier Transformer) or the like, which complicates the configuration.

本発明は斯る点に鑑み簡単な構成で良好なクロ
ツクレートの可変を可能とし、平均ビツトレート
を下げることができる様にし、信号伝送品質を高
めることができる様にしたものである。
In view of these points, the present invention has been developed to enable good clock rate variation with a simple configuration, to lower the average bit rate, and to improve signal transmission quality.

以下第2図を参照しながら本発明波形符号化装
置の一実施例につき説明しよう。この第2図に於
いて、第1図に対応する部分には同一符号を付し
その詳細説明は省略する。
An embodiment of the waveform encoding device of the present invention will be described below with reference to FIG. In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

本例に於いては情報信号入力端子1aに供給さ
れる情報信号を可変ローパスフイルタ4を介して
波形符号化器を構成する適応デルタ変調器5に供
給する。本例に於いてはこの適応デルタ変調器5
の一部に局部復号部5bを設ける。この局部復号
部5bは適応デルタ変調器5に於いて符号化した
デルタ変調信号を再び復号化するものでこの局部
復号部5bの出力側には後述する復号装置2の適
応デルタ変調復号器8の出力信号と同様の復調信
号が得られる如くなされる。この局部復号部5b
の出力側に得られる復調信号をハイパスフイルタ
11に供給する。このハイパスフイルタ11のカ
ツトオフ周波数fVは復調信号が音声信号であると
きには例えば1.5kHzとし、この1.5kHz以上の信号
をレベル検出回路12に供給し、このレベル検出
回路12に於いてはハイパスフイルタ11を通過
した信号のレベルを検出し、この高域信号のレベ
ルに応じた直流電圧を得、これにより高域成分
の、多少を知ることができこれを入力情報信号例
えば音声信号の実効的周波数帯域幅とみなすこと
ができる。このレベル検出回路12のレベル検出
信号を制御信号CSとして電圧可変形発振回路によ
り構成した可変クロツク発生器7の発振周波数制
御端子に供給し、この可変クロツク発生器7の発
生するクロツク信号の周波数をレベル検出回路1
2の検出レベルに応じて増大する様にすると共に
このレベル検出回路12のレベル検出信号を制御
信号CSとして可変ローパスフイルタ4のカツトオ
フ周波数制御端子に供給し、この制御信号CSによ
りこの可変ローパスフイルタ4のカツトオフ周波
数fVを可変クロツク発生器7のクロツク信号の周
波数の1/2の周波数とする如くする。又可変クロ
ツク発生器7のクロツク信号を適応デルタ変調器
5に供給し、この適応デルタ変調器5に於いてク
ロツク信号を基準として入力情報信号をデルタ変
調する如くなす。この適応デルタ変調器5の出力
端子5aに得られるデルタ変調信号を伝送路3を
介して復号装置2に伝送し、この復号装置2の情
報信号入力端子2aに得られるデルタ変調信号を
適応デルタ変調復号器8に供給して復調し、この
適応デルタ変調復号器8の出力側に得られる復調
信号を可変ローパスフイルタ9を介して復調信号
出力端子9aに供給する。
In this example, the information signal supplied to the information signal input terminal 1a is supplied via a variable low-pass filter 4 to an adaptive delta modulator 5 constituting a waveform encoder. In this example, this adaptive delta modulator 5
A local decoding section 5b is provided in a part of the decoding section. This local decoding section 5b decodes again the delta modulation signal encoded in the adaptive delta modulator 5, and the output side of this local decoding section 5b is connected to the adaptive delta modulation decoder 8 of the decoding device 2, which will be described later. This is done so that a demodulated signal similar to the output signal is obtained. This local decoding section 5b
The demodulated signal obtained at the output side of the filter is supplied to the high-pass filter 11. The cut-off frequency fV of this high-pass filter 11 is set to 1.5 kHz, for example, when the demodulated signal is an audio signal, and this signal of 1.5 kHz or more is supplied to the level detection circuit 12. The level of the signal that has passed is detected, and a DC voltage corresponding to the level of this high-frequency signal is obtained. This allows us to know the amount of high-frequency components. It can be considered as width. The level detection signal of this level detection circuit 12 is supplied as a control signal CS to the oscillation frequency control terminal of a variable clock generator 7 constituted by a voltage variable oscillation circuit, and the frequency of the clock signal generated by this variable clock generator 7 is The level detection circuit 1
The level detection signal of this level detection circuit 12 is supplied as a control signal C S to the cut-off frequency control terminal of the variable low-pass filter 4, and this control signal C S The cutoff frequency fV of the filter 4 is made to be half the frequency of the clock signal of the variable clock generator 7. Further, the clock signal of the variable clock generator 7 is supplied to the adaptive delta modulator 5, and the adaptive delta modulator 5 delta modulates the input information signal using the clock signal as a reference. The delta modulated signal obtained at the output terminal 5a of this adaptive delta modulator 5 is transmitted to the decoding device 2 via the transmission line 3, and the delta modulated signal obtained at the information signal input terminal 2a of this decoding device 2 is adaptively delta modulated. The signal is supplied to a decoder 8 for demodulation, and the demodulated signal obtained at the output side of the adaptive delta modulation decoder 8 is supplied via a variable low-pass filter 9 to a demodulated signal output terminal 9a.

又適応デルタ変調復号器8の出力側に得られる
復調信号をハイパスフイルタ11と同様に構成さ
れた例えば1.5kHz以上の周波数の信号を通過する
ハイパスフイルタ13に供給し、このハイパスフ
イルタ13の出力信号をレベル検出回路12と同
様に構成されたレベル検出回路14に供給し、こ
のレベル検出回路14に於いてはハイパスフイル
タ13を通過した信号のレベルを検出し、この高
域信号のレベルに応じた直流電圧を得、これによ
り高域成分の多少を知ることができ、これを入力
情報信号例えば音声信号の実効的周波数帯域とみ
なすことができる。このレベル検出回路14のレ
ベル検出信号を制御信号CSとして電圧可変発振回
路により構成した可変クロツク発生器10の発振
周波数制御端子に供給し、この可変クロツク発生
器10の発生するクロツク信号の周波数をレベル
検出回路14の検出レベルに応じて増大する様に
すると共にこのレベル検出回路14のレベル検出
信号を制御信号CSとして可変ローパスフイルタ9
のカツトオフ周波数制御端子に供給し、この制御
信号CSにより、この可変ローパスフイルタ9のカ
ツトオフ周波数fVを可変クロツク発生器10のク
ロツク信号の周波数の1/2の周波数とする如くす
る。又可変クロツク発生器10のクロツク信号を
適応デルタ変調復号器8に供給し、この適応デル
タ変調復号器8に於いてこのクロツク信号を基準
としてデルタ変調信号を復調する如くなす。
Further, the demodulated signal obtained at the output side of the adaptive delta modulation decoder 8 is supplied to a high-pass filter 13 configured similarly to the high-pass filter 11 and which passes signals with a frequency of 1.5 kHz or higher, for example, and the output signal of this high-pass filter 13 is is supplied to a level detection circuit 14 configured similarly to the level detection circuit 12, and this level detection circuit 14 detects the level of the signal that has passed through the high-pass filter 13, and detects the level of the high-frequency signal according to the level of the high-pass filter 13. By obtaining a DC voltage, it is possible to know the amount of high-frequency components, and this can be regarded as the effective frequency band of an input information signal, such as an audio signal. The level detection signal of the level detection circuit 14 is supplied as a control signal CS to the oscillation frequency control terminal of the variable clock generator 10 constituted by a voltage variable oscillation circuit, and the frequency of the clock signal generated by the variable clock generator 10 is controlled. The level detection signal of the level detection circuit 14 is used as a control signal C S to increase the level according to the detection level of the level detection circuit 14, and the variable low-pass filter 9
This control signal C S is used to set the cut-off frequency f V of the variable low-pass filter 9 to half the frequency of the clock signal of the variable clock generator 10 . The clock signal of the variable clock generator 10 is also supplied to the adaptive delta modulation decoder 8, and the adaptive delta modulation decoder 8 demodulates the delta modulation signal using this clock signal as a reference.

斯る第2図の波形符号化装置1及び復号装置2
に於いては第1図例と同様に入力情報信号の周波
数帯域を検出して可変クロツク発生器7,10の
発振周波数及び可変ローパスフイルタ4,9のカ
ツトオフ周波数fVを制御しているので入力情報信
号中に高域成分がないときには可変クロツク発生
器7,10の発振周波数が低くなり、平均ビツト
レートを下げることができ、これにより信号伝送
品質を高めることができると共に可変ローパスフ
イルタ4,9のカツトオフ周波数fVも低くなり、
量子化ノイズを減らすことができる。更に本例に
於いては復号器5b,8により復調した復調信号
をハイパスフイルタ11,13及びレベル検出回
路12,14により周波数帯域を検出しているの
で、この周波数帯域を検出する検出回路が簡単と
なると共に特別に制御信号CSを伝送する伝送路を
必要とせずそれだけ構成が簡単となる利益があ
る。
The waveform encoding device 1 and decoding device 2 shown in FIG.
In this case, the frequency band of the input information signal is detected as in the example in FIG . When there is no high-frequency component in the information signal, the oscillation frequency of the variable clock generators 7 and 10 is lowered, and the average bit rate can be lowered. The cutoff frequency f V also becomes lower,
Quantization noise can be reduced. Furthermore, in this example, the frequency band of the demodulated signal demodulated by the decoders 5b and 8 is detected by the high-pass filters 11 and 13 and the level detection circuits 12 and 14, so the detection circuit for detecting this frequency band is simple. In addition, there is an advantage that a special transmission path for transmitting the control signal C S is not required, and the configuration is simpler.

尚上述実施例に於いては可変ローパスフイルタ
4を設けたが、適応デルタ変調器5は可変ローパ
スフイルタの効果もあるのでこの可変ローパスフ
イルタ4を省略することができる。又本発明は上
述実施例に限らず本発明の要旨を逸脱することな
く、その他種々の構成が取り得ることは勿論であ
る。
Although the variable low-pass filter 4 was provided in the above embodiment, the adaptive delta modulator 5 also has the effect of a variable low-pass filter, so the variable low-pass filter 4 can be omitted. Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations may be adopted without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の波形符号化装置の例を示す構成
図、第2図は本発明波形符号化装置の一実施例を
示す構成図である。 1aは情報入力端子、4は可変ローパスフイル
タ、5は適応デルタ変調器、5aは出力端子、5
bは局部復号部、7は可変クロツク発生器、11
はハイパスフイルタ、12はレベル検出回路であ
る。
FIG. 1 is a configuration diagram showing an example of a conventional waveform encoding device, and FIG. 2 is a configuration diagram showing an embodiment of the waveform encoding device of the present invention. 1a is an information input terminal, 4 is a variable low-pass filter, 5 is an adaptive delta modulator, 5a is an output terminal, 5
b is a local decoder, 7 is a variable clock generator, 11
1 is a high-pass filter, and 12 is a level detection circuit.

Claims (1)

【特許請求の範囲】 1 入力信号を符号化して符号化信号を伝送する
と共に、該符号化信号を複号する局部複号部を有
する波形符号化手段と、 該波形符号化手段にクロツク信号を供給する可
変クロツク発生手段と、 上記波形符号化手段の局部複号部の出力信号が
供給されるハイパスフイルタと、 該ハイパスフイルタにより得られた高域成分の
レベルを検出し、該レベルに応じた制御信号を出
力するレベル検出手段とを有し、 該レベル検出手段から得られる制御信号によ
り、上記可変クロツク発生手段のクロツク信号の
周波数を制御するようにしたことを特徴とする波
形符号化装置。
[Scope of Claims] 1. Waveform encoding means having a local decoding unit that encodes an input signal and transmits the encoded signal, and decodes the encoded signal; and a clock signal to the waveform encoding means. a high-pass filter to which the output signal of the local decoding section of the waveform encoding means is supplied; detecting the level of the high-frequency component obtained by the high-pass filter; 1. A waveform encoding device comprising: level detection means for outputting a control signal; and the frequency of the clock signal of the variable clock generation means is controlled by the control signal obtained from the level detection means.
JP57086256A 1982-05-21 1982-05-21 Waveform coding device Granted JPS58202682A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57086256A JPS58202682A (en) 1982-05-21 1982-05-21 Waveform coding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57086256A JPS58202682A (en) 1982-05-21 1982-05-21 Waveform coding device

Publications (2)

Publication Number Publication Date
JPS58202682A JPS58202682A (en) 1983-11-25
JPH0367397B2 true JPH0367397B2 (en) 1991-10-22

Family

ID=13881736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57086256A Granted JPS58202682A (en) 1982-05-21 1982-05-21 Waveform coding device

Country Status (1)

Country Link
JP (1) JPS58202682A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61247183A (en) * 1985-04-25 1986-11-04 Nippon Telegr & Teleph Corp <Ntt> Method for reducing coded sample number
GB2184316B (en) * 1985-12-17 1989-10-11 Sony Corp Two-dimensional finite impulse response filter arrangements.

Also Published As

Publication number Publication date
JPS58202682A (en) 1983-11-25

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