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JPH036743B2 - - Google Patents
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JPH036743B2 - - Google Patents

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Publication number
JPH036743B2
JPH036743B2 JP59253281A JP25328184A JPH036743B2 JP H036743 B2 JPH036743 B2 JP H036743B2 JP 59253281 A JP59253281 A JP 59253281A JP 25328184 A JP25328184 A JP 25328184A JP H036743 B2 JPH036743 B2 JP H036743B2
Authority
JP
Japan
Prior art keywords
current
base
transistor
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59253281A
Other languages
Japanese (ja)
Other versions
JPS61132082A (en
Inventor
Masatake Metsugi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59253281A priority Critical patent/JPS61132082A/en
Publication of JPS61132082A publication Critical patent/JPS61132082A/en
Publication of JPH036743B2 publication Critical patent/JPH036743B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は電力変換装置のうち商用周波数の交
流電力を、より高い周波数の交流に変換する装
置、いわゆる高周波インバータのうち特に電流形
インバータに関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a power conversion device that converts AC power at a commercial frequency to AC power at a higher frequency, and particularly relates to a current source inverter among so-called high frequency inverters. It is.

〔従来の技術〕[Conventional technology]

第7図は従来の電流形インバータを示す回路図
であり、図において1はサイリスタ11〜16の
ブリツジ接続で構成された順変換回路、2は直流
リアクトル、3はサイリスタ31〜34のブリツ
ジ接続で構成された逆変換回路、4は負荷電圧の
検出信号を受けて逆電圧時間を確保するタイミン
グでサイリスタ11〜16,31〜34を点弧さ
せる信号を出すゲート制御回路、5はコンデンサ
51とコイル52とからなる並列共振回路であ
る。
FIG. 7 is a circuit diagram showing a conventional current source inverter. In the figure, 1 is a forward conversion circuit composed of a bridge connection of thyristors 11 to 16, 2 is a DC reactor, and 3 is a bridge connection of thyristors 31 to 34. 4 is a gate control circuit that receives a load voltage detection signal and outputs a signal to fire the thyristors 11 to 16 and 31 to 34 at a timing to secure the reverse voltage time; 5 is a capacitor 51 and a coil; This is a parallel resonant circuit consisting of 52.

次に動作について説明する。順変換装置1のサ
イリスタ11〜16はゲート制御回路4のゲート
信号により負荷電圧が所定の値となる位相角で通
流し端子RSTの三相交流側からの電力を端子P1
Nへ直流電圧に変えて出す。直流リアクトル2は
次の逆変換回路3、並列共振回路5を経由する閉
回路中の電流を、ほぼ定電流とみなせる程度に平
滑化する作用をする。逆変換回路3のサイリスタ
31〜34は自己消弧能力がないため、第8図に
示す各部の電圧電流波形のように常に進み力率で
運転し第8図bに示すT1なるサイリスタのター
ンオフタイム以上の逆電圧期間を設けるようにゲ
ート制御回路4で制御している。35はそのタイ
ミングを決める基点となるべき負荷電圧の零点を
検出するための電圧検出器である。サイリスタ3
1,34とサイリスタ32,33が交互に導通を
繰返すことによつて並列共振回路5には第5図a
に示すような正弦波の電圧vと方形波の電流iが
与えられる。
Next, the operation will be explained. The thyristors 11 to 16 of the forward converter 1 conduct electricity at a phase angle such that the load voltage reaches a predetermined value according to the gate signal of the gate control circuit 4, and transfer power from the three-phase AC side of the terminal RST to the terminals P 1 ,
Convert it to DC voltage and output it to N. The DC reactor 2 functions to smooth the current in the closed circuit passing through the next inverse conversion circuit 3 and the parallel resonant circuit 5 to such an extent that it can be regarded as a substantially constant current. Since the thyristors 31 to 34 of the inverse conversion circuit 3 do not have a self-extinguishing ability, they are always operated at a leading power factor as shown in the voltage and current waveforms of each part shown in Fig. 8, and the thyristors are turned off at T1 shown in Fig. 8b. The gate control circuit 4 controls to provide a reverse voltage period longer than the time. 35 is a voltage detector for detecting the zero point of the load voltage, which is the reference point for determining the timing. Thyristor 3
1 and 34 and the thyristors 32 and 33 alternately repeat conduction, the parallel resonant circuit 5 has a state shown in FIG.
A sinusoidal voltage v and a square wave current i as shown in are given.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の電流形インバータは以上のように、サイ
リスタを転流失敗させることなく正常に動作させ
るためには、サイリスタのターンオフタイム以上
の逆電圧時間を設ける必要がある。従つて、周波
数が高い領域になつて1サイクルの周期が短かく
なつても常に一定時間(およそ30μsec)の逆電圧
時間すなわち電圧電流の位相差時間を必要とする
ため、力率が非常に悪くなり負荷へ経済的に電力
を送ることができないという問題点があつた。こ
の場合、ターンオフタイムの短かいサイリスタを
採用することも考えられるが、定格電圧を同一と
すると製作が困難なことから高価となる問題点が
あつた。
As described above, in the conventional current source inverter, in order to operate the thyristor normally without commutation failure, it is necessary to provide a reverse voltage time longer than the turn-off time of the thyristor. Therefore, even if the frequency becomes high and the period of one cycle becomes short, a certain amount of time (approximately 30 μsec) of reverse voltage time, that is, phase difference time of voltage and current, is always required, resulting in a very poor power factor. However, there was a problem in that it was not possible to economically send power to the load. In this case, it may be possible to use a thyristor with a short turn-off time, but if the rated voltage is the same, it would be difficult to manufacture and therefore expensive.

この発明は上記のような問題点を解消するため
になされたもので、安価でかつ周波数が高い領域
でも負荷に経済的に電力を送ることのできる電流
形インバータを得ることを目的とする。
The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a current source inverter that is inexpensive and can economically send power to a load even in a high frequency range.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る電流形インバータは、ダイオー
ドとトランジスタの直列構成からなる逆変換回路
と、上記トランジスタのベース駆動回路とを備え
たものである。
A current source inverter according to the present invention includes an inverse conversion circuit formed of a series configuration of a diode and a transistor, and a base drive circuit for the transistor.

〔作用〕[Effect]

この発明においては、トランジスタのベースド
ライブにより逆変換回路を構成したので、電圧零
点前の必要時間がサイリスタ式の逆電圧時間に比
較して低減される。
In this invention, since the inverse conversion circuit is configured by driving the base of a transistor, the time required before the voltage reaches zero point is reduced compared to the inverse voltage time of the thyristor type.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明す
る。第1図において、1はサイリスタのパワーモ
ジユール17〜19で構成された順変換回路、2
は直流リアクトル、6はトランジスタのパワーモ
ジユール61,62とダイオードのパワーモジユ
ール65〜68で構成された逆変換回路、5はコ
ンデンサ51とコイル52で構成された並列共振
回路、35は電圧検出器、69は電流検出器、7
はベースドライブ信号発生回路70とベースドラ
イブアンプ71〜74等で構成されたトランジス
タのベース駆動回路である。
An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a forward conversion circuit composed of thyristor power modules 17 to 19;
6 is a DC reactor, 6 is an inverse conversion circuit composed of transistor power modules 61 and 62 and diode power modules 65 to 68, 5 is a parallel resonant circuit composed of a capacitor 51 and a coil 52, and 35 is a voltage detection circuit. 69 is a current detector, 7
is a transistor base drive circuit composed of a base drive signal generation circuit 70, base drive amplifiers 71 to 74, and the like.

次に、上記のように構成された電流形インバー
タの動作について説明する。但し、順変換側回路
の動作は従来と同様であるから説明を省略する。
ベースドライブ信号発生回路70では、定常時の
負荷電圧についての電圧検出器35の信号から、
電圧零点を基準としてトランジスタのパワーモジ
ユール61,62の切換のタイミング信号を発生
している。その信号がベースドライブアンプ71
〜74に与えられ、パワーモジユール61,62
の内部トランジスタ61a,62bおよび61
b,62aを交互に駆動して出力電流の経路を切
換えている。この切換動作中は全トランジスタが
流通している瞬間があり、その重なり期間は負荷
条件で異なつてくる。そこで負荷電流の零点を電
流検出器69の信号で確認し、ベースドライブ信
号70a,70bのタイミングが電圧零点と電流
零点が一定範囲内におさまるようにフイードバツ
クループで制御している。第3図Aはベースドラ
イブアンプ71とトランジスタの1組61aの詳
細図でベースドライブアンプ71はトランジスタ
61aを駆動中は端子71aから71bに第3図
Bの電流波形に示すトランジスタの駆動ベース電
流IB1流し3段ダーリントン接続形のトランジス
タ61aを飽和領域に駆動している。次の半サイ
クルには端子71bから71aに電圧を加えて電
流波形に示すIB2の蓄積キヤリヤ放出の電流を流
して速やかなトランジスタ61aの電流しや断動
作を行わせ、その後は微弱な外乱等では誤動作し
ないようにバイアス電圧をかけている。なお、ト
ランジスタの駆動ベース電流IB1を流すとトラン
ジスタは1μsec程度の遅れでコレクタからエミツ
タに電流ICが通流するのに対しトランジスタしや
断のためのキヤリヤ吸収電流IB2を流してもIB2
流れ続けている時間中はトランジスタは電流阻止
能力が回復していなく、かなり長い時間(5〜
20μsec)コレクタからエミツタへの電流ICを流し
続けるのでベーストライブ信号発生回路70の端
子70a,70bの信号は同一タイミングで相互
に反転するものであつても自動的に全トランジス
タの通流の期間が確保できる。しかしその重なり
期間が自然転流する期間より長くなると負荷のコ
ンデンサ51の放電回路を形成して大電流が流れ
るためトランジスタの責務が急増しついには破壊
に至る危険があるため逆流阻止用のダイオード6
5〜68が必要である。
Next, the operation of the current source inverter configured as described above will be explained. However, since the operation of the forward conversion side circuit is the same as the conventional one, the explanation will be omitted.
In the base drive signal generation circuit 70, from the signal of the voltage detector 35 regarding the load voltage during steady state,
A timing signal for switching the transistor power modules 61 and 62 is generated using the voltage zero point as a reference. That signal is the base drive amplifier 71
~74, power modules 61,62
internal transistors 61a, 62b and 61
b and 62a are alternately driven to switch the output current path. During this switching operation, there is a moment when all the transistors are in communication, and the overlapping period varies depending on the load conditions. Therefore, the zero point of the load current is confirmed by the signal of the current detector 69, and the timing of the base drive signals 70a and 70b is controlled by a feedback loop so that the voltage zero point and the current zero point are within a certain range. FIG. 3A is a detailed diagram of the base drive amplifier 71 and a pair of transistors 61a. While the base drive amplifier 71 is driving the transistor 61a, the drive base current I of the transistor shown in the current waveform of FIG. 3B flows from terminals 71a to 71b. The B1 sink three-stage Darlington connection type transistor 61a is driven into the saturation region. In the next half cycle, a voltage is applied from terminal 71b to terminal 71a to flow a current for releasing the accumulated carriers of I B2 shown in the current waveform to quickly cut off the current in transistor 61a, and after that, weak disturbances etc. A bias voltage is applied to prevent malfunction. Note that when the drive base current I B1 of the transistor is applied, the current I C flows from the collector to the emitter with a delay of about 1 μsec . During the time when B2 continues to flow, the transistor's current blocking ability is not recovered, and it takes quite a long time (5~5~
20μsec) Since the current I C continues to flow from the collector to the emitter, even if the signals at terminals 70a and 70b of the base drive signal generation circuit 70 are mutually inverted at the same timing, the period of conduction of all transistors is automatically maintained. can be secured. However, if the overlapping period is longer than the natural commutation period, a discharge circuit is formed for the load capacitor 51 and a large current flows, which increases the duty of the transistor and there is a risk that it may eventually be destroyed.
5-68 is required.

逆に端子70a,70bの信号が共に休止する
空白期間がある場合はトランジスタ61a,61
b,62a,62bが全部通流阻止の状態が発生
する。このとき、直流リアクトル2は電流を継続
させようと作用し高電圧を発生するので通流阻止
の動作をしたトランジスタは絶縁破壊されてしま
うことになる。従つてこの現象を防止するために
は必ず電流を転流させて直流リアクトル2の電流
が継続する回路を確保しながら交互に切換えるこ
とが条件となる。
Conversely, if there is a blank period in which both the signals at the terminals 70a and 70b are at rest, the transistors 61a and 61
A situation occurs in which all of b, 62a, and 62b are blocked. At this time, the DC reactor 2 acts to continue the current and generates a high voltage, resulting in dielectric breakdown of the transistor that acts to block current flow. Therefore, in order to prevent this phenomenon, it is necessary to commutate the current and alternately switch it while ensuring a circuit in which the current of the DC reactor 2 continues.

本回路では基本的に逆電圧時間は不要なのでサ
イリスタ式と異なり遅れ力率による運転も可能で
あるが、遅れ力率の場合は転流しようとする回路
に逆電圧が増勢しつつあり進み力率の状態に比較
して転流の推進力は弱いため、完全に転流が完了
しないうちにトランジスタが通流阻止をする可能
性が高く、この時は全トランジスタ通流阻止に準
ずる過電圧を発生し、トランジスタを破壊する危
険性が大きい。
This circuit basically requires no reverse voltage time, so unlike the thyristor type, it is possible to operate with a lagging power factor, but in the case of a lagging power factor, the reverse voltage is increasing in the circuit to be commutated, resulting in a leading power factor. Since the driving force for commutation is weak compared to the state of , there is a great risk of destroying the transistor.

従つて安定と安全を確保するために第2図a〜
iに示すようにわずかな進み力率で制御し運転を
行う。
Therefore, in order to ensure stability and safety, Figure 2 a~
Operation is performed under control with a slight leading power factor as shown in i.

従つて、ベースドライブ信号のタイミングはト
ランジスタのしや断動作時間(IB2が流れてから
全OFF状態になるまでの時間)を考慮して転流
時間が確保できる状態に制御される。通常転流重
なり時間は5μsec程度なので電圧零点前5〜
20μsecのタイミングが得られることになり、サイ
リスタ式の逆電圧時間(30μsec以上)に対して格
段に短かい時間となり高周波でも高力率の運転が
可能となる。
Therefore, the timing of the base drive signal is controlled in such a manner that the commutation time can be secured, taking into account the transistor's cut-off operation time (the time from when I B2 flows until it becomes completely OFF). Normally, the commutation overlap time is about 5μsec, so 5 to 5 seconds before the voltage zero point
A timing of 20 μsec is obtained, which is much shorter than the reverse voltage time of the thyristor type (30 μsec or more), and operation with a high power factor is possible even at high frequencies.

第4図は第2図における転流の部分と第3図B
のベース駆動電流の関係を時間軸を拡大して示し
たものである。
Figure 4 shows the commutation part in Figure 2 and Figure 3B.
This is an enlarged view of the relationship between the base drive currents on the time axis.

この図においてコレクタ−エミツタ間電流IC
対のトランジスタが通流を開始したため負荷回路
の電圧の方向が転流を助勢するのでキヤリヤの吸
収いかんにかかわらず減少して転流を完了する。
このときのトランジスタは電流ICが流れていると
きキヤリヤ吸収電流IB2を流して通流阻止をした
時と異なり、はるかに飽和の深い状態からの通流
阻止であり、かつコレクタからエミツタへの電圧
印加がなく、キヤリヤ移動勢力が弱いため、転流
開始から電圧零点(T1〜T3)の時間が短かい時
は、T4に示すように電流ICが再通流した後に通流
阻止状態になり、この電流のしや断によりトラン
ジスタの接続されたブリツジの回路インダクタン
スに比例した過電圧が発生する。即ち、運転に際
しT1〜T3の約20μsの進み力率相当の時間をもた
すか、電流の大きさを過電圧が許容値に納まる範
囲で運転を行つている。
In this figure, the collector-emitter current I C decreases regardless of whether it is absorbed by the carrier or not, and the commutation is completed because the direction of the voltage in the load circuit assists the commutation since the pair of transistors has started conducting.
In this case, the transistor is different from the case where the carrier absorption current I B2 is caused to flow when the current I C is flowing, and the current is blocked from flowing from a much deeper saturated state, and the current is blocked from the collector to the emitter. When there is no voltage applied and the carrier moving force is weak, when the time from the start of commutation to the voltage zero point (T 1 to T 3 ) is short, the current I C flows again after commutation as shown at T 4 . A blocking condition occurs, and this current interruption generates an overvoltage proportional to the circuit inductance of the bridge to which the transistor is connected. That is, during operation, the time corresponding to the leading power factor of about 20 μs from T 1 to T 3 is allowed, or the current is operated so that the overvoltage falls within the permissible value.

この発明の実施例は第5図に示すようにトラン
ジスタ61aに対するベース駆動回路7は、ベー
スとエミツタに接続する第1の回路ユニツト71
と、コレクタとベースに接続する第2の回路ユニ
ツト91とで構成されている。
In the embodiment of the present invention, as shown in FIG. 5, the base drive circuit 7 for the transistor 61a includes a first circuit unit 71 connected to the base and emitter.
and a second circuit unit 91 connected to the collector and base.

第6図はこの場合の動作を説明したもので第4
図と同様な時点を示している。ここで電流IB1
IB2を流しているのは第4図と同様であるが、電
流IB2と同期してコレクタからベースにIXなる電流
を流している点が異なる。IB2を流しつつコレク
タとベース間に電圧を加えているため、コレクタ
とベース間のキヤリヤがIXなる電流となつて速や
かに吸収される。従つて第4図の電流IB2の流れ
る時間に対し50%以下の時間(10μsec程度)で流
れ終えて通流阻止状態となる。したがつて、格段
に力率を良くでき、周波数の高い領域でも使用で
きる。
Figure 6 explains the operation in this case.
The same time points as in the figure are shown. Here the current I B1 ,
The flow of I B2 is the same as in Figure 4, but the difference is that a current of I X is flowed from the collector to the base in synchronization with the current I B2 . Since a voltage is applied between the collector and base while flowing I B2 , the carrier between the collector and base becomes I X and is quickly absorbed. Therefore, the current flow ends in less than 50% (about 10 μsec) of the flow time of the current I B2 shown in FIG. 4, and the current flow is blocked. Therefore, the power factor can be improved significantly and it can be used even in a high frequency range.

なお、上記実施例では逆変換回路6の構成とし
て2素子内蔵形のトランジスタのパワーモジユー
ル61,62と1素子のダイオードのパワーモジ
ユール65〜68を示したが、逆に1素子のトラ
ンジスタのパワーモジユール4個を直流側に、2
素子内蔵のダイオードのパワーモジユール2個を
高周波出力側に接続する構成としても良い。
In the above embodiment, the configuration of the inverse conversion circuit 6 is shown as power modules 61 and 62 of transistors with built-in two elements and power modules 65 to 68 of diodes with one element. 4 power modules on the DC side, 2
A configuration may also be adopted in which two power modules of diodes with built-in elements are connected to the high frequency output side.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によればサイリスタに変
えて、汎用のパワーモジユールのトランジスタと
ダイオードで構成したので、装置が安価にでき、
また、サイリスタ式よりも高い周波数で使用でき
るという効果がある。
As described above, according to the present invention, the thyristor is replaced with a general-purpose power module transistor and diode, so the device can be made inexpensively.
Another advantage is that it can be used at a higher frequency than the thyristor type.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による電流形イン
バータを示す回路概念図、第2図はその回路動作
説明の波形図、第3図は第1図のベース駆動回路
の接続の詳細及び駆動電流波形を示す図、第4図
は第3図での転流時点の動作説明の波形図、第5
図はこの発明の実施例を示すベース駆動回路の接
続図、第6図は第5図での転流時点の動作説明の
波形図、第7図は従来のサイリスタ式電流形イン
バータの回路概念図、第8図は第7図の回路動作
説明の波形図である。図において、5は並列共振
回路、6は逆変換回路、7はベース駆動回路、6
1,62はトランジスタ、65〜68はダイオー
ドである。なお、各図中同一符号は同一または相
当部分を示す。
FIG. 1 is a circuit conceptual diagram showing a current source inverter according to an embodiment of the present invention, FIG. 2 is a waveform diagram explaining the circuit operation, and FIG. 3 is a connection detail and drive current of the base drive circuit shown in FIG. 1. Figure 4 is a waveform diagram explaining the operation at the time of commutation in Figure 3, Figure 5 is a diagram showing waveforms.
The figure is a connection diagram of a base drive circuit showing an embodiment of the present invention, Figure 6 is a waveform diagram explaining the operation at the time of commutation in Figure 5, and Figure 7 is a circuit conceptual diagram of a conventional thyristor type current source inverter. , FIG. 8 is a waveform diagram illustrating the circuit operation of FIG. 7. In the figure, 5 is a parallel resonant circuit, 6 is an inverse conversion circuit, 7 is a base drive circuit, and 6 is a parallel resonant circuit.
1 and 62 are transistors, and 65 to 68 are diodes. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 ブリツジ接続された逆変換回路の各辺をトラ
ンジスタとダイオードとの直列接続回路で構成
し、並列共振回路を負荷に有する電流形インバー
タにおいて、上記各トランジスタのベース駆動回
路は上記トランジスタのベースとエミツタとの間
に接続され、上記トランジスタのベースからエミ
ツタへ第1のベース電流を流し、続いてエミツタ
からベースへ第2のベース電流を流して上記トラ
ンジスタの電流をしや断し、所定のバイアス電圧
を印加する第1の回路ユニツトと、上記トランジ
スタとベースとの間に接続され、上記第2のベー
ス電流と同期してコレクタからベースへコレクタ
とベースとの間の蓄積キヤリア放出電流を流す第
2の回路ユニツトとで構成したことを特徴とする
電流形インバータ。
1. In a current source inverter in which each side of a bridge-connected inverse conversion circuit is composed of a series-connected circuit of a transistor and a diode, and the load is a parallel resonant circuit, the base drive circuit of each transistor is connected to the base and emitter of the transistor. A first base current is passed from the base of the transistor to the emitter, and a second base current is then passed from the emitter to the base to cut off the current of the transistor, and a predetermined bias voltage is applied. a first circuit unit that is connected between the transistor and the base, and a second circuit unit that is connected between the transistor and the base and causes an accumulated carrier discharge current between the collector and the base to flow from the collector to the base in synchronization with the second base current. A current source inverter characterized by comprising a circuit unit.
JP59253281A 1984-11-29 1984-11-29 Current type inverter Granted JPS61132082A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59253281A JPS61132082A (en) 1984-11-29 1984-11-29 Current type inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59253281A JPS61132082A (en) 1984-11-29 1984-11-29 Current type inverter

Publications (2)

Publication Number Publication Date
JPS61132082A JPS61132082A (en) 1986-06-19
JPH036743B2 true JPH036743B2 (en) 1991-01-30

Family

ID=17249097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59253281A Granted JPS61132082A (en) 1984-11-29 1984-11-29 Current type inverter

Country Status (1)

Country Link
JP (1) JPS61132082A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5429955B2 (en) * 2008-08-01 2014-02-26 北芝電機株式会社 Current source inverter
JP5335312B2 (en) * 2008-08-01 2013-11-06 北芝電機株式会社 Current source inverter

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5889073A (en) * 1981-11-24 1983-05-27 Hitachi Ltd Current source inverter device

Also Published As

Publication number Publication date
JPS61132082A (en) 1986-06-19

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