JPH0368019A - Fault detecting system for adder - Google Patents

Abstract

PURPOSE:To detect a fault of a computing element which is not dualized by bringing a result of addition of an adder to feedback to an input stage, executing the addition to '0' data and generating a parity, and executing a parity check again. CONSTITUTION:Numbers X, Y to be operated pass through arithmetic input selecting parts 31, 32 and sent to an arithmetic part by an instruction of an arithmetic input selection instructing part 4. A result of operation is stored in an arithmetic result store part 2, and a parity generated by a parity generating part 5 is stored in parity store part, and checked by a parity check part 7. The result of operation stored in the arithmetic result store part 2 is brought to feedback to the arithmetic input selecting part 31, and added to an output of a zero data generating part 9. With respect to this addition, the parity check is executed again.

Description

[Detailed description of the invention] Technical field The present invention relates to an adder failure detection method.

PRIOR ART Conventionally, the method for detecting errors in this type of adder is to duplicate the adder and compare the results of each addition, or,
Adder failures have been detected by determining parity from the addition result of one adder and performing a parity check with the addition result of the other adder. In such a fault detection method, the amount of hardware of the computing unit increases,
When incorporated into an LSI or the like, there is a drawback that the design of the LSI is often difficult due to constraints such as the number of bins or cells.

OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide an adder failure detection method that requires a small amount of hardware.

Structure of the Invention The adder failure detection method of the present invention is an adder failure detection method for detecting a failure in an adder that performs addition processing of input data, and the adder failure detection method detects a failure in an adder that performs addition processing of input data. input supply means for selectively supplying the addition result data of two data and a set of "0" to the adder; a parity generation means for generating parity of the addition result of the adder; and checking the parity output. A parity check means is provided, and the parity check means checks using the result of addition of the two data and the parity of the result of addition of the two results of addition and "0" data. shall be.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows a circuit diagram of an embodiment of the present invention. The calculation unit 1 is an adder that adds two input data, and the calculation result of the calculation unit 1 is held in the calculation result storage unit 2. The calculation input selection instruction section 4 instructs the calculation input selection sections 31 and 32 regarding selection conditions.

- (The property generation unit 5 generates a property based on the calculation result of the calculation unit 1). The parity generated by the parity generation section 5 is held in the parity storage section 6, and the parity check section 7 performs a parity check between the output of the operation result storage section 2 and the output of the parity storage section 6.

A storage timing signal to be applied to the calculation result storage section 2 and the parity storage section 6 is generated by a storage timing generation section 8. The zero data generation section 9 has a function of sending "O" data to the calculation input selection section, and this "0" data is input to the calculation input selection section 32. It also has a path for feeding back the output of the calculation result storage section 2 to the calculation input selection section 31 .

Next, the operation of one embodiment of the present invention will be explained using FIG.

The operands X and Y to be calculated become input data X and Y to the calculation unit 1 via the calculation input selection units 31 and 32 according to instructions from the calculation input selection instruction unit 4.

The calculation result is stored in the calculation result storage section 2 by the set signal 10 shown in FIG. Further, the parity generated by the parity generation section 5 in response to the set signal 11 in FIG. 2 is stored in the parity storage section 6, and further parity checked by the parity check section 7.

All set signals are output by the storage timing generator 8. As a result, a failure in the calculation result storage unit 2 is detected.

Subsequently, the calculation results stored in the calculation result storage section 2 are fed back to the calculation input selection section 31.The data that becomes the input data X and Y to the calculation section 1 according to the instruction from the calculation input selection instruction section 4 is These are the feedback data described above and the "0" data sent out by the zero data generating section 9.

Parity is generated from this calculation result by the parity generation unit 5 and stored in the parity storage unit 6.The calculation result itself is not stored in the calculation result storage unit 2, but the calculation result storage unit 2 stores the previous calculation result. Remaining. In this state, the parity check section 7 performs a parity check using the data (X+Y) and the parity in the current parity storage section 6, thereby making it possible to detect a failure in the adder.

As described in detail, the present invention feeds back the addition result of the adder to the input stage of the adder to execute the addition with O' data, generates parity from the operation result, and uses the previous operation. By performing a parity check with the result,
This has the effect of being able to detect a failure in a single, non-duplicated arithmetic unit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a timing diagram showing one embodiment of the present invention. Explanation of symbols of main parts 1... Arithmetic unit 5... Parity generation unit 6... Parity storage unit 7... Parity check unit 9...・Zero data generation part

Claims (1)

[Claims] (1) An adder failure detection method that detects a failure in an adder that performs addition processing of input data.
input supply means for selectively supplying a set of 0'' to the adder, parity generation means for generating parity of the addition result of the adder, and parity check means for checking the parity output. , a failure of an adder characterized in that the parity checking means checks the parity using the result of addition of the two data and the parity of the result of addition of the two results of addition and "0" data. Detection method.