JPH0368474B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a static random access memory.

BACKGROUND OF THE INVENTION Important requirements for static random access memory (SRAM) are related to operating speed, integration density, and power consumption. The issue of power consumption is extremely important because the trade-off between power consumption and operating speed is very important. That is, large current logic elements used to achieve high-speed operation usually consume large amounts of power, and the power consumption per element poses a serious constraint on the improvement of the degree of integration. Therefore, it is expected that SRAM technology will advance significantly, generally through improvements in any circuit configuration that can reduce power consumption. High-speed static RAM that uses features to reduce power consumption is rated at 2147,4K× by Intel.
Introduced in 1SRAM. This allows the system to power up a few RAM chips on the memory board and retrieve data from those chips while leaving the remaining chips powered down. This shortens the power consumption duty cycle and increases the chip's average active power.
It was possible to increase the operating speed of SRAM.
Since SRAM is asynchronous during operation, a chip select or enable signal was required to initiate a read or write cycle at the current valid address. In addition, Mostek provides edge-trigger operations within the address path.
Further improved SRAM access time.
In this operation, SRAM cycles are recognized as asynchronous once a chip is selected. Once a chip is selected, an SRAM cycle is initiated by the occurrence of an address transition. Voltage transitions on either address lines are detected and an internal clock is used to precharge the bit lines. This allows the sense amplifier to return to equilibrium before the next cell is decoded. The use of this edge trigger technique (or "address transition" or "X-pulse" technique) has been widely applied in many modern SRAM devices to help achieve the objectives described above.

This method reduces chip power consumption, allowing the use of devices capable of high speed operation without being constrained by average power consumption per single region, averaged over temperature relaxation time. become. However, even with this method, it takes a significant amount of time to power up the device when the device is not currently in the signal path. For example, in the sample state-of-the-art SRAM technology, the address transition (when the row and/or column address applied to the external pins of the memory package changes) is typically 2 to 5 ns (nanoseconds) to change the state of the row decoder, 4 to 5 ns or more to change the state of the row decoder, or 4 to 4 ns before the previous transistor of the memory in the selected row of each column opens. ~5ns or more is required. Typically an additional 15-20 ns is required to change the state of the sense amplifier. The column decoder requires only 5 or 6 ns after receiving the address to raise the line voltage and connect the selected column's sense amplifier to the output bus. Therefore, the sense amplifier is not connected to the signal path flow until 10 ns or so after the address buffer changes state. The row select logic is not actually within a single address path for 25 ns after the address buffer changes state. Furthermore, the row decode logic is not connected in the signal path until approximately 10-15 ns or more after the address buffer changes state. Therefore, in the prior art, all these logic elements must be powered for the majority of the read cycle, i.e., more than 40 nanoseconds, after changing from the first state of the output buffer to the next state. . This means that excessive power is consumed. That is, the overall length of time each individual element in the signal path is powered up is:
This gradually becomes longer than the time required to perform the function of the element. Although each element consumes only a small amount of electrical energy during this extra power supply time, when the effects of these power consumptions are combined, the total power consumption used by peripheral elements is equal to the required amount. SRAM
The average power consumption (that is, power consumption in the cell + power consumption in peripheral elements) inevitably increases.

<Problems to be solved by the invention> As explained above, in the conventional SRAM,
Since power had to be supplied to peripheral elements until the time when they were not needed to execute a function, the average power consumption of the SRAM as a whole tended to increase. It is an object of the present invention to provide an arrangement that reduces power consumption within an SRAM.

<Means for Solving the Problems> The present invention provides an internal critical path that synchronizes in response to the signal flow, powers up the signal transmission path, uses a clock, and synchronizes the power up time and the signal flow time. The use of timing elements is a conventional technique for detecting address transitions in that the active power consumption cycles are reduced to the very minimum possible without reducing the operating speed of the SRAM.

According to the invention, an array of memory cells arranged in rows and columns, address decoder means for receiving an address signal comprising a plurality of address bits for addressing said memory cells, said address decoder means corresponding to rows of said array row address decoder means for receiving and decoding bits of said address bits and column address decoder means for receiving and decoding bits of said address bits corresponding to columns of said array, connected to at least said row and column address decoder means. means for providing a first power-up energy signal to said row address decoder means in dependence on a propagation time of said address signal to said row address decoder means, and subsequently providing another power-up energy signal to said address signal. means for providing the first power-up energy signal to the column address decoder means in dependence on the propagation time of the signal to the column address decoder means; and means for providing the first power-up energy signal in dependence on the propagation time of the address signal through the row address decoder means. and means for decoding the row address from the row address decoder means.

<Function> The present invention reduces power consumption in peripheral circuits during unnecessary times by using a novel circuit configuration to power up elements in the active signal path in response to signal flow. In the first embodiment, the power-up means synchronizes with the signal flow and powers up the elements in the signal propagation path.
A dummy element that is exactly the same as the element in the actual signal path is used. The timing elements used are
Since the elements in the signal and power paths are identical, they track each other even during process changes and temperature changes. In particular, a dummy element (such as a dummy column address decoder) is used to provide an appropriate delay to the asynchronous power-up signal for activating its corresponding power element, such as an active column decoder. This novel technique allows for completely accurate matching of the asynchronous signal and the appropriate delay time required to activate the power element. That is, even if the propagation speed of the logic element changes due to a change in the process, the signal propagation speed of the dummy element is also affected, so that the asynchronous power-up signal is provided to the active logic element at an appropriate timing.

In a second embodiment, not only is a delay time tailored to each circuit element used to trigger the power-up input of each circuit element, but also the duration of the power-up pulse provided to each circuit is is also adjusted according to each element. That is, a pulse generator circuit with a one-shot constant pulse duration is used to provide a power-up signal to each circuit element, and the duration of the pulse provided by the one-shot pulse generator circuit is also adjusted for each element. Ru.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in relation to a static random access memory using conventional six transistor cells, and the decoder, sense amplifier and other peripheral circuitry are substantially conventional. However, the power-up signals for the address buffer, decoder, and preamplifier are controlled by delayed asynchronous power-up signals discussed below.

An SRAM configuration according to the present invention is shown in FIG.
All address lines 104, 106 and read/write lines 108 are gated by chip select signal 122, delay element 112 and exclusive OR
Edge detection circuit 110 composed of circuit 114
connected to. The output of this circuit forms a common bus that detects transitions on either the address or read/write lines that occur when the chip is selected. This signal 102 is defined as φ ₀ shown in FIG.

The use of chip select gate operations and the detection of transitions in the read/write signal 108 on a transition detection bus are novel features of the present invention that differ from conventional structures. However, transition detection mechanism 110 is structurally identical to a conventional edge-triggered SRAM circuit. Conventional SRAM uses the signal φ ₀ to
It performs presetting and balancing functions for SRAM bit lines and sense circuits, thereby improving operating speed. In an arrangement according to the invention, the power-up chain is initiated only when a transition on the address or read/write lines occurs that is greater than the transition on the delay element in the transition detector, even if the external chip select signal 122 is high. The signal φ ₀ immediately powers up the X-address buffer 116;
It allows the transmission of signals from the Ax bus 118 through this buffer 116 to the X decoder 120. This buffer is the first element in the SRAM critical path and must be powered up as soon as an address transition occurs. The delay in this power-up signal 102 is determined by the delay in the transition detection circuit 110 and is determined by the noise tolerance required on the system lines. This is because the noise glitches (erroneous electrical signals) in the system lines cause the SRAM to
This is because there is a risk that the address transition may be interpreted as an address transition. This problem is, of course, common to all edge trigger configurations.
φ ₀ pulse 102 is also applied to flip-flop 124
This creates a delay chain.
is starting. This flip-flop 124
The output of dummy address buffer 12 is connected to dummy address buffer 12 by preset signal 132 (shown as ground in FIG. 3).
6. Decoder 128 and word line/driver 1
Power up 30. This timing chain includes the set of X address buffer 116 decoder 120 and word line driver 134 and word line 1
Since it is constructed from the same elements as those in the actual signal flow through 36, delays can be tracked.

That is, it is preferable, although not necessary, to use active logic elements in the dummy path (ie, power-up control path) to emulate the same logic elements used in the active signal path. This means that
This means that accurate timing emulation is provided without the designer having to calculate timing. It also means that the delay characteristics of the dummy elements accurately track the characteristics of these signal path elements, so that the delay time provided is not affected by process differences. However, it is also possible, although less preferred, to use delay elements without using exactly the same elements. especially,
Word line driver 136, 1 with driver 130' (having a twisted polysilicon line that has the same overall length as the word line and covers the moat with the same length)
Although it is possible to emulate the word line/driver using a capacitive element connected to a somewhat shorter polysilicon line, it is easy to emulate the word line/driver and configure it to have almost the same RC (resistive capacitor) time constant. be able to.

Since the dummy path has a predetermined signal, the output φ _XL
138 increases the voltage on flip-flop 124. The output of this flip-flop 124 is the fourth
It is shown as φ _x 140 in the figure. This signal is
It is used to hold the power level of the address buffer long enough for the decoder to drive the appropriate word line to allow access to the cell and output the data it possesses on the bit line. At the same time, _.phi .

Since the column address in the SRAM is only needed after the word line goes high, this address is not present within the critical timing pulse. Next, the power up signal for the column path is
It is activated after the address (row address) signal reaches the X decoder. It is easily possible to perform operations such as the above in an X-power up chain by applying the _φX signal after a dummy decoder is connected in the timing generation path.
Furthermore, the timing of the φ _Y signal 142 is responsive to the φ _X signal 140, as shown in FIG.

This timing signal is applied to the dummy X word line 13.
0 is driven, the Y address buffer 14
4 and Y address (column address) decoder 146 is powered up and after word line 130 is powered down, the output of the decoder is held as is until the word line is sufficiently active, and then powered down. Therefore, the word line is powered up for a sufficient period of time to determine from which bit line data must be taken.

The second power-up timing chain, activated by signal _φXL , is identical to the first timing chain. When the chip is in read mode, this timing chain is used to
52 and output buffer 154 and driver circuit 156. Since the fall time of the previously selected word line determines the deselection time, the power-up timing can also be created using the word line delay time. The sense amplifier/output circuit must hold output data until the next cell is selected. The φ _OE signal 158 shown in FIG. 4 is used to keep each element in this area powered up during the time that the data on bit line 172 is propagated through preamplifier 150, sense amplifier 152, and output buffer 154. Ru. The sense circuit 152 is configured in the desired latch format so that the row and column circuits 1
Data can be retained even after 50,134 is powered down. When the next signal transition is not detected when using the latching sense amplifier 152
It also allows the output to remain valid when the rest of the SRAM has finished its power-up cycle.
As a result, the system can ensure asynchronous and static operation. Therefore, the output data is held by power supplied to a small latch circuit, rather than powering up the entire SRAM to hold the data. Therefore, the duty cycle at which the active circuits are powered up is equal to the time required to transmit the signal through these circuits, making the most efficient use of power within the SRAM for these circuits. .

That is, the position of the first latch determines how much of the SRAM must be kept powered up to keep the output valid.

The present invention allows circuits prior to the first latch circuit to be powered down.

The preferred embodiment of the present invention uses the latch sense amplifier 152 and output buffer 154 to ensure that the sense amplifier 152 and output buffer 154 remain powered up as long as the chip is enabled after an address transition is detected. 152 is used. However, this is not an essential element of the invention. In particular, an alternative embodiment of the present invention may use a latch output buffer 154 to connect all circuitry prior to output buffer 154 (row decoders, column decoders, and sense amplifiers) to an asynchronous power-down signal in accordance with the present invention. After an address transition is detected, the chip remains enabled unless another address transition occurs.
Power is provided by the output buffer 154 and driver 156
This is sufficient to keep the output data valid.

As explained above, another novel feature of the present invention is that the write enable bit is configured as one of the bits connected to the address transition edge detection circuit. This initiates an asynchronous power up cycle in accordance with the present invention. Asynchronous power-up operations are particularly advantageous in write modes where high power consumption occurs in some of the peripheral circuits. However, in this case it is necessary to provide a power down arrangement for the case where a single bit is written to immediately after it has been read. In this case, only the write enable bit changes state. Such conditions are appropriately handled according to the present invention, but were not properly handled in prior art circuits.

In other embodiments of the invention, other sets of dummy elements are used to determine the delay time used during write mode. That is, in the write mode (in this embodiment), column decoder 146 must be powered up before sense amplifier 152, rather than sense amplifier 152 being powered up before column decoder 146. Preferably, row decoder 120 also needs to be powered up before any other element.

The description has been made primarily with reference to static random access memories because static random access memories have strict power consumption constraints on relatively predictable signal paths. Regardless of what memory technology is commonly referred to as "static RAM" by those skilled in the art,
The present invention is applicable to any memory that has completely static (i.e., not controlled by an external clock) operation. Dummy elements are used to define appropriate delays so that peripheral circuitry in the signal path is powered up only when necessary. Preferably, separate power-up timing is provided for read and write modes.

The names "row decoder" and "column decoder" used above simply define the decoder with the longer delay time, ie, the one in the critical timing path, as the "row decoder". In the prior art, row decoders had long time constants because they drove word lines, typically made of polysilicon or polyimide. These word lines are typically shown in the drawings as an array arranged horizontally across the rows and columns. However, regardless of which axis of the matrix is horizontally arranged and illustrated, and regardless of which axis of the matrix is referred to by the manufacturer as a "row," it is used in this specification and the claims. The word "row" refers to the axis of the matrix whose access time is within the critical delay path.

It is preferred to power up each of the separate elements using constant width pulses to minimize power consumption and also prevent interference from noise generated on the address lines. That is, the column decoders receive power-up pulses with durations tailored to the needs of the column decoders and with delays tailored to the typical delays that exist between row access times and column access times. The column preamplifier will receive longer duration, shorter delay pulses than the column decoder. The row decoder has no delay time and will receive pulses with very long durations to match the typically long time constants of word lines, which are typically constructed of polysilicon or polyimide.

Such operations are preferably performed using a one-shot circuit as shown in FIG. 1C for reference, and preferably implemented as a static random access memory configuration as shown in FIG. However, the invention may be configured with numerous other memory layouts. The preferred embodiment of the present invention has six transistor cells 174, sense amplifier 1, which are completely conventional.
52, a row decoder 120, a column decoder 146, etc., the present invention may be implemented in new architectures and device designs that are yet to be developed.

When the peripheral circuit is powered up only when one or more input addresses change in order to realize a pseudo-static system in the peripheral circuit, the conventional technology usually uses an exclusive OR circuit for the address input and an Ain for the output. The exclusive OR logic of and Ain(D) or delayed Ain appears. The output of this circuit is therefore a pulse with a duration corresponding to the delay time applied to the address input signal.

The circuits described herein by reference generate pulses with pulse durations that are either longer or shorter than the time constant.

The circuits described herein for reference are shown in FIGS. 1C and 5. Below is the inverter I ₁ −
I ₄ (Figure 1A) and exclusive NOR logic circuit (Figure 1B)
The operation of the chain including (Fig.) will be explained.

The chain of inverters I ₁ I ₂ I ₃ I ₄ in FIG.
Create Ain(D) from Ain. (See Figure 2) These two inputs Ain and Ain(D) are exclusive in Figure 1B.
This becomes the input to the NOR gate. This uses the very widely used configuration for exclusive NOR gates.

The output of an exclusive NOR gate is normally at a high potential. (See Figure 2) This output becomes a low potential when Ain changes. The output remains at a low potential until a change in Ain appears at Ain(D). At this point the exclusive NOR output goes high. This is also shown in FIG.

This exclusive NOR output is connected to the gate of transistor _T6 of FIG. 1C. If output A (Fig. 2) is initially at a low potential, the input from the exclusive NOR circuit is normally at a high potential and the inverted input of the output appears at the gate of transistor _T5 , so that the device
Both T ₅ and T ₆ are turned on.

Here when the address input changes and exclusive
When the NOR input goes low, transistor _T6 is turned off. As soon as transistor T ₆ is turned off, output A is at a high potential. This is because output A is a NAND logic output of an exclusive NOR output and its delayed inverted NOR output. Also,
This change to a high potential level at output A appears as a low potential level on the gate of T ₅ after being delayed by inverters I ₅ , I ₆ , I ₇ . This low potential level state is propagated through delay line D ₁ and then inverted by inverter I ₈ , which opens transistor T ₆ and pulls down the potential at output A. Three inverters I ₅ , I ₆ , I ₇
After a delay at , T ₅ reopens and the input to T ₆ can be detected.

Therefore, in a sample embodiment of the present invention, in a 16KSRAM with a geometric dimension of 2-3 microns,
The pulse duration applied to the row decoder is 15-20 nanoseconds. The power-up pulses applied to the column decoders preferably have a duration of 9-12 nanoseconds and are delayed 10-15 nanoseconds from the initial power-up pulses applied to the row decoders. The power up pulse given to the sense amplifier is
It preferably has a duration of 10-15 nanoseconds and is delayed for 10-15 seconds from the first power-up pulse applied to the row decoder.

That is, the circuit of FIG. 1C can be used in place of the dummy logic elements 162-166 and flip-flop 166 of FIG. 3 by adjusting the delay circuit _D1 to generate a pulse of a desired pulse duration. .

Using a pulse with constant pulse duration,
Problems related to noise can be significantly reduced. Once the X-NOR output is detected changing to a low potential, a power up pulse is generated and latch-in can be initiated to provide a pulse with a predetermined pulse duration. Once latch-in starts (passes through the NAND gate)
The exclusive NOR input to the NAND circuit is rejected until the power-up pulse is no longer present and the NAND circuit is reset. Therefore, the only addresses that will be latched into the buffer will be those signals that are present on the pin for a short time before the power-up pulse becomes active. This can prevent problems related to address skew (noise) from occurring.

<Effects> Therefore, the present invention provides an SRAM with reduced power consumption.
I will provide a. In particular, the present invention further reduces power consumption than prior art edge-triggered SRAMs. In particular, the present invention allows efficient use of power in both read mode and write mode.

As will be apparent to those skilled in the art, the present invention is susceptible to a wide range of implementations and modifications and is not to be limited except in accordance with the claims appended hereto.

[Brief explanation of drawings]

FIG. 1A is a reference diagram showing a chain including inverters used to provide a delayed address signal Ain(D) corresponding to each input address bit Ain. FIG. 1B is a reference diagram showing a conventional exclusive NOR edge trigger circuit for address bus detection. FIG. 1C is a reference diagram illustrating a pulse generation circuit with a predetermined pulse duration used in a preferred embodiment of the present invention. FIG. 2 is a reference diagram showing the waveform of a signal produced by the pulse generation circuit having the predetermined pulse duration of FIG. 1C.
It is shown in this figure that the noise on the address lines does not shorten or lengthen the pulse duration of the pulses produced. FIG. 3 shows a static random access memory organization that includes delay logic that provides a synchronous circuit configuration with efficient power consumption, so that elements in the signal path are powered up only for as long as needed. FIG. 2 is a diagram showing a static random access memory having such a configuration. FIG. 4 is a timing table of signal waveforms appearing at the signal positions shown in the memory layout of FIG. 3. FIG. 5 is a reference circuit diagram showing in more detail the circuit for generating pulses having a predetermined pulse duration shown in FIG. 1C.

Claims (1)

[Scope of Claims] 1 (a) a memory cell array arranged in rows and columns, (b) address decoder means for receiving an address signal including a plurality of address bits for addressing the memory cells, and (c) the above. The address decoder means comprises row address decoder means for receiving and decoding bits of said address bits corresponding to rows of said array, and column address decoder means for receiving and decoding bits of said address bits corresponding to columns of said array; (d) being connected to at least said row and column address decoder means to provide a first power-up energy signal to said row address decoder means in dependence on the propagation time of said address signal to said row address decoder means; means for subsequently providing another power-up energy signal to the column address decoder means in dependence on the propagation time of the address signal to the column address decoder means; A static random access memory comprising: means for removing a signal from said row address decoder means depending on the propagation time through said row address decoder means. 2. In said memory, the cells in each said column have a sense amplifier, said power up means is connected to said sense amplifier, and said row address decoder is dependent on the propagation time of said address signal through said address decoder means. 2. The static random access memory according to claim 1, wherein the sense amplifier is powered up after the sense amplifier is powered up.