JPH0369458B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A pulse insertion/removal circuit generates three types of signals: a signal with one pulse inserted from the master clock every predetermined period, a signal with one pulse removed, and a signal without pulse insertion/removal. It forms a signal, selects the output signal of the pulse insertion/removal circuit according to the identification code, and adds it to the digital phase synchronization circuit as a reference signal for SAT detection, using a single master clock.
It is possible to form three types of reference signals for SAT detection.

[Industrial application field]

The present invention is applicable to SAT in a car telephone system.
(Supervisory Aadio Tone) signal and other three-frequency tone signals to detect whether or not the tone signal is specified by the identification code. The present invention relates to a reference signal generation circuit for detecting a three-frequency tone signal to which a reference signal is added.

For example, the SAT signal in a car telephone system is used to identify each system zone distributed in a cellular manner, and this system is called a cellular system. The AST signal in this cellular system has three types of frequencies, for example,
5970Hz, 6000Hz, and 6030Hz are used.

In each cell, data is transmitted and received between the base station existing in that cell and the vehicle terminal device, and the frequency of the SAT signal of that cell is notified to the vehicle terminal device using an identification code. The automobile terminal device that receives the identification code detects whether the received SAT signal is the SAT signal specified by the identification code, and if it determines that it is the specified SAT signal, enables the specified channel. If it is determined that the SAT signal is not the specified SAT signal, the specified channel is invalidated and the SAT signal reception detection process is performed again. This is to prevent

[Conventional technology]

A conventional SAT signal receiving section in an automobile terminal device has, for example, the configuration shown in FIG.
A phase comparator 51 compares the phases of a signal obtained by dividing the output signal of the voltage controlled oscillator 53 with the frequency divider 54 and the received SAT signal, and calculates the phase difference. A signal corresponding to the voltage becomes the control voltage of the voltage controlled oscillator 53 via the loop filter 52. Therefore, the output signal of the voltage controlled oscillator 53 becomes a signal whose phase is synchronized with the received SAT signal. This signal is added to the DPLL section 55 as a reference signal, and an output signal phase-synchronized with the received SAT signal is obtained.

The output signal of this DPLL unit 55 is continuously output as a SAT signal even if there is a momentary interruption of the received SAT signal due to fading etc. Therefore, the identification code that specifies the frequency of the SAT signal in the cell Accordingly, the frequencies of the output signals of the DPLL unit 55 are compared, and if the comparison matches, it is determined that the correct SAT signal is being received.

[Problem that the invention seeks to solve]

In the conventional example, there is a dual phase control loop including a phase control loop including the voltage controlled oscillator 53 and a phase control loop of the DPLL section 55, and the phase synchronization pull-in is performed in the DPLL section 55. It is not possible to determine that the correct SAT signal has been received by simply checking the identification code.
This required a means for identifying whether it was a SAT signal or not. Therefore, the circuit scale has increased and it has been difficult to integrate the circuit.

Also, it is possible to prepare a type of reference signal corresponding to the type of SAT signal, select it according to the received identification code, and use it as the reference signal for the DPLL section 55, but it is possible to prepare a type of reference signal corresponding to the type of SAT signal, and select it according to the received identification code. Since it is necessary to provide an oscillator for each generation, there is a drawback that the size increases and the cost increases.

The present invention uses a single master clock to
The purpose of this is to form reference signals of different frequencies necessary for reception detection of SAT signals with a simple configuration.

[Means for solving problems]

The reference signal generation circuit for SAT detection of the present invention will be explained with reference to the principle block diagram shown in FIG. A frequency division counter 2 that counts the master clock by a predetermined number and outputs a signal.
and a delay circuit 3 that delays the output signal of the frequency dividing counter 2 by a period of 1/2 of the synchronization of the master clock.
For each period in which the output signal of the frequency division counter 2 is obtained by adding the output signal of the frequency division circuit 1 and the output signal of the delay circuit 3, a signal with one pulse inserted, a signal with one pulse removed, and a pulse 3 with signals without insertion/removal
It is equipped with a pulse insertion/removal circuit 4 that forms different types of signals, and a selector 5 that decodes an identification code with a decoder 6 and selects the output signal of the pulse insertion/removal circuit 4 based on the decoded output signal. The signal selected and output by the selector 5 is added as a reference signal for a digital phase synchronization circuit that synchronizes the phase of the received SAT signal.

[Effect]

Frequency divider circuit 1 uses the master clock at a duty rate of 50%.
This pulse is counted a predetermined number by the frequency dividing counter 2, and a signal is output for each count. The pulse insertion/removal circuit 4 performs logical processing on the output signal of the frequency dividing circuit 1 and the output signal of the delay circuit 3 to generate a signal in which one pulse is inserted, a signal in which one pulse is removed, and a signal in which no pulse is inserted or removed. Three types of signals are formed. If the predetermined number of the frequency dividing counter 2 is m and the frequency of the master clock is F, then the pulse insertion/removal circuit 4
, a signal with a frequency of F(m+1)/m and a signal with a frequency of F(m+1)/m,
Three types of signals are formed and output: a signal with a frequency of (m-1)/m and a signal with a frequency of Fm/m. These three types of signals are selected using identification codes and become reference signals for the digital phase synchronization circuit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention,
21 is a reference signal generation circuit, 22 is a DPLL section (digital phase synchronization circuit section), and 23 is a lock detection section. A master clock and identification codes DCC1 and DCC2 are added to the reference signal generation circuit 21, and with the master clock as a reference, it generates a signal with one pulse inserted at every predetermined period, a signal with one pulse removed, and a pulse insertion/removal signal. Three types of signals are formed, including a zero signal and a 2-bit identification code DCC1,
One of the three types of signals is selected by the DCC 2 and becomes a reference signal to the DPLL unit 22. In other words, signals with three different frequencies are generated from a single master clock, and one of them is assigned the identification code DCC.
1, which is selected by DCC2 and used as a reference signal.

The DPLL unit 22 has identification codes DCC1 and DCC2.
The reference signal of the frequency selected by
The received SAT signal and the output SAT signal are applied to a lock detection circuit 23 to detect phase synchronization in the DPLL section 22. That is, receiving
If the SAT signal and the output SAT signal continue to be the same, the phase synchronization pull-in state is established, and a synchronization pull-in signal is output to indicate that the correct SAT signal has been received.

FIG. 3 is a block diagram of a reference signal generation circuit according to an embodiment of the present invention, in which the same reference numerals as in FIG. , 13 is an inverter, 14 is an exclusive OR circuit, and 15 is an OR circuit. The frequency dividing circuit 1 is composed of a flip-flop 11, and has a master clock C connected to a clock terminal C.
is applied, the terminal and data terminal D are connected, and a signal a whose frequency is divided by 1/2 is output from the Q terminal.The master clock c is frequency-divided and becomes a signal a with a duty of 50%. It is applied to the frequency division counter 2 and the pulse insertion/extraction circuit 4.

The frequency division counter 2 counts the signal a by a predetermined number and outputs the signal b. For example, if the master clock c is 1.92MHz, the frequency is divided by half by the frequency division circuit 1 and a signal of 0.96MHz is generated. If the predetermined number of the frequency dividing counter 2 is 200, the signal b is output every time the signal a is counted by 200, thereby dividing the frequency by 1/200, 4.8 The pulse signal b has a repetition frequency of KHz.

The delay circuit 3 is composed of a flip-flop 12 and an inverter 13, the master clock c is inverted by the inverter 13, the inverted signal d is applied to the clock terminal C of the flip-flop 12, and the output signal of the frequency division counter 4 is applied to the data terminal. b is added. Therefore, the output signal e of the Q terminal divides the output signal b of the frequency dividing counter 2 into the master clock c.
It is delayed by 1/2 of the period of . This signal e is applied to the pulse insertion/removal circuit 4 together with the output signal a of the frequency dividing circuit 1.

The pulse insertion/removal circuit 4 is composed of an exclusive OR circuit 14 and an OR circuit 15.
The output signal f is a signal obtained by inserting one pulse for each output signal b of the frequency dividing counter 2, and the OR circuit 15
The output signal g is a signal obtained by removing one pulse from each output signal b of the frequency division counter 2. Also frequency dividing circuit 1
By outputting the output signal a as it is, a signal without pulse insertion/removal can be obtained. Therefore, the pulse insertion/removal circuit 4 is an exclusive OR circuit 14
With a simple circuit configuration of the OR circuit 15, it is possible to form and output three types of signals: a signal with one pulse inserted every predetermined period, a signal with one pulse removed, and a signal without pulse insertion/removal. .

2-bit identification codes DCC1, DCC2,
The relationship with the SAT signal is, for example, 5970 by “00”
Hz, “01” means 6000Hz, “10” means 6030Hz.
This identification code specifies the SAT signal, and “11” specifies prohibition of sending the reference signal.
DCC1 and DCC2 are decoded by a decoder 6. In cases other than when prohibition is indicated, the selector 5 is controlled by the output signal of the decoder 6, and one of the three types of signals from the pulse insertion/removal circuit 4 is selected and output, and the output signal is output from the DPLL section 22 (see Fig. 2). ) will be added to Further, when the identification code is "11", the output signal of the decoder is added to the inhibition circuit 7, and the output of the reference signal is inhibited.

FIG. 4 is an explanatory diagram of the operation of the embodiment of the present invention,
a to g show examples of signals a to g of each part in FIG. 3. Assuming that the 1.92 MHz master clock c is shown in FIG. If the signal a is counted 200 times by the frequency division counter 2 and the signal b is output as shown in b in FIG.
The signal d inverted by 3 becomes the one shown in d of FIG. As shown in FIG. 4, the rising edge is shifted by 1/2 of the period T of the master clock c. Therefore, the output signal e of the Q terminal of the flip-flop 12 is different from the output signal of the frequency division counter 2, as shown in e of FIG. b is delayed by a period τ that is 1/2 of the period of master clock c.

This signal E and the output signal a of the frequency dividing circuit 1 are applied to the pulse insertion/removal circuit 4, and the output signal f of the exclusive OR circuit 14 is outputted as a divided pulse as shown in f in FIG. Therefore, within the period in which signal a is counted 200 times, there will be one more pulse,
In addition, the output signal g of the OR circuit 15 outputs two consecutive pulses as shown in g in FIG.
The result is a signal with fewer pulses. Therefore, the signal without pulse insertion/removal is 960KHz, the output signal f of the exclusive OR circuit 14 is 960×201/200=964.8KHz, and the output signal g of the OR circuit 15 is 960×199/200=
It becomes 955.2KHz.

In the DPLL section 22 (see Figure 2), when the reference signal and the received SAT signal are phase synchronized, a frequency divider is provided and a phase comparator is used when the frequency of the reference signal is an integral multiple of the received AST signal. The frequency used for phase comparison in both cases is the same. If this frequency divider divides the frequency by /16, the identification code
When DCC1 and DCC2 are “00”, the SAT signal is
The selector 5 selects the 955.2KHz signal g from among the three types of signals in the pulse insertion/removal circuit 4, and it becomes the reference signal for the DPLL section 22.
The 955.2KHz reference signal is converted to 1/1 in the DPLL section 22.
By dividing the frequency by 16, it becomes a 5970Hz signal, so the correct reception specified by the identification code "00" is possible.
Phase synchronization with the SAT signal can be achieved.

Also, if the identification code is “01”, use selector 5.
The 960KHz signal is selected and becomes the reference signal for the DPLL section 22, and this reference signal is divided into 1/16.
Since it is a 6000Hz signal, it can be phase synchronized with the received SAT signal specified by the identification code "01". Also, when the identification code is "10", the selector 5 selects the 964.8KHz signal f, and the DPLL
The signal becomes a reference signal for the section 22, and is frequency-divided by 1/16 in the DPLL section 22 to become a signal of 6030 Hz. Therefore, phase synchronization can be achieved with the received SAT signal designated by the identification code "10".

Although the pulse insertion/removal circuit 4 is shown as being composed of an exclusive OR circuit 14 and an OR circuit 15, it is of course possible to construct it using other logic gate circuits depending on the logic level, etc. be. Further, the frequency division counter 2 can have a frequency division ratio other than 1/200 depending on the relationship between the frequency of the master clock c and the frequency of the reference signal.

In addition, in the above-mentioned example, the case where it is applied to the detection of SAT signal in a car phone is shown, but it is not applicable to any system that transmits information based on the presence or absence of a three-frequency Toan signal. It is something to which the invention can be applied.

〔Effect of the invention〕

As explained above, the present invention provides a reference signal for a digital phase synchronization circuit when receiving and detecting a three-frequency tone signal such as a SAT signal in a car telephone system or the like. A frequency dividing signal a is obtained by dividing a single master clock c by a frequency dividing circuit 1, and this frequency dividing signal a is counted by a predetermined number by a frequency dividing counter 2. The pulse insertion/extraction circuit 4 uses the pulse insertion/extraction circuit 4 to insert/unload the frequency-divided signal a by using the delay signal e which is obtained by delaying the signal b output by the delay circuit 3 by a period of 1/2 of the period of the master clock c. No signal, and divided signal a
The logical sum output of the frequency-divided signal a and the delayed signal e is used as a pulse deletion signal, and the exclusive logical sum output of the divided signal a and the delayed signal e is used as a pulse insertion signal.
DCC1 and DCC2 are decoded by a decoder 6, and the selector 5 is controlled by the decoded output signal to generate a signal for no pulse insertion/extraction, a signal for pulse deletion, and a signal for pulse insertion, which are formed in the pulse insertion/extraction circuit 4. This system selects and outputs one of three types of signals as a reference signal, and can output multiple reference signals of different frequencies without providing multiple master clock oscillators. Moreover, since it can be configured with a digital circuit, it has the advantage that it can be easily integrated into an integrated circuit.

In addition, as a configuration of the logic processing of the pulse insertion/removal circuit 4,
In the embodiment, an OR circuit 15 for obtaining an OR output in the case of positive logic and an exclusive OR circuit 14 for obtaining an exclusive OR output are provided, but in the case of negative logic, an OR circuit 15 is provided. It can be configured with a corresponding logic gate circuit.

Also, the DPLL section 2 to which the selected reference signal is added
2, the identification code is determined depending on whether or not it is in phase synchronization with a 3-frequency tone signal such as a received SAT signal.
There is an advantage that it is possible to easily identify whether the signal is a three-frequency tone signal such as a SAT signal designated by DCC1 or DCC2.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of a reference signal generation circuit of an embodiment of the present invention, and FIG. 4 is a block diagram of an embodiment of the present invention. FIG. 5 is a block diagram of a conventional example. 1 is a frequency dividing circuit, 2 is a frequency dividing counter, 3 is a delay circuit, 4 is a pulse insertion/removal circuit, 5 is a selector, 6 is a decoder, 7 is an inhibition circuit, 8 is a reference signal output terminal, 11 and 12 are flip-flops. , 13 is an inverter, 14 is an exclusive OR circuit, and 15 is an OR circuit.

Claims (1)

[Claims] 1. In a reference signal generation circuit for detecting three-frequency tone signals, which selects and adds a reference signal corresponding to an identification code to a digital phase synchronization circuit for detecting three tone signals with different frequencies. a frequency dividing circuit 1 that divides the frequency of the master clock by 1/2 and outputs a frequency-divided signal; a frequency-dividing counter 2 that counts the frequency-divided signal by a predetermined number and outputs a signal; a delay circuit 3 that outputs a delayed signal in which the output signal is delayed by a period of 1/2 of the period of the master clock; the frequency-divided signal is a signal without pulse insertion/removal; and the logic between the frequency-divided signal and the delayed signal is determined. A pulse insertion/extraction circuit 4 which uses a sum output as a pulse deletion signal and outputs an exclusive OR output of the frequency division signal and the delayed signal as a pulse insertion signal; , pulse deletion, and pulse insertion, and a decoder 6 that controls the selector 5 by a decoded output signal of the identification code. Reference signal generation circuit for tone signal detection.