JPH0370415B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel-to-serial converter having two functions: converting a serial input into a parallel output and converting a parallel input into a serial output.

[Conventional technology]

Serial/parallel converters that convert serial input to parallel output or parallel/serial converters that convert parallel input to serial output are used in many digital devices. By the way, these converters include those that perform only parallel/serial conversion, those that perform only serial/parallel conversion, and those that perform both.
There is one shown in Publication No. 117190.

This conventional technology applies a serial transmission method to communication between CPUs, and is a shift register that is connected in series to a data transmission line and has an input terminal, an output terminal, and a terminal for a load signal indicating the timing of data acquisition. It is equipped with a latch circuit that stores and holds the output data of the shift register in response to a load signal.When receiving data from another CPU, the shift register converts serial data into parallel data. The data is converted and stored in a latch circuit, and when data is to be sent to another CPU, parallel data is set in a shift register and transmitted serially.

[Problem that the invention seeks to solve]

However, this prior art requires a circuit for taking in parallel data in response to a load signal as a configuration of the shift register, resulting in a problem that the configuration of the shift register becomes complicated and the cost increases.

The present invention solves these problems, and provides a parallel-to-serial converter whose configuration is simplified and costs are reduced by devising connections between input and output terminals for parallel data. The purpose is to

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention consists of flip-flops connected in series for each bit, and data is transmitted sequentially from the previous bit to the subsequent bit in synchronization with a clock signal. A latch circuit that latches data set in each bit of the shift register in response to a strobe signal and outputs it to an output terminal, and each output terminal of the latch circuit is connected to a parallel output terminal. Either the data latched in the latch circuit is output as a parallel signal, or the parallel input terminal is connected to each input terminal of each flip-flop of the shift register, and each bit of the input parallel signal is input to each bit of the shift register. The present invention is characterized by comprising a switching means for switching between setting and setting.

[Effect]

When performing serial/parallel conversion, the switching means connects the parallel output terminal to each output terminal of the latch circuit. Then, when serial data is input to the shift register in synchronization with the clock signal and a strobe signal is applied to the latch circuit, the data of each bit of the shift register is latched into the latch circuit, and the latched data is transferred to the parallel output terminal. given to.

On the other hand, when performing parallel/serial conversion, the parallel input terminal is connected to the input terminal of a flip-flop that constitutes the bit of the shift register. When a clock signal is input to the shift register, parallel data input from the parallel input terminal is set in the shift register.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention, where 1 is an 8-bit shift register, 2 is an 8-bit shift register, and 2 is an 8-bit shift register.
Bit-configured latch circuit, 3 is a switching circuit, 11-
18 is a D flip-flop that constitutes the shift register 1; 21 to 28 are D flip-flops that constitute the latch circuit 2;
Flip-flop, 31 to 38 are tri-state buffers forming the switching circuit 3, 41 is a serial input terminal to which a serial signal is input, 42 is a clock terminal to which a clock signal is input, 43 is a serial output to which a serial signal is output. Terminal, 44-
1 to 44-8 are parallel output terminals to which parallel signals are input or output, 45 is an input terminal for switching signals, and 46 is a strobe terminal to which strobe signals are input.

When operating the circuit shown in the figure as a parallel/serial converter, the switching signal applied to the switching signal input terminal 45 is set to "1", and when operating as a serial/parallel converter, the switching signal is set to "0".
The operation in each case is as follows.

(1) When operating as a parallel/serial converter By setting the switching signal applied to the switching signal input terminal 45 to "1", the b sides of the tri-state buffers 31 to 38 forming the switching circuit 3 are turned on. , parallel input/output terminals 44-1 to 4
By adding each bit of the parallel signal to 4-8, each bit of the parallel signal is set in the D flip-flops 11-18 constituting the shift register 1, and is shifted in synchronization with the clock signal applied to the clock terminal 42. One bit is output from the serial output terminal 43.

(2) When operating as a serial/parallel converter By setting the switching signal applied to the switching signal input terminal 45 to "0", the a sides of the tristate buffers 31 to 38 forming the switching circuit 3 are turned on. In this state, serial input terminal 4
1 and a serial signal, each bit of the serial signal is sequentially shifted by a clock signal synchronized with the serial signal. Then, by setting the strobe signal applied to the strobe terminal 46 to "1" at the timing when the first bit of the serial signal is set in the D flip-flop 18 constituting the shift register 1, the serial signal set in the shift register 1 is set to "1". Each bit is set in the D flip-flops 21 to 28 that constitute the latch circuit 2, and the Q terminal output thereof is outputted to the parallel input/output terminals 44-1 to 44-8 via the a side of the tristate buffers 31 to 38. be done.

FIG. 2 is a block diagram of another embodiment of the present invention, in which 51 is an 8-bit shift register;
1 is an 8-bit latch circuit, and 53 and 54 are switch circuits, in which when one is in the on state, the other is in the off state. Further, 55 is a serial output terminal that outputs a serial signal, 56 is a clock terminal, 57 is a serial input terminal to which a serial signal is applied, 58 is a switching signal input terminal, 59 is a strobe terminal, 60 is a parallel output terminal, and 61 is a parallel This is an input terminal.

When the circuit shown in the figure is operated as a parallel/serial converter, the switching signal applied to the switching signal input terminal 58 is set to "1", and the switching signal for operating the circuit as a serial/parallel converter is set to "0". , the operation in each case is as follows.

(1) When operating as a parallel/serial converter Setting the switching signal to “1” turns on the switch circuit 54, so by applying a parallel signal to the parallel input terminal 61, each bit of the parallel signal is shifted. The bits are set in each bit of the register 51, shifted in synchronization with the clock signal applied to the clock terminal 56, and output one bit at a time from the serial output terminal 55.

(2) When operating as a serial/parallel converter By setting the switching signal to "0", the switch circuit 53 is turned on. In this state, when a serial signal is applied to the serial input terminal 57, each bit of the serial signal is sequentially shifted by a clock signal synchronized with the serial signal. Then, when the first bit of the serial signal reaches the output stage of the shift register 51, the strobe terminal 5
By setting the strobe signal applied to 9 to "1", each bit of the shift signal set in each bit of the shift register 51 is latched by the latch circuit 52, and is outputted to the parallel output terminal 60 via the switch circuit 53. Ru.

〔Effect of the invention〕

As explained above, in the present invention, the switching means connects each output terminal of the latch circuit to the parallel output terminal to output the data latched in the latch circuit as a parallel signal, or connects the parallel input terminal to the shift register. The shift register is connected to each input terminal of each flip-flop to switch whether each bit of the input parallel signal is set to each bit of the shift register, so the shift register receives the clock signal necessary to shift the bit data. Since the data is set by , it is not necessary to provide the shift register with a circuit for a load signal, and therefore the structure of the shift register can be simplified and the cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and
FIG. 2 is a block diagram of another embodiment of the invention. In the figure, 1, 51...shift register, 2,
52...Latch circuit, 3...Switching circuit, 11-18,
21-28...D flip-flop, 31-38...
Tri-state buffer, 53, 54...switch circuit.

Claims (1)

[Scope of Claims] 1. A shift register in which each bit is constituted by flip-flops connected in series and transmits data sequentially from a previous bit to a subsequent bit in synchronization with a clock signal; and a strobe. A latch circuit that latches the data set in each bit of the shift register in response to a signal and outputs it to an output terminal, and a latch circuit that connects each output terminal of the latch circuit to a parallel output terminal so that the data is latched by the latch circuit. A switch for switching between outputting the input data as a parallel signal, or connecting the parallel input terminal to each input terminal of each flip-flop of the shift register and setting each bit of the input parallel signal to each bit of the shift register. A parallel-to-serial converter characterized by comprising means.