JPH0370815B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory content destruction detection device, and particularly to a device for detecting memory content destruction, and particularly for detecting whether or not the memory content of a small external storage device attached to a main unit including a central processing unit is destroyed. The present invention relates to a device for detecting.

Description of the Prior Art Conventionally, floppy disk devices and the like have often been used as external storage devices for data processing devices such as microcomputers. However, this floppy disk device had the drawbacks of being large and expensive. In order to overcome these drawbacks, a storage means (hereinafter referred to as a memory cassette) in which a CMOS-RAM is housed in a cassette has been proposed. This memory cassette is removable from the main body of the data processing device.
Inside is a semiconductor memory and a battery for backing up the contents of the semiconductor memory.

By the way, in the above-mentioned memory cassette, when the built-in battery is exhausted, the contents of the memory may be destroyed. Furthermore, due to carelessness in handling, the contents of the memory or the memory itself may be destroyed. However, it has not been possible to easily know whether the contents of the memory or the memory itself has been destroyed. Therefore, there was a risk that the memory cassette could be inserted into the data processing device without knowing that the stored contents of the memory or the memory itself had been destroyed. In this case, a malfunction occurs in the data processing device.

OBJECTS OF THE INVENTION An object of the present invention is to provide a storage content destruction detection device that can easily detect that the storage contents of a memory cassette have been destroyed and can prevent malfunctions of the main unit.

Summary of the Invention In summary, when it is detected that the storage means is attached to the main body device, the present invention checks whether or not the memory contents of the storage means have been destroyed, and if so, notifies the outside. It was designed to do so.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 is an external perspective view of an embodiment of the present invention. A receiving portion 1 into which a memory cassette 5 is mounted is formed on, for example, an operation panel of a data processing device. A lid 2 is attached to the receiving portion 1 so as to be openable and closable. Further, a micro switch 4 is provided to detect whether the lid 2 is opened or closed. That is, when the lid 2 is closed, the switch 4 is turned on. A connector jack 3 is provided on the side surface of the receiving portion 1, into which a plug 6 exposed to the outside from the memory cassette 5 is inserted and coupled.

On the other hand, the plug 6 of the memory cassette 5 is connected to the address line of the CMOS-RAM stored in the cassette.
A data line, a power supply line, and a terminal (connected to the power supply) used to detect the presence or absence of the memory cassette 5 are led out.

When using the memory cassette 5 as an external storage device for a data processing device, an operator places the desired memory cassette 5 into the receiving portion 1, inserts and connects the plug 6 into the connector jack 3, and closes the lid 2.

FIG. 2 is a block diagram of one embodiment of the present invention. The CPU 10, ROM 11, RAM 12, and I/O port 13 are connected by a data bus 20 and an address bus 21, respectively. ROM1
1 stores a data check program (check sum) for the memory cassette 5 in addition to the original processing program of the data processing device.
The RAM 12 is provided with a register A in addition to various buffers of the data processing device. This register A stores the data check result of the memory cassette 5. I/O port 13 has
A notification circuit 15 including a lamp or a buzzer is connected. Further, a flip-flop (F/F) 14 is connected to the I/O port 13. That is, from the I/O port 13 to the flip-flop 14
A reset input signal is applied to the reset input terminal of the flip-flop 14 to the I/O port 13.
Q output (set output) is given to Note that the set input terminal of this flip-flop 14 is
The aforementioned microswitch 4 is connected, and the flip-flop 14 is set by the falling signal when the switch 4 is turned on. Further, a cassette attachment signal from the memory cassette 5 is applied to the I/O port 13. On the other hand, memory cassette 5
Connector jack 3 has the aforementioned data bus 2.
0, address bus 21 and power supply 16 are connected.

FIG. 3 is a flowchart showing a data check program for the memory cassette 5 stored in the ROM 11 shown in FIG. The operation of an embodiment of the present invention will be described below with reference to FIG.

The operation program shown in FIG. 3 is processed as an interrupt operation. That is, when the operator attaches a new memory cassette 5 to the receiver 1 and closes the lid 2,
Flip-flop 14 is set. The set output, ie, the Q output, from the flip-flop 14 is supplied to the CPU 10 via the I/O port 13, and the processing shown in FIG. 3 starts.

First, in step 1 (abbreviated as S in the figure), it is determined whether the memory cassette 5 is actually installed. This determination is made by detecting a cassette attachment signal supplied from the memory cassette 5 via the I/O port 13. If the memory cassette 5 is not installed, the memory contents cannot be checked.
The process advances to step 2, where the flip-flop 14 is reset and the interrupt processing ends. On the other hand, if the memory cassette 5 is installed, the process advances to step 3 and the flip-flop 14 is reset. Then, in step 4, the data stored in the memory cassette 5 is sequentially and unconditionally read out, and in step 5, checksum processing is performed. This checksum processing, as is well known, involves calculating, for example, the total number of "1" bits in data. The data resulting from the checksum processing (check data) is
It is transferred to register A of RAM 12 and stored.
Subsequently, in step 7, check data previously stored in the memory cassette 5 is read out.
This check data is the result of checksum processing performed in advance when writing data to the memory cassette 5, and is stored in a fixed area of the memory cassette 5. Next, in step 8,
It is determined whether the check data stored in register A and the check data read from memory cassette 5 match. If the check data do not match, it indicates that the data in the memory cassette 5 has been destroyed. Therefore, in step 9, the notification device 1 notifies the operator that the data in the memory cassette 5 is invalid.
Do this according to step 5. On the other hand, if the check data match, the data in the memory cassette 5 is valid, and the CPU 10 shifts to other processing.

In addition, instead of the micro switch 4, when installing the memory cassette 5, the power supply 1 of the data processing device is
The connection between the terminal connected to the power source 16 (lead out to the connector 13) and the power source 16 may be detected.

Furthermore, as the notification means, one that displays characters may be used.

Note that various methods have been considered for checking the data contents, such as a parity error check, and any method may be used.

Effects of the Invention As described above, according to the present invention, when the storage means is attached to the main body device, it is checked whether or not the memory contents of the storage means are destroyed, and if the contents are destroyed, a notification is sent to the outside. Therefore, the operator can not only easily know that data has been destroyed, but also can prevent malfunctions of the main unit.

[Brief explanation of drawings]

FIG. 1 is an external perspective view of one embodiment of the present invention. FIG. 2 is a block diagram of one embodiment of the present invention. FIG. 3 is a flowchart showing a data check program for the memory cassette stored in the ROM shown in FIG. In the figure, 1 is a receiving part, 4 is a micro switch, 5 is a memory cassette, 10 is a CPU, and 11 is a
ROM, 12 is RAM, and 15 is a notification device.

Claims (1)

[Scope of Claims] 1. It is configured to be detachably attached to a main unit including at least a central processing unit, and includes a semiconductor memory for storing information and a power supply for retaining the contents stored in the semiconductor memory. A device for detecting whether or not the memory contents of the storage means have been destroyed in a storage means such as a storage means, comprising: means for detecting that the storage means is attached to the main body device; means for checking whether or not the storage contents of the storage means have been destroyed in response to the detection of the content; and notification means for notifying the outside in response to the detection of the destruction by the checking means; Memory content destruction detection device.