JPH0370851B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a pilot signal generation circuit in a tracking system of a magnetic recording/reproducing apparatus (hereinafter referred to as VTR), and in particular to a pilot signal generation circuit for tracking control and a head switching signal (HSW).
This relates to a circuit that generates timing pulses such as signals. Conventional configuration and its problems In recent years, the density of VTRs has increased, and the width of the recorded magnetization locus (track width) has become increasingly narrower. Ideally, tracks should be recorded linearly on a magnetic tape, but in reality, tracks are recorded with a unique curvature for each deck due to variations in mechanical precision. For this reason, when performing compatible playback in which a magnetic tape recorded on one deck is played back on another deck, the inherent bending difference between the two decks cannot be corrected using control using conventional control signals. , the playback quality deteriorates accordingly. This problem becomes more serious as the track width becomes narrower. In order to solve such a problem, if it is possible to obtain a tracking error signal corresponding to track bending, then according to this error signal,
What is necessary is to displace the rotary head in the direction of the rotation axis. As a method of displacing the rotary head in the direction of the rotation axis, a method using an electro-mechanical transducer composed of a piezoelectric element is well known, and its explanation will be omitted here. By the way, as a method of obtaining a tracking error signal corresponding to the above-mentioned track curvature, there is a method of using a pilot for tracking control (hereinafter simply referred to as a pilot signal). In this method, a pilot signal is recorded superimposed on a video signal, and during playback, the amount of deviation of the scanning head with respect to the recorded magnetization trajectory (track) is determined using the pilot signal that is reproduced as a crosstalk signal from an adjacent track.
This is a method of knowing the direction of deviation. The method for detecting tracking error signals using pilot signals is as follows:
Various methods have been proposed, ranging from a method using one type of pilot signal to a method using four types of pilot signals (four-frequency pilot signals). Purpose of the Invention The present invention provides a circuit that generates the signals f ₁ , f ₂ , f ₃ , and f 4 shown in Table 1 below, which is used in a tracking method using 4-frequency pilot signals (hereinafter referred to as ₄ -frequency tracking method). Contains. Note that the present invention is not directly related to the four-frequency tracking method, so a description thereof will be omitted.

[Table] However, _fH is the horizontal synchronization frequency (line frequency). Since the tracks are directly adjacent to each other, each head must be aligned in the correct relationship to each other when recording. However, there are errors due to hysteresis of the electro-mechanical transducer mentioned above, and a permanent stationary state does not occur between the heads during recording, so it is necessary to control the relative positions of the heads during recording. . The required control signals are obtained by periodic measurements during a short period at the beginning of each track. This measurement was recorded with an _f5 signal at a frequency of about 228KHz for a period of about one line,
During the next approximately one line period, it switches to regeneration and f ₅
The signal obtained from the previous track on which the signal was stored is reproduced and its amplitude is measured. Compare the measurement results from each head and make sure they are equal.
It is sufficient to control the relative position of the heads. Furthermore, the f ₅ signal is used as a second reference signal (f ₅ CK),
The recording head switching pulse (REC/HSW ₁ ) (REC/HSW 1) starts from the VTR's PG signal.
HSW ₂ ), head switching pulse for playback (PB/HSW), _f5 recording timing pulse ( _f5 REC) and _f5 for head relative position control mentioned above.
The reproduction timing pulse (f ₅ PB) can be generated as a pulse having an accurate pulse period using a counter circuit or the like. One possible means of obtaining the four-frequency pilot signals f ₁ to _{f 4} shown in Table 1 with accurate values is to use four oscillation circuits, but this has disadvantages such as high cost. Another method is to provide one reference oscillation circuit having a common multiple of four frequencies and generate a four-frequency pilot signal using a frequency dividing circuit. This method is advantageous in that the variable oscillation circuit for correcting jitter in the reproduced color signal can also be used as the reference signal (CLK) oscillation circuit, and its value can be selected to 378f _H. As mentioned above, when the reference signal (CLK) is 378f _H ,
If this is divided into 1/58, 1/50, 1/40, and 1/36, the results in Table 1 above correspond to these division ratios.
f ₁ , f ₂ , f ₃ , and f ₄ are obtained. It is also used to control the relative position of the heads.
The _f5 signal is also obtained by dividing the reference signal (CLK) by 1/26. Furthermore, each required timing pulse can be obtained by using a counter circuit, a decoding circuit, etc., using the f ₅ signal as the second reference signal (f ₅ CK). The first object of the present invention is to create a four-frequency pilot signal from one reference signal (CLK) by sequentially switching one counter and changing the frequency division ratio, and using another counter to generate a four-frequency pilot signal. Create an _f5 signal from the first reference signal (CLK), and use this _f5
The object of the present invention is to provide a means for creating a timing pulse group whose phase error is suppressed to the accuracy of the reference signal (CLK) by using the signal as the second reference signal (f ₅ CK). The second purpose is to output the 4-frequency pilot signal and the f ₅ signal as continuous waves, or to output the 4-frequency pilot signal as an f ₅ recording timing pulse (f ₅ REC) and
The _f5 signal is output as an intermittent wave with an average DC level only during the f5 reproduction timing pulse ( _{f5PB )} .
Means for outputting an intermittent wave only during the _f5 recording timing pulse ( _f5 REC) period and high impedance for other periods, and means for mixing the _f5 signal with a 4-frequency pilot signal output as an intermittent wave. It is about providing. Structure of the Invention In order to achieve the above object, the pilot signal generation circuit of the present invention divides the frequency of a first reference signal and generates pilot signals of four different periods in phase synchronization with the rotational phase of the rotary head for use in tracking during reproduction. a four-frequency pilot signal generation circuit that generates
a fifth pilot signal ( _f5 signal) which is synchronized with the rotational phase of the rotary head and is used to control the head height during recording.
an _f5 signal generation circuit; and a timing pulse generation circuit that uses the _f5 signal as a second reference signal to generate head switching pulses for recording and reproduction and recording and reproduction timing pulses for the _f5 signal. It is the composition. DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a pilot signal generation circuit. The reference signal (CLK) of _378fH is generated by 4-frequency pilot signal generation circuit 1, _f5 generation circuit 2, and
The signal is supplied to the PG edge detection circuit 3. The four-frequency pilot signals _f1 to _f4 , which are the outputs of the four-frequency pilot signal generation circuit 1, are supplied to the pilot signal output circuit 4, and the pilot signal output circuit 4 is supplied with an _f5 recording timing pulse ( _f5) . REC) and
The f ₅ regeneration timing pulse (f ₅ PB) and the output control signal (CNT) are supplied, and the pilot signal f ₁
The output of ~ _f4 is controlled to be a continuous wave or an intermittent wave. The _f5 signal that is the output of the _f5 generation circuit 2 is supplied to the _f5 output circuit ₅ , which also receives the _f5 recording timing pulse ( _f5 REC) and the output control signal ( CNT) is supplied and controlled so that the output of the _f5 signal is a continuous wave or an intermittent wave. The _f5 signal output from the _f5 inventive circuit 2 is supplied as a second reference signal ( _f5CK ) to the timing pulse generation circuit 6, and as the output of this timing pulse generation circuit 6, it is applied to the two recording heads. Switching pulse (REC/HSW ₁ )
(REC/HSW ₂ ), reproduction head switching pulse (PB/HSW), f ₅ recording timing pulse (f ₅ REC), and f ₅ reproduction timing pulse (f ₅ PB) are obtained. . The regeneration head switching pulse (PB/HSW)
is fed back to the 4-frequency pilot signal generation circuit 1 as a switching signal that sequentially switches the _4- frequency pilot signals f1 to _f4 , and the _f5 recording timing pulse ( _f5 REC) is sent to the pilot signal output circuit 4 and the _f5 output circuit. 5 and the f ₅ reproduction timing pulse (f ₅ PB) are fed back to the pilot signal output circuit 4, respectively. A PG signal is supplied to the PG edge detection circuit 3, and the detected PG edge is supplied as a reset signal to the _f5 generation circuit 2 and as an operation start signal to the timing pulse generation circuit 6. FIG. 2 shows a specific circuit example of the 4-frequency pilot signal generation circuit 1 and the pilot signal output circuit 4.
3 and 4 are waveform diagrams of various parts of the circuit shown in FIG. 2. In addition, Figure 3 shows CNT=Low or CNT・
This is the signal waveform when f ₅ REC・₅ = High, and Fig. 4 shows the signal waveform when viewed at a period several hundred times longer than l ₁ + l ₂ . , i are the signals g, shown in FIG.
This is a continuous wave of h and i waveforms. A reference signal (CLK) is supplied from terminal 7.
8 is a programmable counter (hereinafter referred to as 4-frequency counter), which converts the reference signal (CLK) to (l ₁ +
l ₂ ) Generate a pulse every time it counts to obtain an output signal a, and use this output signal a to control the 4-frequency counter 8.
As shown in FIG. 3, the output signal a becomes a repetitive pulse with a period of (l ₁ +l ₂ ). The output signal b of the 4-frequency counter 8 is obtained by generating a pulse every time the reference signal (CLK) is counted by ₁ , and the period from output signal a to output signal b is as shown in Fig. 3. becomes l ₁ . 9 is a reset flip-flop (RS
-FF), is set by output signal a, reset by output signal b, and outputs signal c. 1
0 is a T-type flip-flop (hereinafter referred to as T-FF)
and outputs a signal d. 11 and 12 are AND
It is a circuit, and the Q output (signal c) of RS-FF9,
Signals e and f are output as respective AND outputs of the Q and output (signal d and its inverted signal) of the T-FF 10. 13 to 16 are NAND circuits, the signal e is sent to the NAND circuits 13 and 14, and the signal f is sent to the NAND circuits 13 and 14.
is supplied to NAND circuits 15 and 16. on the other hand,
The output control signal (CNT) is inverted by the inverter 17, and the inverted signal () is sent to the NAND circuits 13 and 1.
5, and the output control signal (CNT) is
An inverted signal ( ₅ ) in which the f5 recording timing pulse ( _f5 REC) is inverted by the inverter 18 and _an inverted signal ( ₅ ) in which the _f5 reproduction timing pulse ( _f5PB ) is inverted by the inverter 19 are connected to the AND circuit 2.
0 and the output of the AND circuit 20 (CNT・₅・₅ ) is supplied to the AND circuits 14 and 16.
is supplied to Furthermore, the outputs of the NAND circuits 13 and 14 are sent to the NAND circuit 21, and the outputs of the NAND circuits 15 and 14 are sent to the NAND circuit 21,
The output of 16 is supplied to the AND circuit 22, and the NAND
The signal g which is the output of the circuit 21 and the AND circuit 22
The signal h which is the output of is as follows. ○B When CNT=Low (Area A in Figure 4) CNT=High CNT・f ₅ REC・f ₅ PB=Low Therefore, output of NAND circuit 13 = signal e Output of NAND circuit 14 = High → signal g = Same as signal e Output of NAND circuit 15 = signal f Output of NAND circuit 16 = High
→Signal h = Same as signal f ○Ro When CNT=High, f ₅ REC・f ₅ PB=High (area B in Figure 4) CNT=Low CNT・f ₅ REC・f ₅ PB=High Therefore, NAND Output of circuit 13 = High Output of NAND circuit 14 = Signal e → Signal g = Same as signal e Output of NAND circuit 15 = High Output of NAND circuit 16 = Signal f → Signal h = Same as signal f In this case, the signals g and h are the same as in the case of ◯A, and have a repeating waveform as shown in FIG. ○C CNT=High, f ₅ REC=High or f ₅ PB=
In the case of High (area c in Figure 4) CNT=Low CNT・f ₅ REC・f ₅ PB=Low Therefore, the output of the NAND circuit 13 = High The output of the NAND circuit 14 = High → Signal g = Low The output of the NAND circuit 15 Output=High Output of NAND circuit 16=High→signal h=High. 23, 24 are electronic switches, and the signals g, h
When is high, it is connected to the power supply voltage V _DD side, and when it is low, it is connected to the ground side. Signal g=High, signal h=
When it is High, the level V _H of the output signal i is V _H =R ₁ /2 + R ₂ +R ₃ /R ₁ +2R ₂ +R ₃ ·V _DD . Also, when the signal g=Low and the signal h=Low,
The level V _L of the output signal i is V _L =R ₁ /2+R ₂ /R ₁ +2R ₂ +R ₃ ·V _DD . Further, when the signal g=Low and the signal h=High (or the signal g=High and the signal h=Low), the level of the output signal i is 1/2V _DD . Therefore, in region C of FIG. 4, the output signal i becomes a constant value 1/2V _DD . Furthermore, from the above equation, V _H −V _DD /2=V _DD /2−V _L ... or V _H +V _L = V _DD ... is established, and the signal i is from V _DD /2 to V _H A ternary waveform is obtained in which the magnitude of V _DD /2 and the magnitude from V L to V _L are equal, and a waveform with good symmetry is obtained. Although this is useful for removing harmonics of the four-frequency pilot signals f ₁ to _{f 4} , its explanation will be omitted here. FIG. 5 shows four frequencies f ₁ to f ₄ in a four-frequency counter 8 for obtaining four types of pilot signals f ₁ to f 4 .
It is a circuit diagram showing an example of a switching circuit of _f4 , and the output of the 4-frequency counter 8 is connected to the terminals (A ₁ ) to (D ₁ ) of the switch 25 and the terminal (A ₁ ) of the switch 26.
~ (D ₂ ) is supplied. switch 25, 26
are interlocked with each other, and the combinations of terminals (A ₁ ) and (A ₂ ), (B ₁ ) and (B ₂ ), (C ₁ ) and (C ₂ ), and (D ₁ ) and (D ₂ ) are The settings can be switched sequentially. The switches 25 and 26 are driven by the relationship between the reproduction head switching pulse (PB/HSW) and its 1/2 frequency divided signal (1/2 PB/HSW), and this relationship is the same as the second one below. As shown in the table.

[Table] In Table 2 above, H is High potential and L is
Indicates low potential. From Table 2 above, it can be seen that the pilot signals f ₁ to _{f 4} are sequentially switched and output for each field. Furthermore, the four-frequency pilot signals f ₁ to _{f 4} are output as the signal i waveform shown in FIG. 3, and the period thereof is (l ₁ +l ₂ )×2, so
_The pilot signal _{f 1 ,}
f ₂ , f ₄ , f ₃ are the reference signal (CLK) at 1/58 and 1/
It can be seen that the signals are frequency-divided by 50, 1/36, and 1/40, respectively. FIG. 6 shows a specific circuit example of the f ₅ generation circuit 2 and the f ₅ output signal 5, and FIGS. 7 and 8 are waveform diagrams of various parts of the circuit shown in FIG. 6. In addition, Figure 7
This is the signal waveform when CNT=Low or CNT・f ₅ REC=High, and in Figure 8, _l3 is the signal waveform when viewed at a period several hundred times longer than the signal waveform shown in Figure 4. , the shaded part of m is the third
These are continuous waves of the waveforms of the signals l and m shown in the figure. 27 is a counter (hereinafter referred to as f ₅ counter), and its output signal j is the reference signal (CLK) l ₃
It is obtained by generating a pulse every time it counts, and is configured to reset the _f5 counter 27 via the OR circuit 28 using this signal j.As shown in FIG. is a repeated pulse of l ₃ periods. Furthermore, since the _f5 counter 27 is reset via the OR circuit 28 by one PG edge every several hundred times of the signal j, the signal j is output in synchronization with the PG edge. 29 is a T-FF, which divides the frequency of the signal j by 1/2 and outputs the signal k. The Q output (signal k) of T-FF29 is
It is supplied to the NAND circuits 30 and 31, and this
The output of NAND circuits 30 and 31 is NAND circuit 3
2. On the other hand, the output control signal (CNT)
is inverted by the inverter 33, and the inverted signal () is supplied to the NAND circuit 30. Further, the output control signal (CNT) is supplied to the AND circuit 34 together with the f ₅ recording timing pulse (f ₅ REC), and the output of the AND circuit 34 is supplied to the NAND circuit 31.
supplied to Output (l) of NAND circuit 32
becomes as follows. ○D When CNT=Low (area D in Figure 8) Output of NAND circuit 30 = Signal Output of NAND circuit 31 = High
→Output signal l of NAND circuit 32 = same as signal k ○ho When CNT=High, f ₅ REC=High (area ho in Figure 8) Output of NAND circuit 30 = High Output of NAND circuit 31 = signal →NAND The output signal l of the circuit 32 is the same as the signal k. In the case of the above item ◯◯◯◯, the signal l has a repeating waveform of the waveform shown in FIG. ○ When CNT=High, f ₅ REC=Low (to the area in Figure 8) Output of NAND circuit 30 = High Output of NAND circuit 31 = High
→The output signal l of the NAND circuit 32 becomes low. 35 is an electronic switch to which signal l is input. 36 is an OR circuit, into which the output of the inverter 33 and the output CNT·f ₅ REC of the AND circuit 34 are input, and when either input is High, the output signal n of the OR circuit 36 becomes High, and the electronic switch 35 becomes It becomes ON state, and its output signal m is,
The same signal as signal l is obtained, but when both inputs of OR circuit 36 are low, signal n, which is the output of OR circuit 36, is also low, and electronic switch 35 is
It is in the OFF state, and its output m is in an open (high impedance) state (indicated by Z in region B of FIG. 8). Note that _l3 is selected as a frequency division value of 13 counts, and signal m can be obtained as a square wave signal with a duty of 50:50 by dividing the reference signal (CLK) by 1/26, and this signal m is ₅ signals. FIG. 9 shows a specific circuit example of the PG edge detection circuit 3, and FIG. 10 is a waveform diagram of each part of the circuit shown in FIG. Reference signal (CLK) is input to input terminal 7, PG
A signal is provided to input terminal 37. 38 and 39 are D-type flip-flops (hereinafter referred to as D-FF);
40 to 42 are NAND circuits, and as shown in FIG. 8, a PG edge signal can be obtained as the output of the NAND circuit 42. This circuit is generally well known and detailed explanation will be omitted. FIG. 11 shows a specific circuit example of the timing pulse generation circuit 6, and FIG. 12 shows two-channel tape patterns and waveforms of various parts of the circuit shown in FIG. 11, which have a phase relationship with each of these tape patterns. ing. 43 is an AND circuit, and the _f5 signal (using signal k in Fig. 6) is applied to this AND circuit 43.
and signal q are input, and the second reference signal (f ₅ CK) is obtained as its output. 44 is a counter (hereinafter referred to as a timing pulse counter), which uses a second reference signal (f ₅ CK) to generate each timing pulse.
count. 45 is a programmable decoder (hereinafter simply referred to as a decoder), which outputs each bit of the timing pulse counter 44 (12 to 12).
13 bits) and decode S ₁ , S ₁ ′...S ₄ and R ₁ ,
Each count signal of R ₁ ′...R ₄ and R ₄ ′ is output. _S1 ,
S ₂ , R ₁ , S ₃ , R ₂ , S ₄ , R ₄ are count signals starting from the rising edge of the PG signal (0° position of tape pattern A), and S ₁ ′, S ₂ ′, R ₁ ′, S ₃ ′, R ₂ ′,
R ₃ ′ and R ₄ ′ are count signals starting from the falling edge of the PG signal (180° position of the tape pattern). The magnitude relationship of these count numbers is as follows. S ₁ = S ₁ ′, R ₄ = R ₄ ′, S ₄ = R ₃ ′ S ₁ < S ₂ < R ₁ < S ₄ , S ₁ < S ₃ < R ₂ < S ₄ S ₁ ′ < S ₂ ′ <R′ ₁ <R ₃ ′, S ₁ ′<S ₃ ′<R ₂ ′<R ₃ ′ However, S ₂ and S 3 , R ₁ and R 2 , S _{2 ′} and S ₃ ′, R _{1 ′}
The size of each combination of R ₂ ' may be any size. Alternatively, S ₂ =S ₂ ′, R ₁ =R ₁ ′, S ₃ =S ₃ ′, and R ₂ =R ₂ ′ may be used. 46 to 50 are RS-FFs, and a decoder 4 is connected to the set terminal (2) and reset terminal R of each RS-FF.
The outputs of 5 are respectively S ₁ and R ₄ ′, S ₁ ′ and R ₄ , S ₄ and R ₃ ′,
It is input as a combination of S ₂ , S ₂ ′ and R ₁ , R ₁ ′, and S ₃ , S ₃ ′ and R ₂ , R ₂ ′, and the 12th
As shown in the figure (REC・HSW ₁ ), (REC・HSW ₂ ),
(PB・HSW), f ₅ REC), and (f ₅ PB) timing pulses are obtained. 51 is an OR circuit to which count signals R ₄ and R ₄ ' are input, and its output signal r is as shown in FIG. 52 is RS
-FF, the PG edge is input to its set terminal S, the signal r is input to its reset terminal R, and a signal q is obtained as its output. The signal q is supplied as a reset signal for the timing pulse counter 44. When the signal q is high, the timing pulse counter 44 is active, and when it is low, it is reset and the count is stopped at zero. The signal q is also supplied to the AND circuit 43, which outputs the f ₅ signal when the signal q is high (the shaded area of f ₅ CK in Fig. 12), and its output, the second The reference signal (f ₅ CK) is supplied to the timing pulse counter 44, and the above-mentioned operations are repeated. In the above operation,
A timing pulse counter 44 operates using a second reference signal (f ₅ CK) synchronized with the PG edge detected with the accuracy of the reference signal (CLK) as a reference signal.
also starts operating in synchronization with the PG edge, so the second signal, which has a longer period than the reference signal (CLK),
The scale of the counter can be reduced by using the reference signal (f ₅ CK) as the reference signal, and the reference signal (CLK)
bit errors can be suppressed with accuracy of In addition, in Fig. 12, the tape pattern I
The period from 0° to 31° and the period from 180° to 211° of the tape pattern (shaded area) apply to PCM audio,
Since it is excluded from the tracks of the video signal and pilot signal, it is necessary to create each timing pulse as described above. Also, tape pattern
The 0° position and the 180° position of the tape pattern RO have a transfer relationship that allows them to be treated equally, and these tape pattern RO's 0° to 360° are regarded as one period (corresponding to one frame), and the operation is repeated. do. FIG. 13 is a circuit diagram of a circuit that uses a resistor to mix the 4-frequency pilot signal obtained as signal i and the _f5 signal obtained as signal m, and FIG. 14 shows that CNT=High 14 is an explanatory diagram showing the relationship between the f ₅ recording timing pulse (f ₅ REC), the f ₅ reproduction timing pulse (f ₅ PB), and the waveforms of various parts of the circuit shown in FIG. 13 at the time of FIG. A portion of this circuit is shown in FIG. A signal m is supplied to the terminal 53 from the electronic switch 35 shown in FIG. 6, and the signal m and the signal i are mixed to obtain a signal i'. Typically, the value of resistor R ₄ is chosen to be small compared to resistors R ₁ , R ₂ , and R ₃ . During the f ₅ recording timing pulse (f ₅ REC) period, the f ₅ signal of the signal m is superimposed on the 1/2 _DD level of the signal i, and the signal i' changes from approximately 0 to 0 with the average value of 1/2 V _DD . This results in an f ₅ signal with an amplitude of V _DD . During the f ₅ regeneration timing pulse (f ₅ PB), the signal m has a high impedance, so the signal
i' remains at the 1/2V _DD level of signal i, and signal m has high impedance during periods other than (f ₅ REC) (f ₅ PB), so signal i' has the 4-frequency frequency of signal i. The pilot signal is output with the V _L to V _H amplitude unchanged. In this way, as shown in Figure 14,
A signal i' can be obtained by mixing the 4-frequency pilot signal and the _f5 signal, and the resistors R ₁ , R ₂ , R ₃ ,
By selecting the resistance value of R ₄ , the relative amplitude of the four-frequency pilot signal in signal i' to the f ₅ signal can be easily determined. As mentioned above, only when CNT=High, resistor _R4 is used to mix the 4-frequency pilot signal and _f5 signal, and when CNT=Low, resistor _R4 is not applied. . Effects of the Invention As explained above, according to the pilot signal generation circuit according to the present invention, most of the parts except for a simple resistor circuit in the output section can be configured with general logic circuits, and MOS Since it is suitable for making semiconductor integrated circuits (ICs), relatively large-scale circuits can be manufactured compactly and at low cost.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram of a pilot signal generation circuit, FIG. 2 is a circuit diagram of a 4-frequency pilot signal generation circuit and a 4-frequency pilot signal output circuit, and FIGS. The figure is the second
Figure 5 is a circuit diagram of the four-frequency counter switching circuit, Figure 6 is a circuit diagram of the _f5 signal generation circuit and _f5 signal output circuit, and Figures 7 and 8 are waveform diagrams of each part of the circuit shown in the figure.
The figure is a waveform diagram of each part of the circuit shown in Figure 6, and Figure 9 is a waveform diagram of each part of the circuit shown in Figure 6.
A circuit diagram of the PG edge detection circuit, Fig. 10 is a waveform diagram of each part of the circuit shown in Fig. 9, Fig. 11 is a circuit diagram of the timing pulse generation circuit, and Fig. 12 is a tape pattern and each part of the circuit shown in Fig. 11. An explanatory diagram of the relationship with the waveform. Fig. 13 is a circuit diagram of a mixer circuit that mixes the 4-frequency pilot signal and the _f5 signal. Fig. 14 shows the 4-frequency pilot signal and the _f5 signal when CNT = High and both of them. FIG. 3 is an explanatory diagram of the mutual relationship between signals and mix signals. 1... 4-frequency pilot signal generation circuit, 2...
f ₅ generation circuit, 3...PG edge detection circuit, 4...
Pilot signal output circuit, 5... f ₅ output circuit, 6
...Timing pulse generation circuit.

Claims (1)

[Scope of Claims] 1. A 4-frequency pilot signal generation circuit that frequency-divides a first reference signal and generates pilot signals of four different periods in phase synchronization with the rotational phase of a rotary head for use in tracking during reproduction; an f ₅ signal generation circuit that divides the frequency of the first reference signal and generates a fifth pilot signal f ₅ in phase synchronization with the rotational phase of the rotary head for use in controlling the head height during recording;
A pilot signal generation circuit comprising: a timing pulse generation circuit that uses the _f5 signal as a second reference signal and generates a head switching pulse for recording and reproduction and a recording and reproduction timing pulse of the _f5 signal. 2 The 4-frequency pilot signal generation circuit counts the first reference signal and generates four types of first output signals.
N ₁ A, N ₁ B, N ₁ C, N ₁ D and the other four types of secondary
a first counter that generates output signals N ₂ A, N ₂ B, N ₂ C, N ₂ D; and a first counter that generates output signals N ₁ A, N ₂ A, N ₁ B, N ₂ B, N ₁ C, N ₂ C,
A switching circuit that selects and outputs a combination of N ₁ D and N ₂ D in synchronization with the PG signal, and a first flip-flop circuit whose output state changes depending on the selected first and second output signals. , a second flip-flop circuit whose output state is inverted each time the first output signal is input; a first gate circuit that processes the output signals of the first and second flip-flop circuits; a second control signal for controlling the gate circuit to make its output either a continuous signal or an intermittent signal; and a second control signal for processing the control signal to obtain a signal for driving the first gate circuit.
a first electronic switch which is driven by the output signal of the first gate circuit and whose output is either the power supply voltage or the ground potential; and an output of the first electronic switch. Claim 1 comprising a resistor matrix circuit driven by a signal to create a three-level staircase waveform.
The pilot signal generation circuit described in . The _3f5 signal generation circuit includes a second counter that counts the first reference signal, and a third flip-flop whose output state is inverted every time the output signal of the second counter that has counted _N3 cycles is input. a third gate circuit for processing the third flip-flop output; and a second electronic switch for opening and closing the output signal of the third gate circuit.
A control signal for controlling the third gate circuit and the second electronic switch to make the output either a continuous signal or an intermittent signal, and a control signal for processing the control signal to control the third gate circuit and the second electronic switch. a fourth gate circuit for obtaining a signal for driving an electronic switch; and a fourth gate circuit for inputting an edge signal of the PG signal as a reset signal for the second counter in order to synchronize the second counter with the PG signal. 5. The pilot signal generating circuit according to claim 1, wherein the pilot signal generating circuit is configured to include a gate circuit of No. 5. 4 fourth and fifth signals for detecting rising and falling edges of the PG signal with the accuracy of the first reference signal;
and a fifth gate circuit for processing the output signals of the fourth and fifth flip-flops to obtain a PG edge signal.
A pilot signal generation circuit according to claim 1, which is configured to include a PG edge detection circuit. 5 The timing pulse generation circuit uses the _f5 signal, which is the output of the _f5 signal generation circuit, as a second reference signal.
A third counter that counts this second reference signal, a decoder that is driven by the output of this third counter, and a first and second recording head switching pulse that is driven by the output signal of this decoder. 6th to 10th flip-flop circuits whose output signals are a reproduction head switching pulse and a recording and reproduction timing pulse of the _f5 signal, and driven by the output signal of the decoder and the PG edge signal,
an eleventh flip-flop whose output signal is a gating signal for gating the _f5 signal into a second reference signal and at the same time synchronizing the third counter with the PG signal with the accuracy of the first reference signal; A pilot signal generating circuit according to claim 1, wherein the pilot signal generating circuit is configured to include a circuit. 6 Third and fourth gate circuits that output the _f5 signal only during the recording timing period of the _f5 signal and control the impedance to be high during periods other than this, and a power supply during the recording and reproduction timing period of the _f5 signal. 1/ of voltage
The first and second gate circuits control to output the 4-frequency pilot signal at a constant level of 2 and only in other periods, and the f ₅ signal is output as an intermittent signal.
2. The pilot signal generating circuit according to claim 1, further comprising a resistor for mixing the signal and the four-frequency pilot signal.