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JPH0370908B2 - - Google Patents
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JPH0370908B2 - - Google Patents

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Publication number
JPH0370908B2
JPH0370908B2 JP59209207A JP20920784A JPH0370908B2 JP H0370908 B2 JPH0370908 B2 JP H0370908B2 JP 59209207 A JP59209207 A JP 59209207A JP 20920784 A JP20920784 A JP 20920784A JP H0370908 B2 JPH0370908 B2 JP H0370908B2
Authority
JP
Japan
Prior art keywords
region
voltage
space charge
shot
regular hexagonal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59209207A
Other languages
Japanese (ja)
Other versions
JPS6188560A (en
Inventor
Kazuhisa Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP59209207A priority Critical patent/JPS6188560A/en
Publication of JPS6188560A publication Critical patent/JPS6188560A/en
Publication of JPH0370908B2 publication Critical patent/JPH0370908B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 

Landscapes

  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はコンピユーターなどの端末電子機器の
IC化に伴なう低電圧、大電流直流安定化電源に
おいて使用される整流用ダイオードに望まれる低
い順電圧降下特性と比較的高い逆阻止電圧特性を
合わせもつダイオードに関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to terminal electronic devices such as computers.
The present invention relates to a diode that has both low forward voltage drop characteristics and relatively high reverse blocking voltage characteristics, which are desired for rectifier diodes used in low voltage, high current stabilized DC power supplies accompanying the use of ICs.

〔従来技術〕[Prior art]

このようなダイオードの構造としてN形シリコ
ン基板を用いたシヨツトキ・バリヤ・ダイオード
(以降SBDと略す)において、シヨツトキ・コン
タクトの下側のシリコン基板表面にP形の不純物
拡散領域を設け、シヨツトキ・バリヤに基づく低
い順電圧降下特性とPN接合に基づく高い逆阻止
電圧特性とを共に備える高耐圧SBDを形成する
ことは、例えば既にソリツド・ステート・エレク
トロニクス(Solid State Electronics)26(′83)
P491〜493の文献により公知である。
In a shot barrier diode (hereinafter abbreviated as SBD) using an N-type silicon substrate as a diode structure, a P-type impurity diffusion region is provided on the silicon substrate surface below the shot contact, and the shot barrier diode is Forming a high voltage SBD that has both low forward voltage drop characteristics based on PN junctions and high reverse blocking voltage characteristics based on PN junctions has already been proposed, for example, in Solid State Electronics 26 ('83).
It is known from the literature P491-493.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述のような、いわば集積型とでもいうべき
SBDは第4図の要部断面図に示されるような構
造を備えている。
As mentioned above, it can be called an integrated type.
The SBD has a structure as shown in the cross-sectional view of the main part in FIG.

このSBDでは順方向電圧が、すなわちアノー
ド電極3が正に、カソード電極4が負に、印加さ
れると、電流は主として堰層電圧の低いn領域1
の表面8に接するシヨツトキ・バリヤ領域5を流
れ、堰層電圧の高いP形領域2には流れない。逆
方向電圧印加では電圧の増加とともにPn接合6
のn領域1側に拡がり、点線で示される空間電荷
領域7aがn領域表面8を覆いつくし、全体の降
伏電圧はその外側のP形環状領域9による空間電
荷領域端7bでの降伏によつて決まるようにな
る。
In this SBD, when a forward voltage is applied, that is, positive to the anode electrode 3 and negative to the cathode electrode 4, the current mainly flows to the n region 1 where the weir layer voltage is low.
It flows through the shot barrier region 5 which is in contact with the surface 8 of the pump, and does not flow into the P-type region 2 where the weir layer voltage is high. When reverse voltage is applied, the Pn junction 6 increases as the voltage increases.
A space charge region 7a shown by a dotted line completely covers the n region surface 8, and the overall breakdown voltage is due to breakdown at the space charge region edge 7b due to the P-shaped annular region 9 outside the space charge region 7a. It becomes decided.

このような集積型SBDは逆耐圧を重視すれば
空間電荷領域7aがn領域表面8を全て覆うよう
P形領域2をある程度密に配列する必要がある。
そうすると、順方向電圧印加の際のSBD導通領
域5の面積比率が小さくなるので堰層電圧が高く
なり、低い順方向電圧降下特性をもつという
SBDの長所が損なわれる。反対に低い順電圧降
下特性を重視しすぎてP形領域2を疎にすると、
逆電圧印加時に空間電荷領域7aがn領域表面8
を完全には覆わなくなり、P形領域2を設けた意
味がなくなる。
In such an integrated SBD, if reverse breakdown voltage is important, the P-type regions 2 must be arranged densely to some extent so that the space charge region 7a completely covers the n-region surface 8.
In this case, the area ratio of the SBD conduction region 5 when applying a forward voltage becomes smaller, resulting in a higher weir layer voltage and a lower forward voltage drop characteristic.
The advantages of SBD are diminished. On the other hand, if we place too much emphasis on low forward voltage drop characteristics and make the P-type region 2 sparse,
When a reverse voltage is applied, the space charge region 7a becomes the n region surface 8.
Since the P-type region 2 is not completely covered, there is no point in providing the P-type region 2.

従つて本発明の目的は上記の欠点を改良し、で
きるだけ順電圧降下が小さく、逆阻止電圧の高い
高耐圧SBDを提供することである。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to improve the above-mentioned drawbacks and provide a high breakdown voltage SBD with a forward voltage drop as small as possible and a reverse blocking voltage as high as possible.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は前述の問題点を解決するためにP形領
域の形状と配列を工夫し、各P形領域のPn接合
から、逆方向印加された場合に拡がる空間電荷領
域が互に重くなることなく、しかも所定の逆電圧
印加のとき、n領域表面8の全面を覆うような寸
法関係のなかで、とくに著しい効果をもつ寸法形
状を見い出したことに基づくものである。
In order to solve the above-mentioned problems, the present invention devises the shape and arrangement of the P-type regions, so that the space charge regions that spread out from the Pn junction of each P-type region when applied in opposite directions do not overlap each other. Moreover, this is based on the discovery of a dimensional shape that has a particularly remarkable effect among the dimensional relationships that cover the entire surface of the n-region surface 8 when a predetermined reverse voltage is applied.

それは本発明によれば六角稠密(又は正三角稠
密)状に配置した正三角形の各頂点に中心をもつ
正六角形であつて、かつそれぞれの正六角形の各
頂点に突起を備える形状のP形領域がシヨツト
キ・バリヤ領域下に配置されていることにより得
られる。
According to the present invention, it is a P-shaped region that is a regular hexagon having a center at each vertex of an equilateral triangle arranged in a hexagonal dense (or equilateral triangular dense) manner, and has a protrusion at each vertex of each regular hexagon. This is obtained by disposing it under the shot barrier area.

〔作用および実施例〕[Function and Examples]

以下本発明の一実施例について図面を用いて詳
細に説明する。
An embodiment of the present invention will be described in detail below with reference to the drawings.

第1図乃至第3図は本発明の高耐圧シヨツト
キ・バリヤ・ダイオードを示す図である。これら
の図において、同符号は同一の部分を示す。
1 to 3 are diagrams showing a high voltage shot barrier diode of the present invention. In these figures, the same reference numerals indicate the same parts.

第1図は本発明による高耐圧SBDであつて、
そのアノード電極であるシヨツトキ・バリヤ電極
16を上から透して見た上面図である。シヨツト
キ・バリヤ電極16の下のn形シリコン基板の表
面に設けられたP形正六角形状領域13がシヨツ
トキ・バリヤ電極とシリコンと接するシヨツト
キ・バリヤ領域内において、相互に逆電圧印加時
に延びる空間電荷領域の長さの2倍より少し短か
い距離で、しかも後で述べるように所定の配置に
従つて均一に分布しており、さらにシヨツトキ・
バリヤ領域の外側境界にはP形の環状領域14が
設けられている。その外側の領域15はシリコン
酸化膜のような表面保護膜の領域である。P形正
六角形領域13とP形環状領域14との間隔は、
正六角形領域13の形状を必要以上に複雑なもの
にしないため、前記の空間電荷領域の長さの2倍
以内という範囲で、前記正六角形領域13の相互
間の間隔と異ならせることができる。このように
することにより逆電圧が印加されたときに空間電
荷領域がシヨツトキ・バリヤ領域全体を覆うよう
になり、逆阻止電圧はP形環状領域の外側に延び
る空間電荷領域端での降伏によつて決まることに
なる。
FIG. 1 shows a high voltage SBD according to the present invention,
FIG. 2 is a top view of the shot barrier electrode 16, which is the anode electrode, seen through from above. In the shot barrier region where the P-type regular hexagonal region 13 provided on the surface of the n-type silicon substrate below the shot barrier electrode 16 is in contact with the shot barrier electrode and silicon, space charges extend when opposite voltages are applied to each other. The distance is slightly shorter than twice the length of the area, and as will be described later, it is uniformly distributed according to a predetermined arrangement, and furthermore, the shot spot
A P-shaped annular region 14 is provided at the outer boundary of the barrier region. The outer region 15 is a region of a surface protection film such as a silicon oxide film. The distance between the P-shaped regular hexagonal region 13 and the P-shaped annular region 14 is
In order not to make the shape of the regular hexagonal regions 13 unnecessarily complicated, the spacing between the regular hexagonal regions 13 can be varied within a range of twice the length of the space charge region. This allows the space charge region to cover the entire shot barrier region when a reverse voltage is applied, and the reverse blocking voltage is due to breakdown at the edge of the space charge region extending outside the P-shaped annular region. It will be decided in due course.

次にP形正六角形領域の形状と配置についてさ
らに詳しく述べる。第2図は第1図に示される高
耐圧シヨツトキ・バリヤ・ダイオードの断面図で
ある。符号16はアノードとなるシヨツトキ・バ
リヤ電極であり、符号17はカソード電極であ
る。第2図においてシリコンのn形低抵抗率基板
11に積層されたn形高抵抗率シリコン層12の
抵抗率ρによつて定まるPn接合のアバランシエ
降伏電圧もしくはツエナ降伏電圧をVzとすると、
逆電圧印加時にP形正六角形領域13のところの
Pn接合から拡がる空間電荷領域距離L(ミクロ
ン)はL=0.53√・と近似されることが知
られている。従つて、本発明の目的に適うP形正
六角形領域13相互の距離を2Lとすると、L≦
0.53√・であるが実際には安全率を0.95と見
込み、これを乗じてL=0.50√・とするこ
とができるし、またこの方が望ましい。このP形
正六角形領域13の上面形状は第3図の拡大図に
示すように正六角形13bであつて、しかも第1
図に示すように正三角形を相互に稠密に敷きつめ
て得られる六角稠密(又は正三角形稠密)に配列
された正三角形Kの各頂点K1,K2,K3にそれぞ
れ中心をもつように配置されているので、シリコ
ン表面での空間電荷領域の相互の重なりを第3図
の点線で示すように最も少なくすることができ
る。P形正六角形領域13bの大きさ(外接円の
半径をdとする)はできるだけ小さいことが望ま
しい、例えば、半導体素子の製造におけるホト工
程できまる寸法精度からは3〜5ミクロンとする
のが最適である。
Next, the shape and arrangement of the P-shaped regular hexagonal area will be described in more detail. FIG. 2 is a cross-sectional view of the high voltage shot barrier diode shown in FIG. 1. Reference numeral 16 is a shot barrier electrode serving as an anode, and reference numeral 17 is a cathode electrode. In FIG. 2, if the avalanche breakdown voltage or Zener breakdown voltage of the Pn junction determined by the resistivity ρ of the n-type high-resistivity silicon layer 12 laminated on the silicon n-type low-resistivity substrate 11 is Vz,
When a reverse voltage is applied, the P-type regular hexagonal area 13
It is known that the space charge region distance L (microns) extending from the Pn junction is approximated as L=0.53√·. Therefore, if the distance between the P-shaped regular hexagonal areas 13 suitable for the purpose of the present invention is 2L, then L≦
Although it is 0.53√・, the safety factor is actually expected to be 0.95, and by multiplying this, it is possible to make L=0.50√・, and this is preferable. The upper surface shape of this P-shaped regular hexagonal region 13 is a regular hexagonal shape 13b as shown in the enlarged view of FIG.
As shown in the figure, the centers are arranged at the vertices K 1 , K 2 , and K 3 of the equilateral triangles K arranged in a hexagonal dense (or equilateral triangular dense) arrangement obtained by densely arranging equilateral triangles. Therefore, the mutual overlap of the space charge regions on the silicon surface can be minimized as shown by the dotted line in FIG. It is desirable that the size of the P-shaped regular hexagonal region 13b (the radius of the circumscribed circle is d) be as small as possible. For example, from the viewpoint of dimensional accuracy achieved in the photo process in the manufacture of semiconductor devices, it is optimal to set it to 3 to 5 microns. It is.

正六角形領域の相互中心距離をD(ミクロン)
とするとDは次のようにして決めることができ
る。例えばD=2L+2d×√3/2=2×0.50√・ Vz+2×3×√3/2となり、シリコンの抵抗率ρ と降伏電圧Vzが決まればDが求まることになる。
ところで、このように最大空間電荷領域の重なり
を少なくなるように配置すると、正六角形P形領
域の最大空間電荷領域端の上面形状は第3図の点
線で示されるものとなるが、この第6図のように
3本の点線の交点E付近では重ならない場所が生
じることが判明した。これを本発明の目的に適う
ようにしてなお防止するにはそれぞれの正六角形
領域13aの各角部Aに外方Bに向う長さlの突
起ABを付加するとよいことが確かめられた。こ
の突起ABは正六角形領域13aのみならずシヨ
ツトキ・バリヤ領域下に設けられた最外周を除く
すべての正六角形領域の角部に形成されねばなら
ないことは言うまでもない。
The mutual center distance of regular hexagonal areas is D (microns)
Then, D can be determined as follows. For example, D=2L+2d×√3/2=2×0.50√·Vz+2×3×√3/2, and if the resistivity ρ and breakdown voltage Vz of silicon are determined, D can be found.
By the way, if the maximum space charge regions are arranged so that the overlap of the maximum space charge regions is reduced in this way, the top surface shape of the maximum space charge region end of the regular hexagonal P-shaped region will be as shown by the dotted line in FIG. As shown in the figure, it has been found that there are areas where the three dotted lines do not overlap near the intersection E. It has been found that in order to still prevent this while still meeting the purpose of the present invention, it is effective to add a protrusion AB of length l facing outward B to each corner A of each regular hexagonal area 13a. It goes without saying that this protrusion AB must be formed not only at the corners of the regular hexagonal area 13a but also at all corners of the regular hexagonal area except for the outermost periphery provided under the shot barrier area.

この突起ABは正六角形の角部Aから突起の先
端Bまでの長さをlとすると、 l≧AE−BE=AE−L=2/√3L−L≒0.155L となる。実際にはl≒0.16Lが好ましい。突起の
幅はできるだけ小さくてよく、例えば1ミクロン
を選択することができる。
If the length of this protrusion AB from the corner A of the regular hexagon to the tip B of the protrusion is l, then l≧AE−BE=AE−L=2/√3L−L≒0.155L. Actually, l≈0.16L is preferable. The width of the protrusion may be as small as possible, for example 1 micron can be selected.

このようにして定めた突起形状が第3図の正六
角形領域13aに示されている。
The protrusion shape determined in this way is shown in the regular hexagonal area 13a in FIG.

この形状によるP形正六角形領域を備える
SBDは逆電圧印加時にはSBD部のすべての領域
が空間電荷領域で覆われることになる。従つて
Pn接合に基づく高い逆阻止電圧が得られる。ま
たこのP形領域13aの配列を六角稠密状にしき
つめた正三角形の各頂点にC1の中心がくるよう
に配置されているため、空間電荷領域の最大拡が
り時における相互の重なりをほとんど無しにする
ことができ、その結果所定の逆電圧に対して正六
角形領域の全面積を最も小さくなるので、順方向
電圧印加のときの堰層電圧もまた最少となる。
It has a P-shaped regular hexagonal area with this shape.
When a reverse voltage is applied to the SBD, the entire area of the SBD section is covered with a space charge area. Accordingly
A high reverse blocking voltage can be obtained based on the Pn junction. In addition, since the P-type regions 13a are arranged so that the center of C1 is located at each vertex of an equilateral triangle that is tightly packed into a hexagonal shape, there is almost no mutual overlap when the space charge regions are expanded to their maximum. As a result, the total area of the regular hexagonal region is minimized for a given reverse voltage, so that the weir layer voltage when a forward voltage is applied is also minimized.

〔発明の効果〕〔Effect of the invention〕

本発明によればシヨツトキ・バリヤ・ダイオー
ドにおいてバリヤ領域内に配置される不純物拡散
領域の形状が六角稠密配列された正三角形の各頂
点にそれぞれ中心をもつ正六角形であつて、かつ
それぞれの正六角形の各頂点に降伏電圧印加時の
空間電荷領域がシヨツトキ・バリヤ領域を残りく
まなく覆うような突起を備えるようにしたので順
電圧降下が小さく、逆阻止電圧の高いシヨツト
キ・バリヤ・ダイオードを得ることができる。
According to the present invention, the shape of the impurity diffusion region disposed in the barrier region in the shot barrier diode is a regular hexagon having a center at each vertex of an equilateral triangle arranged in a dense hexagonal arrangement, and Since each vertex of the diode is provided with a protrusion such that the space charge region completely covers the shot barrier region when a breakdown voltage is applied, a shot barrier diode with a small forward voltage drop and a high reverse blocking voltage can be obtained. I can do it.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す上面図、第2
図は同上の断面図、第3図は同上の正六角形領域
の拡大図、第4図は従来の集積型シヨツトキ・バ
リヤ・ダイオードの要部断面図である。 13…正六角形領域、14…環状領域、16…
シヨツトキ・バリヤ電極、17…カソード電極、
AB…突起。
Figure 1 is a top view showing one embodiment of the present invention, Figure 2 is a top view showing one embodiment of the present invention;
This figure is a sectional view of the same as above, FIG. 3 is an enlarged view of the regular hexagonal area of the same as above, and FIG. 4 is a sectional view of a main part of a conventional integrated shot barrier diode. 13... regular hexagonal area, 14... annular area, 16...
Shotki barrier electrode, 17... cathode electrode,
AB...protrusion.

Claims (1)

【特許請求の範囲】[Claims] 1 シヨツトキ・バリヤ領域下の半導体表面に該
半導体とは異なる導電型の複数個の不純物拡散領
域が設けられ、それぞれの領域の相互間隔が降伏
電圧印加時におけるPn接合の外側に拡がる空間
電荷領域の長さの2倍より短かくなるように配置
されてなるものにおいて、前記不純物拡散領域の
形状が、相互に稠密に敷きつめられた正三角形の
各項点にそれぞれ中心をもつ正六角形であつて、
かつそれぞれの正六角形の各項点には降伏電圧印
加時の空間電荷領域がシヨツトキ・バリヤ領域を
残りくまなく覆うような突起を備えていることを
特徴とする高耐圧シヨツトキ・バリヤ・ダイオー
ド。
1. A plurality of impurity diffusion regions of a conductivity type different from that of the semiconductor are provided on the semiconductor surface under the shot barrier region, and the mutual spacing between each region is equal to the space charge region extending outside the Pn junction when a breakdown voltage is applied. In the impurity diffusion region arranged so as to be shorter than twice the length, the shape of the impurity diffusion region is a regular hexagon having a center at each point of an equilateral triangle arranged densely,
A high voltage shot barrier diode, characterized in that each point of each regular hexagon is provided with a protrusion such that a space charge region completely covers the shot barrier region when a breakdown voltage is applied.
JP59209207A 1984-10-05 1984-10-05 High withstanding-voltage schottky-barrier-diode Granted JPS6188560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59209207A JPS6188560A (en) 1984-10-05 1984-10-05 High withstanding-voltage schottky-barrier-diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59209207A JPS6188560A (en) 1984-10-05 1984-10-05 High withstanding-voltage schottky-barrier-diode

Publications (2)

Publication Number Publication Date
JPS6188560A JPS6188560A (en) 1986-05-06
JPH0370908B2 true JPH0370908B2 (en) 1991-11-11

Family

ID=16569124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59209207A Granted JPS6188560A (en) 1984-10-05 1984-10-05 High withstanding-voltage schottky-barrier-diode

Country Status (1)

Country Link
JP (1) JPS6188560A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105465A (en) * 1988-10-14 1990-04-18 Sanken Electric Co Ltd Schottky barrier semiconductor device
JPH0750791B2 (en) * 1989-09-20 1995-05-31 株式会社日立製作所 Semiconductor rectifier diode, power supply device using the same, and electronic computer
US5278443A (en) * 1990-02-28 1994-01-11 Hitachi, Ltd. Composite semiconductor device with Schottky and pn junctions
CN103545382A (en) * 2013-11-12 2014-01-29 株洲南车时代电气股份有限公司 A junction barrier Schottky diode and its manufacturing method

Also Published As

Publication number Publication date
JPS6188560A (en) 1986-05-06

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