JPH03716B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory using transistors, and a memory circuit having a redundant circuit.

In recent years, semiconductor memories have been developing in the direction of increasing capacity. This increase in capacity has been achieved through the development of finer elements and wiring technology, as well as an increase in chip area. Due to this miniaturization, minute dust generated on the manufacturing line has also become a source of defects. For example, the adhesion of dust of about 2 μm to 2 μm elements and wiring becomes a fatal defect, increasing the defect density per unit area.

On the other hand, an increase in chip area naturally increases the number of defects per chip. For this reason, it is clear that as the memory capacity increases, the defect rate per chip increases exponentially. For this reason, even with improvements in manufacturing technology, it is unavoidable that the yield of defect-free chips will drop rapidly as capacity increases. In order to solve these difficulties, it has begun to be introduced that redundant circuits are included in chips to repair defects.

Memory defects tend to occur in the memory matrix, which accounts for more than half of the effective area of the chip, and a defect occurring in the matrix causes only one bit or a small number of bits to be defective. This method attempts to repair defects by replacing columns with repair rows or columns prepared as redundant circuits. Conventionally known methods for writing to redundant circuits include passing a large current through a conductor called a fuse to blow it out, or cutting the fuse with a laser. The method of fusing with a current requires the application of a relatively high voltage and a large transistor to flow a large current, so it is not suitable for increasing the capacity, and a method of writing with a laser is often used.

FIG. 1 is a diagram showing a conventionally known remedy. _C1 indicates a row or column decoder in which a defective bit exists (hereinafter referred to as a defective decoder), and _C2 indicates a decoder replacing the defective decoder (hereinafter referred to as a spare decoder). Each decoder consists of a NOR section consisting of transistors Q ₀₅ to _{Q 09} or Qs ₀₅ to Qs ₁₂ , a NOR section consisting of transistors Q ₀₃ and Q ₀₄ or Qs ₀₃ and Qs ₀₄ , and an inverter section that outputs a negative phase signal of output N ₃ or Ns ₃ . and an output section consisting of transistors Q ₀₁ and Q ₀₂ or Qs ₀₁ and Qs ₀₂ . The signal input to the NOR section of both decoders is a signal that becomes 1 level when the memory is in a non-selected state, and at this time all word lines are made to be in a non-selected state. Three sets of address correction signals (A ₀ , ₀ ) _, (A ₁ , ₁ ), (A ₂ ,
₂ ) are also input, so that if this spare decoder _C2 is not in use, the contact _Ns3 is always at the 0 level, so it is always in a non-selected state. Now the address inputs of defective decoder C ₁ (A ₀ , A ₁ ,
₂ ) is input, the defective decoder C ₁
This section shows how to replace C2 with spare decoder _C2 .
First, use a laser to cut fuses fs ₅ , fs ₃ , and fs ₂ of spare decoder C ₂ , and the spare decoder will be
Only when A ₀ , A ₁ , ₂ are all 0, the NOR node Ns ₃ is set to high level and the decoder is selected. On the other hand, only at this time, the defective decoder C ₁ also has the NOR part N ₃ at the 1 level, so the defective decoder C ₁
is copied to spare decoder _C2 .
On the other hand, by cutting the fuse _f11 of the defective decoder, the contact _N11 has no potential supply means and maintains zero potential due to leakage, etc., so the defective decoder is always in a non-selected state and the defective decoder _C1 is completely switched to _C2.
The copy to is completed and the output of the defective decoder is deactivated.

However, according to the conventional method, the cut-off decoder output is in a high impedance state, and the leakage current only maintains the non-selected state. Therefore, the decoder output, which is cut off due to power supply fluctuations or noise introduced during operation due to capacitive coupling, is not at a constant level and may sometimes exceed the threshold value of the transistor. The memory cells connected to the defective decoder will not be read out, so there is no need to fear that their stored information will be destroyed, but it will adversely affect the circuit operations of other cells. For example, charge on the bit line may leak into the cell or I/O bus, causing a high level drop on the bit line. Another feature of CMOS memory is that it has low power consumption, especially the current during standby is as small as a few μA, but even for such functions, the leakage current during standby increases due to the leakage mentioned above. It will end up being put away.

The present invention provides a means for stabilizing the output of the disconnected decoder, ie, the potential of the word line or I/O switch gate, etc., when such a defective decoder is repaired. The present invention will be explained below based on examples.

FIG. 2 shows one embodiment of the invention. The figure shows only a normal decoder, and it is assumed that it has the same inputs as in FIG. Also, transistors and nodes with the same symbols have the same functions as the defect decoder of FIG. Here, a fuse _f13 for deactivation is connected in series between the node _N2 of the inverter section and the transistor _Q04 connected to its ground side.

Therefore, when not selected, the NOR part transistor Q ₀₆ ~
At least one of Q ₀₉ is in a conductive state, the node N ₃ of the NOR section becomes 0 level, the node N ₂ of the inverter section and the node N ₁ of the driver section are respectively 1 level and 0 level.
It has become a level. In the selected state, the NOR input transistors Q ₀₆ to _{Q 09} are all non-conductive, the node N ₃ is at the 1 level, and the nodes N ₂ and N ₁ are at the 0 and 1 level, respectively.

Now, if this decoder is a defective decoder, cutting the fuse f ₁₃ connected in series between the node N ₂ of the inverter section and the transistor Q ₀₄ will result in the following:
The transistor is disconnected from node N ₂ and connected to node N
is always connected to the power supply via transistor Q ₀₃ , so node N ₂ always outputs 1 level, and therefore output N ₁ can always output 0 level with low impedance, and this decoder is deactivated and always remains unselected. This results in a stable non-selected state.

According to the present invention, a fuse is inserted between the transistors constituting the inverter section and the nodes, and by cutting the fuses, even if an input to be selected is input, the internal nodes are prevented from reaching the selection level, so that the decoder outputs to avoid high impedance state,
It becomes possible to obtain a stable non-selected state.

[Brief explanation of drawings]

FIG. 1 shows a decoder C ₁ and a spare decoder C ₂ of a conventional redundant circuit, and FIG. 2 shows a decoder section of the present invention. In the figure, Q ₀₁ , Q ₀₂ , ..., Q ₀₉ ,
Qs ₀₁ , Qs ₀₂ , ..., Qs ₁₂ are transistors, fs ₁ ,
fs ₂ , ..., fs ₆ indicate fuses.

Claims (1)

[Claims] 1 In a redundant circuit that deactivates a defective decoder by cutting the fuse inside the decoder using a laser, there is an input NOR section, an inverter section that inverts the output of this NOR section, and an output of this inverter section. In the inverter section, a fuse is inserted between a node that outputs an inverted output to the driver section and a transistor connected to the ground side of this node, and when this fuse is cut, A redundant circuit characterized in that the redundant circuit is configured to always output a power level from a node of the inverter section and output a ground level to the driver section.