JPH0372295B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a sector scanning ultrasonic scanning device for performing tomography of human body organs such as the heart. More specifically, the present invention relates to a scan conversion device for converting points on a tomographic plane to points on a display device. Traditionally, when performing tomography of a human body using a sector-scanning ultrasound scanning device, data is collected at points that satisfy the Nyquist criterion along the radial line of the ultrasound signal generated from the scanning device (scanner). The method used was to sample, store the resulting data sample in memory, and display the data sample on a display device.
Due to the gaps between the radial lines, there were disadvantages such as lines and wavy shapes that were required for imaging on the display device (see "Digital Scan Converters in Diagnostics" by J. OPHIR and NFMAKLAD).
The paper entitled “Ultrasound Imaging” Proc.
(See IEEE, Vol. 67, No. 4, April 1979). Conventionally, in order to improve this problem, a method has been used in which a radial line for interpolation data is inserted into the blank space. This method improves the wavy shape, but
This creates a portion in memory where duplicate data samples are stored. Of these redundantly stored data samples, only the last stored data sample is output to the display device, which has the disadvantage of causing crevices and unnecessary contrast in the displayed image. It was hot. In order to improve this, there was a method of inputting the peak value or average value of the duplicated data samples into the display device, but this method was only a slight improvement and had the same drawbacks. Was. Furthermore, in the above method, the data samples on the tomographic plane are stored in the memory and displayed on the display at a rate of
Real-time operation at a 30 sector scan rate was not possible. The present invention was made to eliminate the above-mentioned drawbacks, and it is possible to obtain true cross-sectional imaging in a short time using correction values obtained from four data points that constitute a sub-slice, which is a minute portion within a sector. With the goal. Embodiments of the present invention will be outlined below. first,
Four points forming a subslice, which is a minute portion within the sector, are selected. From the interpolated values obtained from these four points, the true image is reconstructed on the display device by obtaining data samples corresponding to the points in the display memory contained within the subslice. Specifically, the subslice is an area surrounded by two radial lines and two circular arcs,
The four points are the intersections of each radial line and each circular arc. The first and second intermediate interpolated values are obtained at the radial position of each display point from a sample pair both along the radial direction, or at the angular position of each display point from a sample pair both along the arc direction. It will be done. If said first and second intermediate interpolated values are obtained at the radial position of the display point, then a final interpolated value is obtained from said intermediate interpolated value at the angular position of the display point, and said intermediate interpolated value is obtained at the angular position of the display point. If obtained in position, the final interpolated value is obtained in radial position. The radial position of each display point within a subslice is determined by adding a stored value for each step along a column of display points and a stored value for each step along a row of display points to the known radius of the previously scanned display point. Obtained by iteratively adding or subtracting values. The fractional part of this repeated addition or subtraction is a radial coefficient and is called RERR. The angular position is measured at a known distance, called COUNT, of the previously scanned display point from one of the radial lines of the slice, measured along the column of display points, for each step along the column of display points. Iteratively adding different stored values for each step along the row of stored values and display points;
Signal i.e. COUNT for each display point
get value The known distance between the radial lines of the slices along a given column of display points is further iteratively appended with a predetermined stored value for each step along a row of display points to generate a signal for each display point. In other words, the XHAT value is obtained. The signal COUNT at each display point is the signal at that point.
Divide by XHAT to obtain a signal representing the angular position, ie, the θERR value. If the angle between the radial lines is small, there will be a small error in the true angular position expressed as the ratio of the arc length between the display point and the radial line of the slice. In the present invention, the angular position and the radial position are not directly calculated, but interpolated values are calculated by iterative addition, so calculations can be made in a short time. In an ultrasound system, if the data sample represents brightness, 5 bits are required to represent the 32 brightness levels that can be reproduced on a cathode ray tube. In this way, RERR, COUNT,
Although 5 bits are required to represent the final value of XHAT, θERR, 12 bits are used to reduce the amount of accumulated error to an acceptable level in repeated additions. Interpolation can be achieved in a very short time by multiplying with ROM, and since both the luminance samples and the RERR and θERR values used in the interpolation have only 5 bits, it is not convenient. size ROM is used. Below, calculation formulas used in the examples of the present invention will be briefly shown. The angle of the center line in the radial direction is 0°C,
Take all other radial angles to positive values. 90℃
For the sector, there are radial lines within +45°C on each side of the radial center line. Let the angle of the outer radial line R ₀ be θ ₂ and the angle of the inner radial line R ₁ be θ ₁ . RERR Repetition relationship is between previous point j and new point (i+1)
Adjust the previous radius value by an incremental amount determined by the transverse direction between. If this movement is in the X direction, left or right, then Ky=0.
Conversely, if this movement is in the y direction, up or down, then Kx=0. If the movement in the X direction is towards the center line of the sector, then
Kx is positive and causes an incremental decrease in radius by Kx sinθ ₂ . Conversely, for outward movement in the X direction,
Kx is negative, resulting in an incremental increase by Kx sinθ ₂ . If the movement in the y direction is away from the sector vertex, then Ky is positive, and if the movement in the y direction is towards the vertex, Ky is negative. The coefficients RERR and θERR required at each display point ostensibly require direct calculation of the radius R and angle θ, where θ is the vertical line through the center of the sector and the sector slice through the display point. It is the angle between the line to the vertex. That is, for the jth display point, (1) Rj = √ ² + ² where (xj, yj) are the rectangular coordinates of the jth display point. (2) θj=tan ^-1 xj/yj However, equation (1) can also be calculated from the iterative approximation resulting from the Taylor series approximation given by the following equation (3). (3) R _j+1 =Rj−Kx sin θ ₂ +Ky cos θ ₂ where θ ₂ represents the outer angle of the two radial lines forming the sector slice. θERR The stored value ΔXHAT added for each step of the scan path along a row of display points to obtain the XHAT for each display point is tanθ ₂
−tanθ ₁ , where θ ₂ is the line of slice θ=
is the angle between 0° and the outer radius line, and θ ₁ is
It is the angle between the line θ=0° and the inner radius line of the slice. Therefore, (4) XHAT _j+1 =XHAT _j +ΔXHAT·Ky It is also shown as follows. (5) COUNT _j+1 = COUNT _j +Kx+Ky tanθ ₂ The value of tanθ ₂ is stored for each slice. Examples of the present invention will be described below. The block diagram in FIG. 1 shows the basic configuration of a digital scan converter according to the present invention. Scanner 20 is
transmitting acoustic pulses to the human body by means not shown and transmitting analog signals related to the magnitude of reflected sound received from body tissues located along a number of radial lines of the sector shown in FIG. 1A; Occur. Only a few radial lines are shown in FIG. 1A.
When an analog signal is being received, uniformly spaced digital samples, indicated by the dots in FIG. 1A, are obtained along each radial line by A/D converter 22 and scan converted. Device 2
4 is applied. The first data sample is at the origin 0 of the sector, and since the data samples are distributed along the radial arc, the other data samples are at the intersections of equally spaced radial arcs and the radial line of the sector. be. As previously mentioned, the functionality of the scan converter 24 is such that the scan converter 24 functions to transfer data samples to the appropriate display points of the display memory 26 located in orthogonal columns and rows as indicated by the crosses in FIG. 1B. is to write a digital data value. To do this, scan converter 24 determines the data value to be written and the x of the display point on display memory 26 at which it is to be located.
Output the y coordinate. Once stored in display memory 26, the data is read out from the appropriate x,y coordinate point by readout device 28 and
And it can be positioned and displayed at the corresponding coordinate point of the display means 30 indicated by the cross mark in FIG. 1C. Basic Principles of the Invention Figure 2 shows that at the intersections of radial arcs A ₁₀ to _{A 13} and radial lines R ₂ to R ₅ uniformly spaced by a distance S,
2 is an enlarged view of a portion of the sector shown in FIG. 1 with data sample points shown as dots appearing along these radial lines; FIG. Each data sample point is designated by the letter S with a subscript equal to the number of the radial line in which it appears and a superscript equal to the number of the circular arc in which it appears. The data sample points are thus distributed along the radial arc. The display points of display memory 26 in FIG. 1 are located in orthogonal columns and rows parallel to the x- and y-axes, respectively, and are indicated by crosses. For simplicity, some of the radial lines R ₂ to _{R 5} have been omitted. However, although not shown, the x-axis passes through the origin 0, where the display point is located. The spacing between columns of display points is Ky, and the spacing between rows of display points is Kx. A first method of performing interpolation will be described below. To determine the final interpolated data value to be used at the display point indicated by the symbol DP in Figure 2,
A signal or RERR' value representing the radial distance between DP and the radial arc A ₁₁ and a signal or θERR' value representing the angular deviation between DP and the radial line R ₃ are obtained. Thus, RERR' and θERR' represent the radial and angular position of the display point DP with respect to A ₁₁ and R ₃ , respectively. The first intermediate interpolated data value I ₁ is determined along the radial line R ₃ by linearly interpolating between the data samples of S ₃ ¹¹ and S ₃ ¹² according to the following equation:
can be obtained at the radial position of the DP. (6) I ₁ = S ₃ ^11* (S-RERR') + S ₃ ^12* RERR'/S However, S ₃ ^11* and S ₃ ^12* are data samples S ₃ ¹¹ ,
S ₃ is a data sample value of ¹² . Similarly, the second intermediate interpolated data value I ₂ is determined by the radius of DP along radius R ₄ by linearly interpolating the data samples of S ₄ ¹¹ and S ₄ ¹² according to the following equation: Can be obtained in direction position. (7) I ₂ = S ₄ ^11* (S-RERR') + S ₄ ^12* RERR'/S S ₄ ^11* and S ₄ ^12* are data sample values of S ₄ ¹¹ and S ₄ ¹² . The final interpolated data value FDP corresponding to DP is the first and second intermediate interpolated data value I ₁ according to the following formula:
and I ₂ at that angular position by linearly interpolating. (8) Instead of calculating FDP = I ₁ (Δθ − θERR′) + I ₂ · θERR′ / Δθ θERR′ is the distance between R ₃ and R ₄ measured along the same column of display points. A COUNT value, which is the distance between DP and R ₃ as measured along the same column of display points through the value of XHAT and DP, is determined.
When θERR′ is proportional to Δθ, COUNT is
Proportional to XHAT. Thus, the final interpolated data value at display point DP can be determined from the following equation, where XHAT is replaced by Δθ in equation (8) and COUNT is replaced by θERR′, (9) FDP =I ₁ (XHAT−COUNT)+I ₂・COU
NT/XHAT. A second method of obtaining the final interpolated data value for display point DP can be easily obtained by reversing the order of interpolation. That is, a first intermediate interpolated data value I ₁ ' can be obtained at the angular position of DP along the radial arc A ₁₁ by using the following formula. (10) I ₁ ′=S ₃ ^11* (XHAT−COUNT)+S ₄
^11* .COUNT/XHAT The second intermediate interpolated data value I ₂ ' can then be obtained at the angular position of DP along arc A ₁₂ by using the following formula: (11) I ₂ ′=S ₃ ^12* (XHAT−COUNT)+
S ₄ ^12*・COUNT/XHAT Therefore, the final interpolated data FDP can be expressed by the following formula. (11)′ FDP=I ₁ ′(S−RERR′)+I ₂ ′・RERR′/S As will be explained later, the calculation of these equations is If the angular position is represented by the signal θERR
If expressed by = COUNT/XHAT,
The interpolated value is easily obtained. RERR is A ₁₁ and
A is the fractional position of DP between ₁₂ and θERR is
is the fractional position of DP between radial lines R ₃ and R ₄ .
Therefore, for example, equation (6) becomes as follows. (6') I ₁ = S ₃ ^11* (1-RERR) + S ₃ ^12*・RERR And equation (9) becomes as follows. (9') FDP = I ₁ (1 - θERR) + I ₂ · θERR In either calculation method, the first intermediate interpolated data value is obtained by interpolating data samplings on one side of the DP, and a second intermediate interpolated data value is on the other side of the DP in the same direction as one of the radial and angular directions. Obtained by interpolating data samples. In the first method, the first intermediate interpolated value I ₁
is obtained by finding the interpolated values of S ₃ ^11* and S ₃ ^12* that are to the left of DP in the angular direction, and the second intermediate interpolated data value I ₂ is to the right of DP in the angular direction. It is obtained by interpolating certain S ₄ ^11* and S ₄ ^12* . If the angle between R ₃ and R ₄ is small, the intermediate interpolated value data I ₁ , I ₂ and DP will be aligned approximately on a straight line. Similarly, in the second method,
I ₁ ′ is obtained by interpolating S ₃ ^11* and S ₄ ^11* along arc A ₁₁ and radially on one side of DP, and I ₂ ′ is Along ₁₂
and S ₃ ¹² and S ₄ ¹² radially on the other side of the DP
can be obtained by interpolating . Although the above description describes one way in which the scan converter 24 comprising the present invention can operate, I ₁ is obtained by interpolating four data samples along R ₃ . , and along R ₄ 4
such as obtaining I ₂ by interpolating two data samples, or in a second method obtaining I ₁ ' by interpolating four data samples along arc A ₁₁ , and By interpolating four data samples along arc A ₁₂
Other methods are also possible, such as obtaining I ₂ ′.
Another method is to obtain the interpolated values I _1B and I _1C in the same way as to obtain I ₁ and I ₂ , and angularly precede them in order to obtain the final interpolated value in DP. It is to interpolate. Similarly, the interpolated value I _1A ′ can be obtained from the data samples along A ₁₀ and
I _2B ′ can be obtained from the data samples along with A ₁₃ . These can then be radially interpolated to obtain the final interpolated data values at DP. Furthermore, another method is to use data samples at four sample points far away from the DP such as S ₂ ¹⁰ , S ₅ ¹⁰ , S ₂ ¹³ and S ₅ ¹³ to limit the area encompassing the DP. be. For the interpolation described above, a linear function is illustrated, however any non-linear interpolation method can be used to obtain interpolated values at the radial or angular position of the DP. The type of interpolation changes only the coefficients applied to the data samples. Fundamentals of Calculations As mentioned earlier, calculating all the final interpolated display values within a sector using the direct method is much faster than the real-time operation of a device such as an ultrasonic scanner that scans one sector in 1/30 of a second. it takes time. For an explanation of the basis of calculations according to the invention, reference is made to FIG. Two radial lines from the scanner, i.e. outer lines that define the slice
R ₀ and the inner line R ₁ are the rows of display points along the y-axis, which is the centerline of the sector, and θ ₂ and θ ₁ respectively.
It forms an angle of . In the figure, the angle θ ₂ −θ ₁ between the lines R ₀ and R ₁ is greatly exaggerated, and in general,
It is 3/4° to 1 1/2°, but it is drawn at about 10°. Calculating RERR Below we present the basis for calculating RERR. By starting at the display point DP ₁ of FIG. 3 which happens to be on the outer radius line R ₀ and towards the origin 0 towards the adjacent display point DP ₂ which is a distance Kx from the display point DP _1. can be understood by noting what happens when stepping along the x-axis. If the perpendicular falls from R ₀ through DP ₂ , the acute angle of the right triangle thus formed is θ ₂ and the side of the triangle with respect to θ ₂ is Kx sinθ ₂ . Subtracting this amount from the radius of the display point DP ₁ , however much it may be, results in a value slightly less than the radius value of the display point DP ₂ indicated by the radius length R ₂ . That this is not strictly exact is clear from the fact that the true radius of DP ₂ is the hypotenuse of a right triangle of which R ₂ is one side, and is therefore smaller than the actual radius. If this step is from DP ₂ to DP ₁ , ie away from the origin 0, then the value of Kx sin θ ₂ is added to whatever radius was calculated for DP ₂ . The steps in the +y direction of the length Ky up to DP ₃ add the length Ky cosθ ₂ according to the calculation method, but they also have the radius R ₃ of DP ₃ smaller than the true radius, so It's a little inaccurate. However, if θ ₂ −θ ₁ is between 1 1/2° and 3/4°, as is usual, these errors can be ignored. Although the aforementioned formulas, and devices constructed according to them, utilize the angle θ ₂ of the outer radius line of each slice when making radius calculations, instead:
Another angle close to θ ₂ that differs from θ ₂ by a value less than or equal to Δθ can be selected. Such a selection requires that the error be kept within tolerances. The radius at origin 0 is zero. Therefore, if the display point scanning signal described above, which scans along the rows and columns of display points in slices R ₀ , R ₁ , starts at origin 0 as shown by dotted line 31, and if Kx If the value of sinθ ₂ is subtracted for each step to the right and added for each step to the left, then
And if Ky cos θ ₂ is added for each step away from the origin along the y-axis, then the radius of every display point in the scanning path is within the slice fitted by R ₀ , R ₁ It can be determined with sufficient accuracy to be consistent with the error of a given display point. The radius value of the display point can also be used as described below to prevent data from being written to display memory 26. So that the interpolation along the radial direction mentioned above can be performed
Determining RERR is its more important function. With the format |Kx|=|Ky|=|S|=1, RERR is simply a fraction of the number representing the radius, but if Kx is different from Ky and from s, then Normalization can then generate a radius value measured in units of s such that the fraction is still RERR. Therefore, the following equation holds. (12) R _{j+1 =} R _j −Kx sinθ ₂ +Ky cosθ _{2 XHAT} calculation
Previously defined as the distance between the radial lines of slices like . If a perpendicular line 32 is drawn from the y-axis at the location of display point 34, the value of XHAT for the display point in the same column can be obtained as follows. Ky between origin 0 and display point 34
If the number of increments of is n, then (13) X=nky tanθ ₂ and (14) X'=nky tanθ ₁ and (15) XHAT=X−X ′=nky tanθ ₂ −nky tanθ ₁ It can be seen that the value of XHAT increases by a constant amount ΔXHAT for each change in Ky along the y-axis. (16) ΔXHAT= nky tanθ ₂ −nky tanθ ₁ /n = (tanθ ₂ − tanθ ₁ )ky As used in the system described below, COUNT is the display point for which data is determined along the display point sequence. distance to
It is the value measured from the outer radius line such as R ₀ . DP ₁ in Figure 3 is on the outer line R ₀ , so
The value of COUNT is zero. against DP ₂
The value of COUNT is Kx. Thus, a step along the column of display points toward the center line of the sector increases the value of COUNT by Kx (the third
(see DP ₄ and DP ₄ ' in the figure), and steps away from it decrease the value of COUNT by Kx.
However, if this step moves away from the origin 0, such as the step from DP ₁ to DP ₃ ,
When along the rows of display points, i.e. along the y-axis, the COUNT value is Ky tanθ ₂
only increases. The value of COUNT for the display point at the origin is zero. Therefore, if +Kx, −Kx, and Ky
If the value of tanθ ₂ is chosen as described above, then
You will get the value of COUNT. Any display point is inside a sector slice whenever 0COUNT<XHAT. By dividing COUNT by XHAT,
A fractional measure of the angular position of the display point between the radial lines R ₀ and R ₁ of the slice, θERR, is determined.
Since RERR is a fractional measure of the radial distance of a display point between two data sample points,
θERR and RERR can be used in angular and radial interpolation in the same way. When the value of COUNT is being determined for a slice in the right half of the sector, CONUT is still measured from the outer line, but as can be seen from _{FIG .} and R _I , rather than to the left of R _I ′, as in the case of R I . The same calculation would be applied by measuring COUNT from the outer radial line R _O '. However, the fractional angular position of the display point must be measured from the outer line R _p or R _O '.
For example, in the left half of the sector, R _O
can always be measured for the left radial line with , and similarly for the right half with R _O '. This calculation would be the same as just described for the left half. But in the right half, +Kx and -Kx would have to be swapped and -tanθ ₂ would be used instead of +tanθ ₂ . This can be added to the ROM as described below. The final interpolated data values for display points near the origin are generally not important. The RERR and θERR values of these points are required during the iterative addition to obtain the RERR and θERR values needed to calculate the final interpolated data value for the target display point, so these Obtaining the value is essential. Overall System The block diagram of FIG. 4 is the scan converter 24 of the present invention. Its functionality consists of approximately 125,000 pieces of display memory in a 90 degree sector as shown in Figure 1A, scanned approximately 30 times per second by a radial scanner such as 20 in Figure 1. The final interpolated data value for each display point is calculated in real time. This is accomplished by determining the final interpolated data value for each display point in a slice, i.e., a display point on or between a pair of radial lines, and then iteratively applying this operation to each successive slice. Ru. In FIG. 4, the radial scanner 33 is
The analog data obtained along each successive radial line is fed to an A/D converter 35, and this is applied to the samples S ₁₀ , S ₁₁ , S ₁₁ ,
S ₁₂ , S ₁₃ and sample S ₁₀ ′ on radial line R _I ,
Digital samples of data are generated that occur at uniformly spaced points along the radial line, as indicated by S ₁₁ ', S 12 _' , and S ₁₃ '. Since the data used in the calculations for each slice is different, line identification means 36 are provided for obtaining the identification of the line being scanned from the signal of the radial scanner 33. This is accomplished in a number of ways, such as by assigning a digital number to each line, or by identifying a given line within a sector, and counting and identifying lines as it is being scanned. be able to. Once obtained, however, the line identification signal is used by the write control to direct the digital data samples from A/D converter 35 to a storage point in memory 40 in such a way that the radial position along the line is discernible. used by means 38. The following description describes the means for obtaining data samples from memory 40 that define the area encompassing the display points, as well as the signals RERR and θERR representing the radial and angular positions, respectively, of the display points used in the interpolation process. It is related to the means for Means 42 obtains a signal STRTL from radial scanner 33 indicating when the scanner begins scanning along a radial line. When scanning through the display points of the slice corresponding to the line identified by the signals supplied by the line identification means 36, the means DPSG is responsive to each signal STRTL to detect a predetermined position, such as at the origin of the radial line. A display point scanning control signal representing a step order in one of the directions +x, -x, +y, or -y derived from a display point is provided. Although the sequence of steps typically includes those in the +x, -y, and +y directions as shown by the display point scan path indicated by dotted line 31 in FIG. It is also possible for steps performed in The X counter device 46 provides a signal indicating that a step is along the X axis, and the X up/down device 4
8 provides a signal indicating whether the step is in the +x or - direction, Y counter device 50 provides a signal indicating that the step is along the y-axis, and Y up/down device 52 provides a signal indicating whether the step is along the y-axis. ,
Provides a signal indicating whether the step is in the +y or -y direction. X counter device 46 and X
By applying the output of up/down device 48 to an Ru. By applying the outputs of the Y counter device 50 and the Y up/down device 52 to the Y address counter 56,
The y coordinate of the same coordinate point is identified with respect to the initial display point y coordinate. The outputs of the x and y address counters 54 and 56 are respectively applied to the address lines of the display memory DM to direct the final interpolated data FDP to the appropriate position when the final interpolated data value FDP for that point is determined. Radius Calculation The determination of the radius of each display point identified by the display point scanning signal provided by the means DPSG can be accomplished as follows. A signal from the line identification means 36 which, in combination with a display point scanning control signal from the means DPSG, identifies the line whose radial position is to be determined.
To be applied to one input of the adder 60, as explained in connection with FIG.
An appropriate value of sin θ, +Ky·cos θ, or −Ky·cos θ is selected from the memory 58. The angle θ is
The angle of the radius line is fairly close to the central angle of the slice. How close is determined by the error that can be tolerated in angular position. The output of the adder 60 is set to x or y by connecting the output of an OR gate 64, whose inputs are connected to the outputs of the X counter device 46 and the y counter device 50, respectively, to the clock input of the latch circuit 62.
Latch circuit 62 operates whenever there is a step along the axis. The output of latch circuit 62 is connected to another input of adder 60. The adder 60 and the latch circuit 62 together form an accumulator that is responsive to each previous step in the +x, -x, +y, -y direction along the scan path determined by the means DPSG. +Kx generated by
By adding all values of sin .theta., +Kx sin .theta., +Ky cos .theta., or -Ky cos .theta., a signal representing the radius of the display point is generated at the output of latch circuit 62. Display Point Selection Final interpolated data values can be obtained for each display point in the scan path determined by the signal provided by the DPSG, so that it is outside the slice (hereafter referred to as overhead). The time to perform this calculation for a display point located in can be minimized by using the following rule. i.e. 1 increment outside the outer line in the X direction at the sector apex. 2 If outside the outside line and facing outward, drop vertically and reverse the transverse direction of the X direction (change XDIR). 3 If facing outwards in the slice, and if there are no further points in the slice further out in the current transverse raster, and if there are no more points on the subsequent transverse line, then vertically descend and reverse direction (change XDIR).
However, if another point is within the slice on the subsequent line, then continue traversing the current line for another point and then continue with Rule 2. 4 If facing towards the center of the sector, continue until it is inside the slice, i.e. inside the inside line, and drop vertically after addressing the last display point in the current traverse that is inside the slice. and then reverse direction (change XDIR). The final interpolated data values for points outside the slice are not entered into the display memory DM since they are highly inaccurate and can be read by the display memory scanner 66 and applied to the display device 68. Shouldn't. Instead of calculating multiple values and preventing inaccurate data from being stored in the display memory DM, the present invention disables the means to calculate final interpolated data values for display points outside the slice. Utilization of Radius R As previously mentioned, the value of the radius R of the display point indicated by the means DPSG is determined by the latch circuit 62.
appears in the output of The bit representing the radius R is applied to a comparator 70, where it is applied to the maximum radius R _MAX representing the outer radius boundary for the sector.
is compared with the value of The radius R of the display point is
If R _MAX or less, the comparator 70 outputs the AND gate 7
2, and its output is applied to the control input of the display memory DM. A signal indicating that the display point is within that slice, as described below.
THETOK is obtained and applied to the other input of AND gate 72. Thus, if a data value is written to DM, both signals
ROK and THETOK must be positive. The signal ROK is less important than the signal THETOK because incorrect final interpolated data values for a few display points at the edge of the slice are less of a problem than incorrect data values within the slice. The main advantage of ROK is that it smooths the perimeter of the sector. Calculating RERR Equation (6) is the relative radial position of the display point with respect to the data sample point used in the interpolation,
For _example , it shows that a signal must be obtained representing the relative radial _position of the display point _DP ^{in FIG} _. The value of R cannot be used directly when calculating.
It is possible to obtain a signal representative of the radial distance between the outer data sample point S ₃ ¹² and DP for use in the interpolation of the present invention. That is, it is possible to obtain a signal RERR' representing the radial distance between DP and the inner data sample point S ₃ ¹¹ . In the embodiment of the invention, at the point where Kx = Ky = S, the fractional portion of the output of latch circuit 62 is RERR
That is, it is the distance ratio between the distance between the display point and the inner arc and the distance S of the adjacent arc. In general
Kx and Ky are different from each other and different from S. Changes in Kx and Ky that occur when moving the display point change the calculated radius by more than 2S. Also, since it is necessary to take the above into consideration when calculating RERR', it becomes easy if Kx and Ky are less than S. As shown in FIG. 2, Kx, Ky, and S generally all take different values. Output signal R of latch circuit 62
is supplied to one input terminal of subtractor 74, and the output of latch circuit 76 is supplied to the other input terminal of subtractor 74. At the start of scanning the angular radial line, the outputs of all latch circuits are cleared by the signal STRTL. A difference signal RERR' equal to the value of R minus the output value of latch circuit 76 appears at one output 78 of subtractor 74. As a result, a signal RDIR indicating an increase or decrease in R appears at the other output 80. This difference signal RERR' is applied to one input terminal of a comparator 81, and a value equal to S is applied to the other input terminal. Here, if RERR′>S, comparator 8
1 outputs the signal CROSS, and also when RERR'<O, the signal CROSS is output, and the value of RERR' passes through integer multiples of S in increasing and decreasing directions, respectively. signal
CROSS is a radial line as shown in Figure 2.
It is output by scanning from display point DP ₄ located between R ₂ and R ₃ to display point DP ₃ or by scanning in the opposite direction. One input terminal of the adder/subtractor 83 is connected to the output of the latch circuit 76, the other input terminal is connected to receive a value equal to S, and the control input terminal is connected to the output of the latch circuit 76.
RDIR is connected as input. The input terminal of latch circuit 76 is also connected to the output terminal of adder/subtractor 83. When RDIR indicates that R is increasing, adder/subtractor 83 outputs the sum of the output of latch circuit 76 and S to its output terminal, that is, the input terminal of latch circuit 76. Conversely, when RDIR indicates that R is decreasing, the adder/subtracter 83 outputs its output terminal, that is, the latch circuit 76.
The difference between the output of the latch circuit 76 and S is outputted to the input terminal of the latch circuit 76. The clock input of the latch circuit 76 is a signal
Since it is connected to input CROSS,
When the signal CROSS occurs, the input of the latch circuit is transmitted to its output terminal, ie, one input terminal of subtractor 74. A signal representing the fractional distance of a display point such as DP between A ₁₁ and A ₁₂ as shown in Figure 2.
RERR is obtained by dividing RERR' by S using divider 77. However, if S=
If Kx=Ky holds true, RERR at the output terminal of the latch circuit 62 becomes the result of dividing R at the end. In this case, the latch circuit 76, the adder/subtractor 83,
The subtracter 74, comparator 81 and divider 84 are no longer necessary. Calculation of XHAT The value of XHAT is the distance between radial lines measured along the display point sequence containing the display point of interest as shown in FIGS.
XHAT is equal to the sum of +ΔXHAT for each step in the y direction away from the origin (ΔXHAT equals tanθ ₂ -tanθ ₁ ) and -ΔXHAT for each step in the y direction toward the origin. Since the value of ΔXHAT changes for each slice, it is only necessary to apply a line identification signal from the line identification means 36 to the ROM 88 to select the value of ΔXHAT for that line. The output of ROM 88 is applied to an accumulator consisting of adder 90 and latch circuit 92. This accumulator operates similarly to the adder 60 and latch circuit 62 used in the radius calculation.
However, instead of being updated with each movement in the x and y directions, latch circuit 92 is updated only with movement in the y direction. Calculating COUNT The signal COUNT is the distance measured along the display point sequence between the display point and any radial line of the slice. The line identification signal from the line identification means 36, the display point scanning control signal from the means DPSG, and the Y up-down circuit 52.
The y up-down signal from
Select one of the values of tanθ and add it to adder 9
8 input. The line identification signal selects the term with tan θ ₂ corresponding to the angle θ ₂ used for the slice, and the signal from the y up-down circuit 52 in combination with the display scan control signal from the means DPSG is +Ky tan θ. and −Ky tanθ
Choose the appropriate one. The value of +Kx or -Kx is
The selection is made by the steps along the x direction made by the scan control signal. The table below shows the input selection matrix for ROM 96 under the conditions described above. +x is a step to the right increasing the value by 1, -x is a step to the left along the x-axis, -y is a step towards the origin, and +y is a step to the left along the y-axis. This is a step away from the origin.

【table】

【table】

The output of ROM 96 is applied to an adder 98 having its output connected to a latch circuit 100, which is connected by connecting its clock input to the output of OR gate 64 via lead 102. is updated by steps in either the y or x direction. The output of latch circuit 100 contains all negative values that occur when stepping from one display point to another.
It is connected to the input of adder 98 to form an accumulator for producing at the output the sum of the changes in the value of COUNT. Determination of θERR The values of XHAT and COUNT are the angular distances COUNT and XHAT−COUNT used in the interpolation formula.
((9), (10), (11),
(11′)), by XHAT of divider 104.
It is generally easier to divide COUNT to obtain a signal θERR representing the fractional distance of a display point from one line to another. Determining whether a display point is between the radius lines of a slice The determination of whether a given display point is between the radius lines of a slice is performed as follows. The most significant bit of COUNT output from latch circuit 100 is applied to one input of AND gate 108 via inverter 106. As is well known, this bit becomes a "1" when the digital signal at COUNT goes negative such that the output of inverter 106 goes low. Furthermore, XHAT and
The value of COUNT indicates a high state if COUNT is less than XHAT, and a high state if COUNT is less than XHAT.
is applied to decision block 110 which outputs a low state if it is greater than . In this way, if
If COUNT is negative or greater than XHAT, the output from AND gate 108 THETOK?, a situation that only occurs when the display point is angularly outside the slice. is in a low state. THETOK? is applied to one input of AND gate 72, and the other input of AND gate 72 receives ROK? is applied. in this way,
THETOK? is high, indicating that the display point is angularly inside the slice, and ROK? AND gate 72 outputs a high state only when is also high, indicating that the display point radius is less than _RMAX , and the final interpolation applied at the indicated x,y address. data value, display memory
Remember it in DM. Interpolation Read controller 82 obtains multiple data samples from multiple radial lines from memory 40 under control of RDIR and CROSS and applies them simultaneously to the inputs of interpolators 112 and 114.
Two of the data points are located where a radial arc of smaller radius than the display point intersects the radial line of the slice, and two of the data points are located where a radial arc of larger radius intersects the radial line of the slice. It is located at an intersection. When the display point scan control signal from the means DPSG causes the display point scan to intersect the outer or inner radial arc, the signal CROSSs causes the readout controller 82 to
signal that a crossing has been made and
RDIR determines whether the intersection is outward or inward radial. Read control device 82
selects appropriate data points such that four data samples always define the area that encompasses the display point. As before, the newly selected data point can be further away from or closer to the sector apex depending on the values of RDIR and s. For example, the first four data display samples are S ₃ ^11* , S ₃ ^12* , S ₄ ^11* , and
S ₄ ^12* , and the display scan intersects from the display points to points outside the radial arc A ₁₂ within the area defined by these points, then the read controller 82 detects the inner data samples S Samples other than ₃ ^11* and S ₄ ^11* S ₃ ^12* and S ₄ ^12*
and data samples S ₃ ^13* and S ₄ ^13*
Add. If this scan crosses the radius line A ₁₂ again, the intermediate interpolated values obtained by interpolators 112, 114 are provided to interpolator 116, in which the first four data samples are used. By means of switch S ₁ and switch S ₂ in the positions shown, interpolator 1
12 and 114 interpolate in the radial direction, and interpolator 11
6 interpolates angularly, and S ₃ applies data samples on R ₃ to interpolator 112 and data samples on R ₄ to interpolator 114. With switches S ₁ and S ₂ in other positions, the interpolation order is reversed and S ₃ sends the inner data samples to interpolator 112 and the outer samples to interpolator 11.
4. If interpolation is to be done with respect to other additional display points as described in connection with FIG. It is clear that data samples must be obtained from memory 40 and appropriate ones thereof must be made available to the interpolator at the same time. Only one other combination is illustrated in FIG. 4A, as those skilled in the art will readily be able to conceive of the necessary data sample selection and interpolation means. In Figure 4A, the first and second
Interpolated data values of are obtained from the data samples at four data sample points along each of radii R ₃ and R ₄ in FIG. Data sample S ₃ ^10* ,
S ₃ ^13* is sent to the interpolator 118, and the data samples S ₃ ^11* ,
S ₃ ^12* is sent to interpolator 120, data samples S ₄ ^10* ,
S ₄ ^13* is sent to the interpolator 122, and the data samples S ₄ ^11* ,
S ₄ ^12* is applied to interpolator 124 and RERR
is applied to all interpolators. The outputs of interpolators 118 and 120 are connected to an adder 126 that generates a first intermediate interpolated data value I ₁ and
The outputs of 2 and 124 are applied to an interpolator 128 which outputs a second intermediate interpolated data value. Interpolator 1
18 and 122 may take into account different distances of the inner and outer data samples from the DP, with different weighting factors applied to them, if necessary. A detailed circuit diagram of the present invention will be explained below. Scanner, Bus Signal The various trigonometric functions used when interpolating in accordance with the present invention are scanned because the scanner requires information about the angles associated with the radial line from which the data is being generated. A means to identify the lines is required. Various methods can be used, such as generating a pulse on a first line of sectors and providing coefficients that are updated each time the scanner transmits an acoustic pulse into the body.
However, in order to be able to configure sectors under software control, each angle is
Just before receiving the data for that angle, it is uniquely named by a 7-bit word. This data is quantized to 5 bits. To minimize the number of signal buses between the scanner and scan converter of the present invention, the angle and data bits share a common data transfer bus 133, as shown in FIG. 5, which is 12 bits wide. . Scanner 1 in Figure 5
The output of 34 is as shown in FIG. 5A, when the most significant bit has a value of 1, bits 2-8 represent the line number, and when it has a value of 0, Bits 2-6 represent one of 32 levels of data samples. To reduce the amount of trigonometric data that must be stored in ROM, the sector is angularly symmetrical about the center radius line, and bit number 1 is arbitrarily set to a value of 1 when the line is in the left half of the sector. and a value of 0 when it is in the right half. The centerline of the sector has a bit set to one. Least significant bit, in this case bit number 11
includes a pulse called "STROBE" that occurs when the word contains line identification information as well as when the word represents the value of a data sample. Timing Signals The scan converter is clocked by pulses CLK generated by clock circuit 136, but in order to provide each circuit with sufficient time to perform its function, the frequency of the output of clock circuit 136 is , divider 138 to obtain the signal ENABL
The frequency is divided in half by . The inverse of this signal, negative signal NENBL, is provided by connecting an inverter 140 to the output of divider 138. Since the scanner 134 clock may not be synchronized with the scan converter clock circuit 136, the least significant bit signal STROBE from the scanner 134 is applied to a synchronizer 135. Synchronizer 135 can take many forms, but is shown here as a pair of D flip-flops 132, 139 and an AND gate 1.
41 and are coupled as shown. AND, identified as INENABLE, to control the order of operation of various parts of the scan conversion circuitry with respect to words received from scanner 134.
The output of gate 141 is the synchronized signal
STROBE, applied to shift register 142 updated by pulse CLK. If the frequency of clock 136 is 12.4MHz, then
Register output order pulse NINEN0,
The signal STROBE is made high for at least 80 ns and made low for at least 80 ns so that NINEN1 and NINEN2 are synchronized with CLK. Each pulse is low for 80ns, and the three pulses last for only 240ns. Inverted signal INEN0,
INEN1 and INEN2 are each inverter 1
44, 146, and 148. As can be seen, NINEN0 or INEN0 is used to enable the latch, NINEN1 or INEN1 is used to control the write function, and NINEN2 or INEN2 is used to control the counter. Line number identification Output signal from AND gate 141
INENABLE is used to latch circuit 1 to latch the word currently present at the scanner output.
52 through an inverter 150. The signal SIGN with bit number 1 indicating the half sector of the line and bit numbers 2 to 8 indicating the line number are led to the latch circuit 154, and when the latch circuit 154 is enabled, it outputs the line number L#. The SIGN bit appears on one output and the SIGN bit appears on the other output. Bit numbers 2 to 6 sometimes contain line identification information,
Latch circuit 154 is activated only when these bits represent a line number, since at other times they represent the value of the data sample. this is here
The most significant bit indicated as HDR1 is
This is accomplished by "ANDing" the output of OR gate 156 with ENABL and NAND gate 158 to which 1 and INEN2 are applied. In this way, the reason for using INEN1 and INEN2 is
This is because INEN1 may be in one of two stable states with respect to the ENABL signal.
ENABLE has a period of 160ns, while INEN0 is 80ns wide. Therefore, the line number
Both INEN0 and INEN1 are required to ensure that they are latched in sync with the ENABL signal. Also, the STRTL signal is generated in a similar manner. This signal will be explained in detail later. The reason for using the ENABLE signal is to establish the overall pipeline timing for the hardware.
Effectively, a 160ns pipeline time is set by dividing the 12.4MHz clock by 1/2. Thus, each synchronization operation requires 160ns to achieve preparation, propagation delay, and hold time. NAND gate 158 locks latch circuit 154 when HDR1, that is, the most significant bit is 1.
can only generate the low power required to drive the The data present at the input of latch circuit 154 is scan line information. Data Rendering Bit numbers 2-6 are connected to the inputs of latch circuit 160 driven by NINEN0, so whether they represent line information or the value of a data sample, they are is transferred to the data bus 162 as DATA. When these bits represent line information, the qualification signal SWE obtained by connecting an inverter 164 between the line 166 carrying HDR1 and one input of an AND gate 168 provides the information in FIG. Their writing to line memory is prevented. AND
The other input of gate 168 is connected to INEN1. When a word from scanner 134 represents line information, HDR1 is high, so qualification signal SWE must be low. But when this word represents data, HDR1 is low, so when INEN1 occurs, the qualification signal SWE
becomes high. The starting point of the line is used for the interpolation function as mentioned above.
Calculations of RERR and θERR are obtained by successively adding or subtracting certain stored values from respective known initial values. These known initial values can be from any display point, but since the known values of RERR and θERR at the origin are zero, it is easier to use the sector origin as the starting point. . However, this method requires knowing the data sample that occurs at the start of the line. HDR1 occurs at the start of each line, so
It can be used to generate the signal STRTL. One way is to use NAND gate 15
8 and the input of the latch circuit 172. While data is being input, HDR1 is low, so the output of latch circuit 172 is also low. However, L
If # is input, HDR1 is high, so the signal
If NENBL enables this latch, a high output signal STRTL will appear at its output. signal
STRTL is used in Figure 10 to initiate the associated calculations. Writing Data Samples To explain one method of storing data samples, reference is made to FIGS. 5 and 6. In FIG. 6, data bus 162 from FIG.
78, which in turn are connected to the I/O of digital line memories 180, 182, and 184, respectively. Each line memory can store 396 data samples along a line, and two previously written radial lines are read out to generate the data samples needed for interpolation. It is desired that data samples from one radial line of the scanner 134 be written to one memory while the scanner 134 is running. Three-state buffers require a low state to be applied to their drive inputs to pass data to the line memory.
One means for obtaining a suitable control signal NLD is shown in FIG. from lead 166
HDR1 is applied to one input of a NAND gate 186, INENO is applied to the other, and its output is a low state energized MOD3 that outputs a high state on one of the three output lines _M1 , _M2 , _M3 . counter 188
is applied to Each received HDR1 is sent to a NAND gate 186 as a signal to a MOD3 counter.
Output NLD and shift the MOD3 counter to the high state of the next output line. Thus, after three HDR1s, the sequence repeats. Driving the line memories 180, 182, 184 so that data that was present on the I/O can be written requires a low state to be applied to the write enable terminal. Obtaining such signals is accomplished by applying M ₁ , M ₂ , M ₃ to the inputs of NAND gates 190, 192, 194, respectively, and the qualification signal SWE to their other inputs. be done. SWE indicates that the data sample is on data bus 1 so that the outputs of NAND gates 190, 192, and 194 can go low.
62 and causes data to be written to the line memory only when the data sample is on the data bus. This prevents line number data from being written to memory 180, 182, 184. A high on any M ₁ , M ₂ , or M ₃ will cause that NAND gate to output a low state and enable writing to the associated line memory. Thus, if M ₁ is high, line memory 180 is enabled to receive data. However, since each line memory has a common I/O, it is also necessary to interrupt the output channel by applying a high state to the output enable terminal OE while that memory is receiving data samples. It is said that This is the line memory 180, 18
This is achieved by applying M ₁ , M ₂ , and M ₃ to the 2,184 OE terminals, respectively. For example, if
If M ₁ has a high state, line memory 18
Output channels of 0 are not enabled for output. To summarize, M ₁ , M ₂ , and M ₃ increase in sequence.
If M ₁ is high, the 3-state buffer 17
4, the data sample is the I/O of the line memory 180
However, three-state buffers 176 and 178 prevent data samples from reaching the I/Os of their respective line memories 182 and 184. At the same time, the write control input of line memory 180 receives a low state so that data samples can be written into line memory 180. While the output channels of line memories 182 and 184 are enabled for output, line memory 180
The output channel of is not enabled for output.
Thus, when M ₁ is high, data samples can only be stored on line memory 180, and
Since M ₂ and M ₃ are low, data samples previously stored in line memories 182 and 184 can be read. The question now arises as to how to store the samples in sequentially arranged addresses. This is up/down counter 19
6,198,200. first,
A signal NLD at the output of NAND gate 186 is applied to the load inputs L of counters 196, 198, 200 to return them to all zero counts at the beginning of each line. In order for these counters to be able to count in all, a low state must be input to both inverting inputs ENT and ENP. For example, assume a data sample is written to line memory 180 because M ₁ is high. Under these conditions, the input of counter 196
ENP is low for the entire line because the signal M1+SHIFT is coupled to ENP by inverter 195 as described above. Since M1 is always high between lines, they make the state of SHIFT irrelevant. When writing, UND ₁ is high and the counter count is rising. UND1,
UND2 and UND3 are OR gate 202,
M1, M2, M3 to one input of 204, 206
is obtained by connecting the signal NMDECR to the other input. Since M ₁ is high, NMDECR is set so that the count of counter 196 increases.
Regardless of the state of , the output of OR gate 202 is high. The actual count occurs in response to the signal NM1+ADDEN applied via inverter 193 to the ENT input of counter 196. Since NM1, the inverse signal of M1, is low and the input ENT of counter 196 cannot be brought low, a count is made each time ADDEN goes high.
NM1+ADDEN, NM2+ADDEN and NM3
+ADDEN can be obtained as follows. so that the input is high while data samples are being received.
HDR1 is applied to one input of AND gate 205 via inverter 203. Each data sample instead generates a synchronized signal STROBE INENABLE to generate INEN2.
Accompanied by STROBE. When INEN2 goes high, the output of AND gate 205 or the signal
ADDEN is also high. Signal ADDEN is applied to one input of each of OR gates 207, 208, 210, and signals NM1, NM2, NM3 are applied to the other input, respectively. This signal is M
1, M2, M3 to inverters 212, 214, 2
16. When writing to line memory 180, M
1 is high and NM1 is low. or,
The output signal ADDEN of the AND gate 205 is
High in relation to INEN2, counter 196
is counted. As mentioned above, UND1 is high, so it counts up. The effects of the various signals on the other line memories and counters will become apparent in the discussion of reading data samples from the line. In this example, the data samples are line memory 1
Written in 80. At the same time, data samples are read from line memories 182 and 184. If the reading order was always unidirectional, then
The read function will be explained at this point. However, since this is not an example, it is necessary to explain how the signals INCR, DECR, and SHIFT that control the read function are obtained. Display Point Scanning Control Signals The display point scan control signals along the columns and rows of display points required to advance from a given display point, such as the origin of a sector, through the display points in the slice corresponding to a given line number. A means is required for generating a display point scan control signal representative of a step scan. As previously mentioned, the display point scanning control signal can take different forms due to the different motions in the X and Y directions, and can be generated by a computer, or as in this example. ,
Can be obtained from memory. The apparatus of FIG. 7, which will be described below, includes a state machine 220 that generates a series of single bits, and which is indicated by a 0, that a step is along the x-axis along a column of display points. , and by 1 to indicate that the step is away from the origin along the y-axis along the row of display points. In an embodiment of the invention, the first step from the origin of the sector is to the left for slices in the left half of the sector, as indicated by scan path 31 in FIG. to the right for slices in the right half of the sector, as indicated by scan path 31' in FIG. This scanning algorithm is such that every time the y address changes, the direction for the x counter changes from its last setting, i.e. in line 31, after the first y address change, XDIR counts up the x counter. It uses the concept of change as it approaches the center of the sector. y
Moves can still be chained. However, each movement in the y direction is such that when the state machine 220 outputs 0 (x movement), the x counter moves in the last accepted x direction.
This is a change we accepted at XDIR. Also, for slices that lie the same angle on either side of the centerline, y-axis, the scan paths are the same except that the direction of the corresponding step along the x-axis is opposite. However, the 1's and 0's from state machine 220 are the same. The signal XDIR, which is 0 for steps toward the center and 1 for steps toward the outside of the sector along the x-axis, is output by address counter controller 222 to the output of state machine 220. , and the SIGN bit obtained from latch circuit 230. The address counter controller 222 shown in FIG. 7 also receives a signal YINC/
Supply XINC. FIG. 7 will be explained in detail. With bit L# representing the line number and the output of latch circuit 154 in FIG.
The bits representing SIGN are connected to the scanner, latch, and buffer 224, which is controlled by the signal STRTL from the latch circuit 172 of FIG.
It is passed through the buffer 226. This FIFO buffer 226 is configured so that, before the slice is defined and ready for readout, the scanner's two consecutive radius lines are connected to the digital line memories 180, 182,
Two line numbers are stored in two of 84. As each STRTL signal of the radius line is generated, L# in FIFO buffer 226 is advanced. On the sector's third STRTL signal, the L# for the sector's first line is input to the L# translation ROM 228.
Its output is applied to latch circuit 230. In order to explain the operation of the L# translation ROM 228, the seventh
B ₁ , 7B ₂ , 7B ₃ This will be explained with reference to FIG. The radius lines are assigned an even number starting with the outer line in the left half of the sector which is 1/120, and here the seventh
As shown in Figure B, 1 is the SIGN bit indicating that the line is in the left half, and 120 is the line number. Optionally, the centerline is I/O. The outermost line of the right half of the sector is not shown, but is 0/120. FIG. 7B shows the outermost slice of the left half of the sector formed by radius lines 1/120 and 1/118. The data samples are stored in the line memory 1 of FIG. 6 where data samples of lines 1/120 and 1/118 are stored.
80, 182, and 184, but data samples from the dotted line 1/116 are written to the third line memory. As discussed below, the various angular measurements used in determining RERR, COUNT, and XHAT are based on the angle between the outer radius R ₀ and the y-axis in this example. Translation ROM 228 is necessary for the following reasons. All triangles relate to the outside line or left side of the sector. This is FIFO buffer 2
It means the oldest line number of 26. When the output slice of interest is as shown in FIG. _7B1 , the current output from FIFO buffer 226 is line 1/2, meaning that the current angle is that of line 1/2. It is. When the center lines intersect as shown in Figure _7B2 , the FIFO buffer 2
The output of 26 is 1/0. However, as shown in Figure _7B1 , the 0/2 angle and the 1/2 angle are equal, so the 0/2 angle is used. To complete this, the line translation ROM 228 adds 2 to the line number (Figure _7B3 ) and changes its sign to 0. In other words, 0/2 is ROM instead of 1/0
228 and has the same L# as 1/2 shown in FIG. _7B1 . The SIGN bit does not affect L#, but is delayed like the line number for reasons explained below. The remaining lines on the right have 2 added to them. Everything on the left excluding the center line is
Pass through the translation ROM 228. State machine 220 The 3 most significant bits of the 6 bits of the output of the latch circuit 230 representing the line number are the ROM select bits.
is applied to the ROM 232 and the state memory 23
4 to select one of the eight ROMs. Each ROM in state memory 234 contains up to eight slices. The three least significant bits are applied to state memory 234 to select a portion of the selected ROM associated with a particular slice. Each slice has a total of
It contains 256 8-bit words, having 2048 bits. Each bit corresponds to one step in the path scanned through the display points. If this step is in any direction along the x-axis, it is 0. And if this step is along the y-axis, it is 1. A particular x direction is the y direction from the origin as described above.
Determined by the total number of directional movements. The signal STRTL at the output of the scanner latch buffer 224 is applied to start the state machine, address counter 236, to output an 11-bit address at the rate of the ENABLE pulse (pipeline time). Eight of these eleven bits are applied to sequentially select one of the 256 8-bit words of each slice in state memory 234 and provide them to latch circuit 238. The three least significant bits of the 11-bit output of the state machine address counter 236 are ANDed with ENABLE of AND gate 240 to enable latching.
The state machine passes the 8-bit word applied to it from memory 234 to multiplexer 242, which sequentially selects the bits of the word under control of the three least significant bits and sends them to address counter controller 222. Apply. The output of multiplexer 242 is the signal
YINC/XINC. State address decoder State machine, address counter 236
The 11-bit word at the output of is applied to state address decoder 246, which is a ROM, to advance the timing signal. When the count represented by the 11-bit word reaches a predetermined value, which occurs when the function of FIG. 8 is implemented as described below, the signal STRTI, which is the start interpolation signal, is activated by the latch of FIG. is sent to the reset input of circuit 248. Its purpose will be explained later. decoder 246
sends a signal NACCCLR that clears the counter and three latches in the circuit of FIG. 8 that determine R, RERR, COUNT, and XHAT. Decoder 246 also includes address counter controller 22
Outputs a signal NINTL that initializes the output of 2. The signal CTRLD then repeatedly sets the x address counter 249 to the x address of the origin of the sector as determined by source 250 and the y count of the origin as determined by source 254 at the beginning of each line. y address counter 252 is set. Address Controller As described in connection with FIG. 7A, the address counter controller 222 includes the multiplexer 2
For each 0 in the output of multiplexer 242, a signal XCNT is provided to an x address counter 249, and for each 1 in the output of multiplexer 242, a signal YCNT is provided to a y address counter 252.
Address counter controller 222 also controls the signal
XU/D is supplied to the x address counter 249. Furthermore, address counter control device 222
is YINC/ from multiplexer 242
and a path defining signal such as 31 and 31' in FIG. 3 in response to the output of multiplexer 242 and signal SIGN from latch circuit 230.
Supply XDIR. Signals XDIR and YINC/
is used, as described below, to identify the values of the trigonometric functions used by the circuit of FIG. 8 to determine the values of R, RERR, XHAT, and COUNT. Signal obtained from address counter control device
ACCCLK updates the accumulator latch of FIG. 8 which is used in determining the values of R and COUNT, and the signal THETCLK obtained from controller 222 updates the latch of the accumulator of FIG. It is used to update the accumulator latch in Figure 8. Now refer to FIG. 7A. At the beginning of each line, and therefore at the beginning of a new slice, the signal NINTL from state address decoder 246 of FIG. 7 goes low and is applied to the preset input of D flip-flop 256, causing XDIR to go high.
It signals a step along the x-axis toward the outer radius, but the direction with respect to the origin is not determined. NINTL also uses XOR gate 260
whose output is connected to one input of
An eight-stage delay device 258 whose input is connected to the output of a certain D flip-flop 256 is cleared.
The other input of XOR gate 260 is connected to receive the SIGN bit from latch circuit 230 shown in FIG. The output of XOR gate 260 is XUP/. If this line is in the left half of the sector, SIGN is high, so the output of XORN 260 is low, indicating a count down, ie, to the left. If this line is in the right half of the sector, SIGN is low, so the output of the XOR 260 is high, indicating a count up. Control of XDIR is accomplished as follows. YINC/ from multiplexer 242 shown in FIG.
is applied to one input of AND gate 262,
and ENABLE is applied to the other. If the next step is still outward,
Since YINC/ is 0, AND gate 26
2 pressure is low. This output is applied to one input of XOR 264, the other input of which is connected to the output XDIR of D flip-flop 256. Since XDIR is high for outward movement, the output of XOR264 is high and
XDIR remains high. But if YINC/
If XINC is 1, indicating movement from the origin along the y-axis, the output of AND gate 262 is high when ENABLE occurs;
Bring the output of XOR 264 low and bring XDIR low to indicate a step toward the center of the sector with the next movement of x. Now the direction of the step along the x-axis and XUP/
Since DN is known, the signal XCNT remains supplied for each step of x. To do this, YINC/ is applied to a nine stage delay 266, which is also cleared by NINTL. The output of the 9-stage delayer 266 is connected to one input of an AND gate 268 and to an input of an AND gate 27.
Connected to the inverting input of 0. ENABL is then applied to both other inputs. If YINC/
is low, the output of AND gate 268 is low, so there is no count of y, but AND
Since the output of gate 270 is high, XCNT is high, causing x address counter 249 to count up or down depending on whether XUP/ is high or low. If YINC/ is high, indicating a y step, the output of AND gate 268 goes high, causing y address counter 252 to count up. The purpose of delays 258 and 266 is to clear previous data through the interpolator of FIG. They are CLK after ENABLE qualification
Updated by. However, D flip-flop 256 is updated only by CLK. CLK is also connected to one D
is applied to the clock input of synchronizer 272 which has an input. Another D of synchronizer 272
The input is connected to the output of AND gate 262,
The corresponding output is connected to the third D input, and its corresponding Q output provides the signal THETCLK. x and y address counter 24 shown in FIG.
The outputs of 9 and 252 are each connected to a latch circuit 274.
and 276, which in turn are connected to buffers 278 and 280, respectively. Both buffers 278, 280 have a signal ENABLE applied to their EN inputs. in this way,
For each signal ENABLE, the x and y addresses are applied to leads 282 and 284, respectively, and this is passed along the bottom of FIG. 10 to the display memory DM' of FIG. Determination of R and RERR Now, refer to Figure 8. The L# bit from the output of latch circuit 230 in FIG. ,
and +cosθ are supplied to the input address of the ROM 286 which stores the values. Figure 8A shows XDIR and
A truth table is shown for a given line showing the output of ROM 286 for different combinations of bit values of YINC/. ROM286 is suitable
Can be programmed to provide 12-bit output. The 12 bits are used to limit the fractional number coming out of ROM 286 and applied to the input of latch circuit 286. Its output is also applied to one input of adder 290.
A latch circuit 292 is coupled between the output of adder 290 and another input thereof to form an accumulator. The output of latch circuit 292 contains a fractional portion of the radius of interest, and its five most significant bits are the desired signal RERR. It is represented by 5 bits, but this addition used all 12 bits to avoid too many accumulated errors, ie, a situation where there are more than 1000 sins and cos to add and/or subtract. The latch circuit 292 is cleared at the beginning of the line by the signal NACCLR obtained from the state address decoder 246 of FIG.
Updated by ACCCLK. As seen in FIG. 7A, signal NACCCLR is derived from ENABLE and controls the rate of steps through the display points. Thus, each movement in x and y adds an incremental amount (+sin θ, +cos θ) to the past calculation of radius. As shown, the integer part of the radius calculation consists of the instructions for the accumulator carry,
It is maintained in radius counter 294 under XDIR and YINC/. The values of Kx, Ky, and the distance between the data samples along the radius line are all equal to 1 in this example, so
Connecting the signal YINC/and the carry output of adder 290 to radius counter 294, which counts the number of carries and generates a signal R equal to the integer value of the data sample separation within the radius of each display point. Radius counter 294 also outputs a signal INCR when the radius R increases through an integer value of R, and outputs a signal DECR when the radius decreases through an integer value of R. Signal R is connected to the radius limit signal from source 298 and to comparator circuit 2 to go high whenever the radius R of the display point exceeds a defined limit.
96. The output of the comparison circuit 296 is
ROK? It is. Signals RERR, INCR, DECR, and ROK? is passed through latch circuits 300 and 302. The signal RERR passed through the interpolation means of FIG. 10 is shown and ROK? is passed through delay stage 304 to one input of NAND gate 306. The signal THETOK obtained as described below? When high, indicates that the display point is within the slice. Signal THETOK is applied through delay stage 304 to the other input of NAND gate 306. The output of the NAND gate 306 is the latch circuit 3
08, and its output is applied to buffer 310
is applied to Like this, ROK? or
THETOK? If either of the buffer 310 output NVALD? is low? becomes high.
NVALD? is the display memory in Figure 10.
Guided by DM′. If NVALD? is low, the final interpolated data value obtained for the display point by the interpolation means of FIG. 10 is input into the display memory DM'. Signal INCR and
DECR is used to control the read functions of two of the line memories 180, 182 and 184 in FIG. Radius Counter 294 The circuit diagram of the radius counter 294 in FIG.
Shown in Figure B. In the figure, from adder 290 YINC/
XINC and carry signal, signal R, INCR and
One logic circuit for obtaining DECR is shown. The carry signal is 1 if the radius in adder 290 increases and passes through an integer value, and the carry signal is 0 if the radius increases and does not pass an integer value. Conversely, if the radius in adder 290 decreases and passes through an integer value, the carry signal is zero. And if the radius decreases and does not pass through an integer value, the carry signal is 1. If the fractional portion of this radius was zero, then the radius counter output indicates a radius of the display point equal to the radius of one of the data sample points. YINC/ passes through a two-stage delay device 312
is applied to one input of OR gate 314, and XDIR is applied to one input of OR gate 314 through delay device 316.
4 is led to the other input. The output of OR gate 314 is connected to the up/down control input of up/down counter 318 and to one input of XOR 320. The other input of XOR 320 is connected to the carry output of adder 290, and the output of XOR 320 is different from the input of AND gates 322 and 3 to which OR gate 314 is connected.
It is connected to the inverting input of 24. OR gate 3
The output of 14 is connected to the other inverting input of AND gate 324 and to the non-inverting input of AND gate 322. NENBL in FIG. 5 is applied to the drive input of the up-down counter 318,
And the output of XOR 320 is connected to the drive input of the same counter. The signal INCR is
at the output of the two-stage delay device 326 connected to the output of the AND gate 322, and the signals DECR, AND
a two-stage delay device 32 connected to the output of gate 324;
It is at the output of 8. CLK is the clock input of the up/down counter 318 as well as the delay circuit 31.
2, 316, 326, and 328, and NACCCLR is applied to the input of up/down counter 318. If the radius does not pass through a radial boundary such as the radial arc in Figure 3, both INCR and DECR will be 0.
It is. But if it increases through the radial boundary, INCR is 1 and DECR is 0. And if it decreases through the radial boundary, INOR is 0 and DECR is 1. Determination of XHAT Refer again to Figure 8. In this example, tanθ ₂ −
A value of ΔXHAT equal to tanθ ₁ (where θ ₂ is the angle from the center of the sector to the outer line of the slice, and θ ₁ is the angle of the inner line) is stored in ROM 330 for each radius line. has been done. The L# signal from the output of the latch circuit 230 in FIG.
By applying 330 address inputs, △
Select the corresponding value of XHAT. The output of ROM 330 continues for the entire line and is applied to the input of adder 332. The output of adder 332 is applied to latch circuit 334, which receives the output from state address decoder 246 in FIG.
Cleared by NACCCLR and updated by THETCLK from address counter controller 222. The output of the latch circuit 334 is
connected to another input of adder 332 to form an accumulator, and which
updates the accumulator with each y movement, producing a value of XHAT at the output of latch circuit 334, which is the sum of ΔXHAT for each step of y. A large number of bits are used in the feedback to adder 332 to prevent too large an accumulation error. Also 16 bits are used in this accumulator, and this is
The 4 most significant bits are used for the integer part of the XHAT. Determination of COUNT The signal representing L# from the latch circuit 230 of FIG. ₂ is applied to ROM 336 to select one of the values. The angle θ ₂ is the angle between the outer line of the slice and the center line of the sector, therefore the value of tan θ ₂ is
Depends on the L# selected. A latch circuit 338 is connected between the output of ROM 336 and the input of adder 340, and the output of adder 340 is directed to latch circuit 342.
Latch circuit 342 is cleared by NACCCLR from state address decoder 246 of FIG. 7 and updated by signal ACCCLK from address counter controller 222 of FIG. The output of latch circuit 342 is output to adder 340 to sum all values selected from ROM 336 for each step indicated by display point scan control signals YINC/ and XDIR.
connected to another input. This is as measured from the outside line of the slice, whether the slice is in the left or right half of the sector.
It is a COUNT value. Eight bits are required for the sum calculation, but 16 bits are used in the feedback loop to reduce cumulative errors. 4 bits are used for the integer part of COUNT.
However, unlike RERR and XHAT,
When the display point is outside the outer line of the slice, COUNT has a negative value. Therefore, the most significant bit is used by latch circuit 3 to indicate whether the value of COUNT is positive or negative.
42 output. Determination of θERR As mentioned above, θERR is actually determined by COUNT/
It is XHAT. This division can be performed with 16 bits each, but this precision is not necessary in this example, and 5 bits of precision is sufficient, so
Appropriately selected 5-bit fields from both COUNT and XHAT provide the necessary bit resolution for this device. Since XHAT is the larger of the two numbers and is non-negative, it is simply shifted to the left until the most significant bit is a non-zero value. Then COUNT is shifted by the same amount. The purpose of ROMs 344, 346, 348 is to provide the ability to shift 0-3. The 5-bit outputs of ROMs 346 and 348 pass through a latch circuit 350 to a divider ROM 352.
and it was scaled
Divide COUNT by the scaled XHAT and apply the result to latch circuit 354. Then, it outputs a desired signal θERR which is guided to the interpolation pipeline shown in FIG. Signal indicating whether the angle is within the slice
THETOK? To obtain COUNT, the bit representing the sign of COUNT is routed through an inverter 349 and a latch circuit 350 to an AND gate 356.
If COUNT is positive, this bit is high, indicating that the display point is not outside the outer line angle θ ₂ , but if this
If COUNT is negative, AND gate 356
The input to is low and THETOK? does not indicate.
Comparator circuit 358 is connected to receive COUNT and XHAT, and if COUNT
If less than XHAT, output a high bit to indicate that the display point is not inside the inside line of the slice, and if COUNT is
If it is greater than XHAT, output a low bit to indicate that the display point is inside the inner line. This bit of the output of comparator circuit 358 is passed through latch circuit 350 to AND gate 35.
connected to another input of 6. Its output is passed through a latch circuit 354, which sends a signal THETOK? , and this causes the delay means 3 to occur as described above.
Through 04, ROK? For inputs other than those to which
It is passed to the input of NAND gate 306. Reading from Line Memory As previously discussed, in accordance with embodiments of the present invention, the final interpolated data value for each display point is determined by interpolating two pairs of data samples that define the subslice in which the point is located. obtained by.
As shown in FIG. 9, the final data values of DP5 and DP6 are obtained from data samples S ₂ , S ₃ , S ₂ ′, S ₃ ′ that limit one subslice, but for DP7. The final data values of the data samples S ₁ , S ₂ , S ₁ ′,
obtained from S ₂ ′. Since DP8 is in the same subslice as DP5 and DP6, its final data values are derived from the same data samples they were in, ie, S ₂ , S ₃ , S ₂ ', S ₃ '. in this way,
The means for reading data samples from the line memories 180, 182, 184 of FIG. 6 must be capable of retaining, advancing, or retracting selected data samples along each radial line of the slice. No. Line memory 18 from which data samples are read
Two choices among 0,182,184 are signal
It is determined by which two of M ₁ , M ₂ , and M ₃ are low. In FIG. 6, the signals M ₁ ,
M ₂ and M ₃ are line memories 180, 182, and
and 184 output enable terminals.
If M ₁ is high, the line memory 180 is
It is enabled to receive data, data is input into it, and its output channel is blocked so that data cannot be read from it. M ₂ and M ₃ are low to prevent line memories 182 and 184 from receiving data. However, M ₂ and M ₃ open the output channels of line memories 182 and 184 to read data from them at the addresses set by counters 198 and 200. The outer radius line is to the left in the left half of the sector and to the right in the right half. In this embodiment of the invention, the signal COUNT is always associated with the outside line so that data samples from the outside line must be separated from data samples on the inside line. This function is provided by multiplexers 360 and 36
2. A different input of each multiplexer is connected to a line memory 180, 182, 184.
are respectively connected to each I/O channel of
Multiplexer 360 directs data samples from the outer radius line to bus OL, and multiplexer 362 directs data samples from the inner radius line to bus IL, as described below. The controller of multiplexer 360 controls signal M ₂
an inverter 363 connected between the source of XOR 370 and one input of AND gate 366, an inverter 368 coupled between the output of
are the signals SIGN and SIGN applied to their respective inputs.
M ₁ and the output of XOR370 is AND gate 3
72 and signal M ₃ is applied to the other input of AND gate 372 via inverter 374 . The output of AND gate 366 is applied to the least significant bit of multiplexer 360, the select A input LSB SEL A, and
The output of AND gate 372 is output to multiplexer 36
Most significant bit of 0, select B input MSB.
Applied to SEL・B. With these connections,
The outside line is selected as shown in the table of FIG. 6A and applied to the outside line bus OL. The controller for multiplexer 3626 controls the signal
An inverter 376 connected between the source of M ₃ and one input of AND gate 378, an inverter 380 connected between the source of M ₂ and one input of AND gate 382, one connected to the source of SIGN. consists of an XOR383 having an input of M1 and another input connected to the source of _M1 , and
The output of XOR 383 is connected to the input of AND gate 382 and also to one input of AND gate 378 via inverter 384.
The output of AND gate 378 is multiplexer 3
62 most significant bits, select B input MSB.
SEL.B, and the output of AND gate 382 is the least significant bit of multiplexer 362,
Connected to select B input LSB/SEL/A. With these connections, the inside line is selected as shown in FIG. 6B and applied to the inside line bus IL. As shown in FIG.
The output read OL from the shift register 386
and the output lead IL from multiplexer 362 is connected to a shift register 388. QA of shift register 386 and
The QB outputs each provide successive data points on the outer line to means described below for obtaining a first intermediate interpolated data value, and to a shift register 388.
The QA and QB outputs each provide successive data points on the inner line to means described below for obtaining second intermediate interpolated data values. SELECTING DATA SAMPLES FROM LINE MEMORY Signals INCR and DECR provided by radius counter 294 of FIG. 200 to move forward, stay at the same point, or move backwards. If the radius of the display point becomes larger than that of the data sample, as when stepping from DP ₇ to DP ₈ in Figure 9, INCR is high, and when stepping from DP ₆ to DP ₇ , If the radius of the display point becomes smaller than that of the data sample, then its
DECR becomes high. If the integer part of the radius does not change, as when stepping from DP ₅ to DP ₆ ,
Since both INCR and DECRB remain low,
The counter does not change. As explained below, the signal
The counter does not change until SHIFT appears. SHIFT appears in response to the respective high states of INCRN and DECR. At the beginning of the line, as can be seen from _FIG .
until it has a radius larger than that of S ₁₁ ′.
A special situation arises because both INCR and DECR are low. Therefore, as shown in Figure 6, INCR or DECR is used in relation to the two memories being read.
None of these can generate the signal SHIFT needed to change the counter. In these situations, the counter is controlled as follows. At the beginning of each line of data received from scanner 134 of FIG. 5, a signal STRTL is generated at the output of latch 172 of FIG. 5 and begins scanning the display points as described in connection with FIG. used for. The STRTL signal is applied to the set input of latch circuit 248 and to two stage shift register 392. 2-stage shift register 39
2 is enabled by NENBL, so it outputs two consecutive high state pulses STRT1 and STRT2 to the separate inputs of OR gate 396. In effect, STRTL is a shift register 392
for input to OR gate 396.
Generates two delayed versions of STRTL. OR
The output of gate 396 is applied to one input of AND gate 398, and ENABLE is applied to the other, and by coincidence of the two, AND gate 398 is applied to the SHIFT signal so that the counter can Output a certain high level. For the first two samples of each line of the slice (the first sample of each line is at the origin) occurring simultaneously with STRT1 and STRT2, when sufficient time has elapsed for the signals RERR and θERR to occur, the signals STRT1 is sent from state address decoder 246 in FIG. 7 to the reset input of latch circuit 248. Since latch circuit 248 is set by STRTL, STRT1 clears it. The time between STRTL and STRT1 is
Indicated by WAIT. When STRT1 occurs, latch circuit 248 is activated by latch circuit 399.
is enabled and to which the signals INCR and DECR from radius counter 294 of FIG. 8 are applied. INCR and DECR are latch circuits 399
, respectively, are changed to MINCR and MDCER, and passed through separate inputs of OR gate 396.
And when it is high, a signal is sent to the output of AND gate 398.
SHIFT can occur. Also, MDECR
is input to inverter 395 to generate signal MNDECR. Counter control by SHIFT To enable counters 196, 198, 200 to count, their inputs ENT and
ENP must be in a low state. Assume that data samples are being written to line memory 180 such that M ₁ is high and both M ₂ and M ₃ are low. In the explanation of the writing function, M
1 is high, causing the ENP input of the counter 196 for the line memory 180 to be low for the entire line, and its count is advanced each time the signal ADDEN applied to the ENT input occurs. counter 1
98 and 200, NM2 and NM3 are high for the entire line. They are then applied to the individual ENT inputs via inverters 197 and 199 so that these inputs are held low during that line. Signals M2+SHIFT and M3+SHIFT are applied to the ENP inputs of counters 198 and 200 via inverters 400 and 402, respectively. Since M2 and M3 are low for the entire line, they cannot drive the ENP input low. In this way, only SHIFT has counter 1
98,200 can be counted. Signal M
1+SHIFT, M2+SHIFT, and M3+
SHIFT is OR gate 40 for M1, M2, M3
8,410,412 inputs, and
obtained by applying SHIFT to those other inputs. The line memory 180, 182 or 184 is read out and the corresponding counter 196, 19
8,200 counts in response to the signal SHIFT as just described, the counter
Counts up when UND1, UND2, and UND3 are high, and counts down when UND1, UND2, and UND3 are low.
As was done when considering the write function,
Assume that display samples have been written to line memory 180 such that M1 is high, M2 and M3 are low, and NMDECR is high.
Under these conditions, the OR gate 20 in Figure 5
The output UND1 of 2 is high, so that the counter 196 for the line memory being written
counts up when necessary. OR gate 20
4 output UND2 and OR gate 206 output
UND3 is also high, so counter 198
and 200 are set to count up. But if MDECR is low, they are set to count down. When counters 198 and 200 are counting up and down, the display samples at the corresponding addresses in line memories 182 and 184 are stored in shift registers 386 and 3, as shown in FIG.
It is placed in the Q _A section of 88. SHIFT also controls shift registers 386 and 388 via the following logic circuitry in FIG. SHIFT is AND
It is applied to one input of gate 409 and to one input of AND gate 411. Also
MDECR is the other input of AND gate 409,
Then, through the inverter 413, the AND gate 41
1 to the other input. AND gate 40
The output of 9 is connected to the left shift input of shift registers 386 and 388, and the output of AND gate 41
The outputs of 1 are connected to their left shift inputs. When SHIFT goes high and MDECR is low, AND gate 411 causes shift registers 386, 388 to shift the data samples in them to the right and receive new data samples at their inputs. However, if SHIFT goes high and MDECR goes high, AND gate 409 shifts the data samples in shift registers 386 and 388 to the left, i.e.
Replace Q _A with Q _B , Q _B with Q _C , etc. Shift registers 386 and 388 are eight words long, providing the ability to protect by six data samples, with two words remaining in the registers. SHIFT is STRT1 and STRT2 present at the inputs of OR gate 396 in FIG.
appears twice at the start of each line due to the action of . This operation converts the first two data points S ₁₀ , S ₁₁ of FIG. 3 for line Ro and S 10 ', S ₁₁ for line R ₁ to
S ₁₁ ′ in their respective shift registers 386
and 388 Q _B and Q _A areas. However, the display point scanning signal YINC/,XDIRN
No further changes occur within the four data samples until S ₁₁ , S ₁₁ ' result in a step to a display point having a radius greater than display points S 11 , S 11 '. And at that point, signal INCR goes high, causing SHIFT to go high and counter 19
8 and 200, and data samples S 11 and S ₁₂ of outputs Q _B and Q _A of shift register 386, and data samples S _{11 ′} and S ₁₂ ′ of outputs Q _B and Q _A of shift register 388. You can move the shift register to the right to apply the voltage. Now, the display point scanning signal is S ₁₁ and
Assume that we take a step to a display point with a radius smaller than S ₁₁ ', ie, a step back on the inner radial boundary of interest. signal
Since DECR, like MDECR, is now high and M2 and M3 are low, signals UND2 and UND3 are low, setting up/down counters 198 and 200 to count down. SHIFT counts down the counter and, in combination with MDECR, shifts shift registers 386 and 388 to the left, shifting display points S ₁₀ , S ₁₁ and S ₁₀ ′, S ₁₁ ′ to Q _B of registers 386 and 388, respectively. and return to Q _A position.
The steps to the next display point are S ₁₁ and
If S ₁₁ ′ causes the third intersection of a certain arc line, then
The samples S ₁₂ and S ₁₂ ′ missing from the register are
Since the read address is controlled by SHIFT as described above, line memories 182 and 184
Since the next points from are samples S ₁₂ and S ₁₂ ′,
No problems arise. Interpolation Figure 10 will be explained. The data samples of the QA and QB outputs of the shift register 386 are transferred to the multiplication ROMs 414 and 416.
of the shift register 388.
The QA and QB output display samples are applied to multiplication ROMs 418 and 420, respectively;
The signal RERR representing the radial position of the display point is then latched into the latch circuit 415 and then applied to all four ROMNs 414, 416, 418,
420. The data samples are represented by 5-bit numbers, like the signal RERR, which is of course a fraction. With ROM416 and 420
RERR×QR value, and ROM414 and 418
is programmed to perform the appropriate multiplication of (1-RERR) x QB data values. ROM414
The output of the adder 4 passes through the latch circuit 414'.
22, and the ROM 416
The output of the adder 4 passes through the latch circuit 416'.
22 other inputs, so its output is the first
becomes the intermediate interpolated data value _I1 . Similarly ROM41
The outputs of 8 and 420 are routed through latch circuits 418' and 420', respectively, to the inputs of adder 424, so that its output becomes the second intermediate interpolated data value _I2 . The first and second intermediate interpolated data values I ₁ and I ₂ are passed through latch circuits 422' and 424', and then multiplied by
Applied to the inputs of ROMs 426 and 428, respectively. Signal θERR from the output of latch circuit 354 of FIG.
Latch circuit 430,
After passing through 432 and 434, multiplication ROM4
26 and 428. ROM426 is 1
-θERR is multiplied by the output of latch circuit 422', and ROMT 428 multiplies θERR by the output of latch circuit 424'. The latch circuits 426' and 428' are connected to the ROM 42, respectively.
6 and 428 and different inputs of adder 436 to produce the final interpolated data value at its output. After passing through latch circuits 438 and 440 and buffer 441, the final interpolated data value is placed at the x,y address in display memory DM' determined by x and y sector address counters 249 and 252 of FIG. NVALD at the output of AND gate 306 in FIG. 8 is high if the display point is angularly and radially within the slice. memory
DM' can be read out by the DM' readout controller 4 in any desired manner.
42 and the signal is displayed on the display 44.
4. Summary of Operation The table below shows the display points shown in Figure 9.
Display point scanning control signals XDIRN and YINC/ and INCR for DP ₅ to DP ₁₄ ,
Displays the radius value, COUNT and XHAT along with the states of DECR, XUP/DN, XCNT and YCNT, and where DP ₅ is the initial This is a display point. Usually the initial display point is at the origin of the sector where all these values are zero, but iterative addition can start from any display point for which this value is individually known. As previously mentioned,
XDIR=1 indicates a step from the center of the sector, YINC/=0 indicates a step along the x-axis, and YINC/=1 indicates a step along the y-axis away from the origin. When a step from one display point to another does not intersect the radial boundaries of the subslice,
INCR and DECR can both be 0, but if either is 1, this step crosses such a boundary. XCNT
A value of 1 for YCNT and YCNT indicates a step along each axis. 11 and 1 to further aid in understanding the operation of the embodiments of FIGS.
Figure 2 shows the timing of the various signals used. The points in the circuit at which these signals appear are indicated by the corresponding circled letters.

【table】

Other Examples To increase the resolution of a portion of an image, the radial lines of the scanner are moved closer together within that portion. The scan converter of the present invention is constructed by varying the 1's and 0's in the memory of the state machine of FIG. It is possible to adapt to such a format by changing the stored value of . The sampling rate of the A/D converter is then such that it is desirable to interpolate along the radial direction, but with advances in technology, increasingly higher sampling rates can be expected; This interpolation is not necessary. In such cases, you can now select an appropriate display sample from each radius line.
It is further necessary to determine INCR and DECR. Then, it is further necessary to perform angular interpolation. The system described here is useful if the signal
This is how it works if RERR is set equal to zero. FIG. 13 shows a variation of this system, in which ROM 414 and 416 of FIG.
is replaced with ROM446 and ROM418
and 420 are replaced with ROM 448, and ROMs 426 and 428 are replaced with ROM 450. The latch circuit has been omitted for simplicity. ROMs 446, 448, and 450 have the same configuration. Each is RERR,
θRERR includes different storage outputs for all possible combinations of error signal and data sample values. As shown, signal RERR is applied to ROMs 446 and 448 and signal θERR is applied to ROM 450 so that first intermediate interpolated data values I ₁ and I ₂ are obtained at the radial position of each display point; A final interpolated data value FDP is then obtained at the angular position of the display point. In this case, data samples S ₁ and S ₂
is along one radius of the slice,
and data samples S ₃ and S ₄ are along other radial lines. However, as mentioned above,
Signal θERR is applied to ROM446 and 448,
And since the signal RERR can be applied to the ROM 450, the first and second intermediate interpolated data values
I ₁ and I ₂ are the angular positions of the display points. In this case, S ₁ and S ₂ lie along a radial arc, and S ₃ and S ₄ lie along another radial arc. FIG. 14 shows a single ROM, and this includes the three ROMs 446, 448, 4 of FIG.
All 50 functions are performed internally. FIG. 15 shows another embodiment of the invention, and in which the values of RERR and θERR for each display point are previously determined and stored in ROM 454.
Since the signals RERR and θERR are not actively available when the display points of the slice are being scanned. Display point scanning control signals XDIR and YINC/ are provided by means 456 and are
The address is determined by counters 458 and 460 as described above. Signal STRTL
To reduce the number of pins applied to ROM 454 and required, the word representing the first line of a sector can be used by means 462 to synchronize the signal at the beginning of each sector scan. From the x, y address of the display point,
ROM 454 selects the appropriate storage values for INCR and DECR to be used as described in FIGS. 5, 6, 8, and 10 to retrieve the correct data samples S ₁ , S ₂ , S ₃ , and Select _S4 . RERR and θERR for each display point, and
The final data values for all possible combinations of DATA are stored in ROM 454. The appropriate final data values are RERR, θERR, and
Selected from the digital value of DATA. Thus, ROM 454 is a means responsive to the data samples and display point scan control signals to determine the final interpolated data value for each display point. The scan converter of the present invention is also capable of magnifying selected portions of the image between any two radial lines and within a predetermined radial range. this is,
means for dividing the RERR for each display point of the small portion of the image by a magnification factor m; and means for dividing the RERR for each display point of the small portion of the image by a magnification factor m; This can be done by providing a means for multiplying XHAT and COUNT for. It is also possible to scan small parts of the image at high speeds to brighten the image of rapidly moving objects. Instead of using a single radial position, two
can be calculated into two radial positions. Two constants ΔR ₂ and ΔR ₁ are chosen for each line within the sector. ΔR ₂ is routed to the first accumulator and ΔR ₁ to the second accumulator. The two accumulators are updated each time movement in the y direction is indicated by the display point scanning signal. The first accumulator uses θ ₂ when calculating the radius corresponding to the distance from the sector vertex along the outer line to the intersection of a row of display points DP of interest. The second accumulator uses θ ₁ when calculating the radius corresponding to the distance from the sector apex along the inner line to the intersection of the same rows as described above. In order to properly move the two shift registers individually so that the data present at the QA and QB outputs from each shift register are close to their respective radius calculations,
Each radius counter has their own signal INCR and
Generate DECR. The two radius calculations are then RERR _O ¹¹ for the outer line, and for the inner line
Generates two RERR signals called RERR _i ¹¹ . These signals are used to interpolate the data in each shift register. The result is two intermediate interpolated data values, each in close proximity to two sample data values that are not necessarily at the same radial excursion from the vertex. The intermediate interpolated data value is at the intersection of the current output display column and the two scan lines being read from the target line memory. These two intermediate data values are primarily signals
It is used in a similar manner to the current method of correcting for θERR using COUNT and XHAT. The result is a COUNT and
is the final data value obtained by . Enlargement of a selected region can be accomplished by multiplying θERR for each display point within this region by a magnification factor m and dividing RERR by m. As described above, the present invention obtains interpolated values along the rows and columns in the x-axis and y-axis directions, and adds data repeatedly, so it can create wavy shapes in an extremely short time. A true tomographic plane without unnecessary lines can be reproduced on the display device. Note that in this example, interpolation was performed linearly, but
Various curves can also be used to obtain interpolated values.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention. Figures 1A, 1B, and 1C are graphical representations of the functions of each device in Figure 1. Figure 2,
FIG. 3 is a diagram used in the basic calculation of the present invention. FIG. 4 is a detailed block diagram of the present invention.
Figure M is a combination diagram of Figures 5, 6, 7, 8, and 10. 5, 6, 7, 8 and 10 are circuit diagrams of the present invention. FIG. 4A is another embodiment of the interpolation means of FIG. FIG. 5A is a digital information form diagram of the present invention. Figures 6A and 6B are truth tables for the multiplexer of the present invention. FIG. 7A is a circuit diagram of the address counter control device 222 shown in FIG. 7B, 7B ₁ , 7B ₂ and 7B ₃ are circuit diagrams of the translation ROM 228 of FIG. FIG. 8A is a truth table of the ROM 286 of FIG. FIG. 8B is a circuit diagram of radius counter 294 of FIG. FIG. 8C is a truth table of the ROM 336 of FIG. FIG. 9 is a diagram for explaining an embodiment of the present invention. 11 and 12 are timing charts of an embodiment of the present invention.
13, 14, and 15 show other embodiments of the present invention. 20: scanner, 22: A/D converter, 24: scan conversion device, 26: display memory, 28: reading device, 30: display means.

Claims (1)

[Claims] 1 Obtaining interpolated values from data samples occurring at the intersections of a radial line forming a slice of the sector and equally spaced radial arc lines having the same center as said radial line, said interpolated values being
In a scan conversion device represented by display points arranged at the intersection of orthogonal columns and rows respectively parallel to an axis, the spacing of said rows being Kx and the spacing of said columns Ky. means for providing four data samples occurring at the intersections of a radial line and two radial arc lines, representing the radial position of a display point within the selected subslice with respect to the radial arc line of said subslice; means for providing a first signal; and means for providing a second signal representative of the angular position of said selected display point with respect to two radial lines of said subslice; means responsive to a selected one of the first and second signals to obtain at least one intermediate interpolated value of one of the radial position and angular position from data samples on one side; responsive to a selected one of the first and second signals to obtain at least another intermediate interpolated value of one of the radial position and angular position from data samples on the other side of the display point; means for the other of the first and second signals and the intermediate interpolated value to obtain a final interpolated value for the selected display point on the other side of the radial and angular positions; means for responding, sequentially considering the display points in the slice to determine the first signal from the radial position (Rj+1) of the display point to the radial position (Rj) of the immediately preceding display point; The first and second distances (COUNTj+1,
XHATj+1) by adding or subtracting second and third constant distances determined by slices to each of the first and second distances (COUNTj, XHATj) to the immediately preceding display point.