JPH0373182B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Example (a) One Implementation Explanation of Examples (Figures 2 and 3) (b) Explanation of Other Embodiments Effects of the Invention [Summary] In a parallel-to-serial conversion circuit using a plurality of shift registers, the data of the last bit is fixed ( By providing a plurality of shift registers of (n+1) bits and an OR circuit that ORs the outputs of the plurality of shift registers, the output after the shift operation of the shift registers is used as the final bit data, and the OR circuit This makes it possible to output serial data using a plurality of shift registers.

[Industrial application field]

The present invention relates to a parallel-to-serial conversion circuit that converts parallel data to serial data using a plurality of shift registers, and in which the serial outputs of the plurality of shift registers are sequentially output without the need to specifically select the outputs of the plurality of shift registers. This invention relates to a parallel-to-serial conversion circuit that can perform

For example, in a magnetic disk device or the like, it is necessary to convert parallel data given from a higher level into serial data, and a parallel-to-serial conversion circuit is used for this purpose.

This parallel/serial conversion circuit (hereinafter referred to as P/S)
Shift registers that can perform parallel-to-serial conversion through a shift operation are generally widely used as conversion circuits (referred to as conversion circuits).

[Conventional technology]

As such a P/S conversion circuit, as shown in FIG. 4, one that performs parallel-to-serial conversion by alternately using two shift registers 1 and 2 is known.

In this P/S conversion circuit, assuming that the given parallel data is n bits, shift registers 1 and 2 for n bits are provided, and a control circuit 3 alternately loads and shifts the parallel data of shift registers 1 and 2. By doing this, n-bit serial data SD1 and SD are generated from shift registers 1 and 2.
2 alternately, selects multiplexer 4, and outputs the serial data of shift register 1.
The serial data SD2 of the shift register 2 was outputted following the output of SD1.

According to the operation diagram in Fig. 5, one byte is 8 bits (n=8), and the first byte is D0 to D.
7 is in shift register 1, 2nd byte D8~D
15 shall be given to shift register 2,
A detailed description will be given assuming that 2 bytes of serial data D0 to D15 are output.

First, the shift control signal SC1 is turned on by the system clock SYSC T0, and the shift register 1 can be operated by the system clock SYSC.

At the same time, 8-bit parallel data D0 is transferred to shift register 1 by parallel load signal PR1.
~ D7 can now be loaded and the system clock
Parallel data D0 to D7 are loaded into the shift register 1 at the rising edge of T1 of SYSC. Thereafter, shift register 1 is shifted by system clock SYSC, and serial data SD1 is output.

Since the control signal MPC of the multiplexer 4 is turned on by the T1 clock of the system clock SYSC and is switched to the shift register 1 side, the serial data SD1 is outputted from the multiplexer 4. In this way, shift register 1 has T1
When the 8 clocks from T8 to T8 are input, the shift control signal SC1 is turned off, the input of the system clock is prohibited, and the shift operation is stopped. At the same time, the shift control signal SC2 is turned on, and the input of the system clock to the shift register 2 is permitted, enabling operation, and the parallel load signal
8-bit parallel data D8 to D15 are loaded into the shift register 2 by PR2,
Similarly, shift register 2 is shifted by system clock SYSC, serial data SD2 is output, and multiplexer control signal
MPC is switched to shift register 2 at system clock T9, and serial data SD2 is output from multiplexer 4.

In this way, by switching the multiplexer 4 in synchronization with the input permission of the system clock, the serial data SD1 and SD2 by the shift operations of the two shift registers 1 and 2 are output continuously, and 2 bytes worth of serial data SD1 and SD2 are output continuously. It outputs serial data.

[Problem that the invention seeks to solve]

However, in such a conventional P/S conversion circuit, it is necessary to provide a multiplexer 4 at the output stage of the shift registers 1 and 2, and therefore,
In addition to the problem that it is difficult to construct an inexpensive circuit, the multiplexer 4 is composed of a large number of gate elements (transistors), which increases the possibility of failure, making it difficult to improve reliability. The problem was that I couldn't do it.

In view of the above-mentioned points, an object of the present invention is to provide a parallel-to-serial conversion circuit that eliminates the need to select outputs of shift registers even when a plurality of shift registers are used alternately, and can eliminate a multiplexer. shall be.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

The present invention comprises a plurality of shift registers 1a and 2a each loaded with n-bit parallel data and converted into serial data by a shift operation, and a control circuit 3a that sequentially switches the shift operation of the plurality of shift registers. and outputs serial data from the plurality of shift registers, each of the plurality of shift registers is configured with an (n+1)-bit shift register in which the last bit data is fixed. At the same time, an OR circuit 5 is provided to OR the serial outputs of the plurality of shift registers, and its output is used as a parallel-to-serial conversion output.The control circuit shifts one shift register by n bits and performs a shift. It is characterized in that the output after the operation is set to the data state of the final bit, and the other shift registers are controlled to be shifted by n bits.

[Effect]

In the present invention, the shift registers 1a and 2a to which n-bit parallel data is loaded are shifted to the (n+1)th bit set to a fixed value. An OR circuit 5 is provided at the output stage.

Therefore, as shown in FIG. 1B, the shift register 1a is loaded with n-bit parallel data.
When shifted to the (n+1)th bit, the final output becomes the fixed value "0" for the (n+1)th bit.

Therefore, even if loading and shifting of parallel data is started in the shift register 2a after the output of the n-th bit of the shift register 1a, the shift register 1a
Since the output of a is “0”, the logical sum (ao) circuit 5
From then on, only the output of the shift register 2a is output.

As a result, the output stage of the shift registers 1a and 2a can be a simple OR circuit 5, and there is no need for a complicated multiplexer and its output selection.
This makes it possible to have an inexpensive configuration and also improves reliability.

〔Example〕

(a) Description of one embodiment FIG. 2 is a configuration diagram of an embodiment of the present invention.

In the figure, the same components as those shown in FIG. 1 are indicated by the same symbols, and 30 is a load signal generation circuit, which divides the frequency of the system clock SYSC to generate parallel load signals PR1 and PR2. Reference numerals 31 and 32 are shift signal generating circuits which divide the frequency of the system clock SYSC to generate shift control signals SC3 and SC4.

In this embodiment, shift registers 1a, 2a
has a capacity of 9 bits for 8 bits of input parallel data, and the 9th and final bit is set to "0".

Each of the shift registers 1a and 2a receives the system clock SYSC, shift control signals SC3 and SC4 from the control circuit 3a for enabling clock operation, and a parallel load signal PR for parallel loading.
1, PR2 is input.

FIG. 3 is an explanatory diagram of the operation of the configuration shown in FIG.

The control circuit 3a divides the frequency of the system clock SYSC to generate parallel load signals PR1, PR2 and shift control signals SC3, SC4. That is, the load signal generation circuit 30 of the control circuit 3a
creates parallel load signals PR1 and PR2 with a cycle of 16 clocks of system clock SYSC, parallel load signal PR1 is synchronized with system clocks T0, T16, etc., and parallel load signal PR2 is synchronized with system clocks T8, T24. …
Shift signal generation circuit 3 created in synchronization with
2 generates a shift control signal SC3 that is on between system clocks T0 and T8, and a shift signal generating circuit 31 generates a shift control signal SC4 that is on between system clocks T8 and T16.

Therefore, each shift register 1a, 2a can operate for nine system clocks by each shift control signal SC3, SC4.

The operation of the configuration shown in FIG. 2 will be explained based on FIG.

Parallel load signal PR1 and shift control signal SC at T0 of system clock SYSC
3 is turned on, and the shift register 1a can be operated by the system clock SYSC.
On the other hand, the shift control signal SC4 is turned off, and the shift register 2a is set to the system clock SYSC.
The operation is prohibited and the output remains at the final bit "0".

In this state, the system clock SYSC T1
As a result, 8-bit parallel data D0 to D7 are loaded into the shift register 1a, and the first bit D0 is output from the shift register 1a.

From then on, T2 and T of the system clock SYSC
3..., the shift register 1a performs a shift operation, and the second bit D1, the third bit D2, etc. of the loaded parallel data are sequentially output serially.

When the system clock SYSC reaches the rising edge of T8, the parallel load signal PR2 and shift control signal SC4 are turned on, and the shift register 2a can be operated by the system clock. On the other hand, the shift register 1a outputs the 8th bit D in synchronization with the system clock T8.
Outputs 7.

When T9 of the system clock SYSC rises,
Shift register 1a shifts to the 9th bit, so the output is forced to “0” like 8'.
Then, the shift control signal SC3 turns off, and subsequent shift operations by the system clock are prohibited, and the serial output SD1 holds "0" thereafter.

At the same time, 8-bit parallel data D8 to D15 are loaded into the shift register 2a, and the first bit D8 is output from the shift register 2a. In particular, since the output of the shift register 1a is "0" at the 9th bit, the OR circuit 5 outputs the serial output SD2 of the shift register 2a.

From here on, T10, T of the system clock SYSC
11..., the shift register 2a
shifts, and the 2nd bit D9 and the 3rd bit D10 of the loaded parallel data
... are serially output in sequence.

When the system clock SYSC reaches the rising edge of T16, the parallel load signal PR1 and shift control signal SC3 are turned on again, and the shift register 1a can be operated by the system clock. On the other hand, shift register 2a
outputs the 8th bit D15 in synchronization with the system clock T16.

When T17 of the system clock SYSC rises, the shift register 2a shifts to the 9th bit, so the output is forced to "0" as shown in 16', and the shift control signal SC
4 is turned off, subsequent operations by the system clock are prohibited, and the serial output D2 holds "0" thereafter.

At the same time, 8-bit parallel data D0 to D7 are similarly loaded into the shift register 1a, the first bit D0 is output, and the operations following the step are repeated.

Therefore, the output serial data of the OR circuit 5
As shown in Figure 3, SD is the 1st byte, 2nd byte,
...becomes a serial sequence.

In this way, shift registers 1a, 2a
Add 1 bit to n, the number of bits to be loaded in parallel to n, and set this bit to “0”.
The operation by the clock is alternated by (n+1) bits, and the output at the end of the operation is held at "0".

Therefore, when serial data is output by the clock operation of one of the shift registers 1a and 2a (during serial conversion), since the other shift register outputs "0", the OR circuit 5 It becomes possible to output serially converted data from the shift register.

(b) Description of other embodiments In the above embodiments, the explanation was given using an example of parallel data with n=8, but the explanation is not limited to this, and although the explanation was given using two shift registers as an example, it is also possible to use three or more shift registers. In short, it is sufficient if there is a plurality of numbers.

Also, I explained the logical sum circuit using an OR circuit, but
It may also be a NOR circuit or the like.

Although the present invention has been described above using one embodiment, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, in a parallel-to-serial conversion circuit equipped with a plurality of shift registers, a multiplexer is not required at the final stage of the shift registers, and an OR circuit is sufficient, so the circuit configuration can be made inexpensive. It has the effect of being able to

Furthermore, since the configuration of the final stage is simplified, the possibility of occurrence of failures is reduced, and a highly reliable circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the invention, FIG. 3 is a diagram explaining the operation of an embodiment of the invention, FIG. The figure is an explanatory diagram of the operation of the prior art. In the figure, 1a, 2a... shift register, 3a...
...Control circuit, 5...Order circuit.

Claims (1)

[Claims] 1. A plurality of shift registers 1a and 2a each loaded with n-bit parallel data and converted into serial data by a shift operation, and control for sequentially switching the shift operations of the plurality of shift registers. circuit 3a, and outputs serial data from the plurality of shift registers, each of the plurality of shift registers is configured as an (n+1)-bit shift register in which the last bit data is fixed. At the same time, an OR circuit is provided to OR the serial outputs of the plurality of shift registers, and the output thereof is used as a parallel/serial conversion output, and the control circuit shifts one shift register by n bits. . A parallel/serial conversion circuit characterized in that the output after the shift operation is set to the data state of the final bit, and other shift registers are controlled to be shifted by n bits.