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JPH0374048B2 - - Google Patents
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JPH0374048B2 - - Google Patents

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Publication number
JPH0374048B2
JPH0374048B2 JP597282A JP597282A JPH0374048B2 JP H0374048 B2 JPH0374048 B2 JP H0374048B2 JP 597282 A JP597282 A JP 597282A JP 597282 A JP597282 A JP 597282A JP H0374048 B2 JPH0374048 B2 JP H0374048B2
Authority
JP
Japan
Prior art keywords
circuit
memory
power supply
power
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP597282A
Other languages
Japanese (ja)
Other versions
JPS58124319A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP597282A priority Critical patent/JPS58124319A/en
Publication of JPS58124319A publication Critical patent/JPS58124319A/en
Publication of JPH0374048B2 publication Critical patent/JPH0374048B2/ja
Granted legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Description

【発明の詳細な説明】 本発明は、テレビ受信機に使用される選局装置
に関し、特に不揮発性メモリを用いた選局装置に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection device used in a television receiver, and particularly to a channel selection device using a nonvolatile memory.

従来、不揮発性メモリを用いた選局装置ではメ
モリのデータ書き込み、読み出し用電源として、
負の高い電圧が必要であり、この負電源として
は、コスト的に優利なテレビ受信機のFBT(フラ
イバツクトランス)の2次巻線からとり出す方式
が広く用いられている。
Conventionally, in channel selection devices using non-volatile memory, the power supply for writing and reading data in the memory is
A high negative voltage is required, and as this negative power source, a method is widely used in which the negative power source is taken out from the secondary winding of the FBT (flyback transformer) of the television receiver, which is advantageous in terms of cost.

特にリモコン内蔵の選局装置では、リモコン動
作を行なうために常に電源を供給しておく必要が
あるが、メモリ用電源はテレビ受信機等の電源が
オフであるため電圧が得られない。このため、電
源オン時、不揮発性メモリのデータを読み出すた
めには、メモリ用電源の電圧が立上がつて安定に
なるまで待つてから読み出しを開始する必要があ
る。このため、このような待ち時間が必要であ
り、すぐに動作することができなかつた。
In particular, in a channel selection device with a built-in remote control, it is necessary to constantly supply power in order to operate the remote control, but the power supply for the memory cannot obtain voltage because the power of the television receiver or the like is off. Therefore, in order to read data from the nonvolatile memory when the power is turned on, it is necessary to wait until the voltage of the memory power supply rises and becomes stable before starting reading. For this reason, such a waiting time is required, and it is not possible to operate immediately.

本発明の目的は、上述のような従来の選局装置
の欠点をなくすために、メモリのデータ読み出し
時の待ち時間を短かくした選局装置を提供するに
ある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a channel selection device that reduces the waiting time when reading data from a memory in order to eliminate the drawbacks of the conventional channel selection device as described above.

本発明は、選局装置全体の電源をオンしてシス
テムリセツト回路が働いた場合、そのリセツト状
態を検知、保持し、リセツト動作後最初にキー入
力により電源をオンした時は、メモリ電源回路の
電圧が安定になるまである一定時間メモリ読み出
しを遅延させ、その後メモリ読み出しを行ない、
それ以降キー入力による電源オン、オフではメモ
リ読み出しを行なわず、メモリ電源が安定になる
まで待つことなく選局できるものである。
The present invention detects and maintains the reset state when the system reset circuit operates when the power of the entire channel selection device is turned on, and when the power is turned on by key input for the first time after the reset operation, the memory power supply circuit is activated. Memory read is delayed for a certain period of time until the voltage stabilizes, and then memory read is performed.
Thereafter, when the power is turned on or off by key input, the memory is not read out, and the channel can be selected without having to wait until the memory power becomes stable.

以下に、第1図を参照して本発明の実施例につ
いて説明する。
Embodiments of the present invention will be described below with reference to FIG.

1はキーボードによるキー入力を判別し、電源
制御回路4を駆動して電源オン、オフを制御し、
さらにリセツト記憶回路2の出力状態に応じて不
揮発性メモリ7のデータの読み出し、書き込みを
制御するメモリ制御回路、2はリセツト回路3が
働いたかどうかのリセツト状態を記憶するリセツ
ト記憶回路、3は選局装置全体の電源オン時シス
テムをリセツトするためのリセツト信号をリセツ
ト記憶回路2、メモリ制御回路1に供給するリセ
ツト回路、4は電源回路9へのAC電源入力をオ
ン、オフする電源スイツチを制御する電源制御回
路、5は電源をオン、オフするためのキー入力を
行なうキーボード、6はメモリ制御回路1、リセ
ツト記憶回路2、リセツト回路3、及び電源制御
回路4に常時電源を供給するための電源回路、7
はメモリ制御回路1のデータと常に一致するよう
にデータを記憶し、電源オン時にメモリデータを
読みだし、電源オフ以前の状態にするためにデー
タを記憶するの不揮発性メモリ、8は不揮発性メ
モリ7の読み出し、書き込みを行なうための負電
源を供給するテレビ受信機の偏向回路、9は偏向
回路8に電源を供給するための電源回路、10は
電源回路9へのAC入力をオン、オフする第2の
電源スイツチ、11は電源回路6および電源スイ
ツチ10へのAC入力をオン、オフする第1の電
源スイツチである。
1 determines key input from the keyboard and drives the power supply control circuit 4 to control power on/off;
Further, a memory control circuit controls reading and writing of data in the non-volatile memory 7 according to the output state of the reset memory circuit 2, a reset memory circuit 2 stores the reset state indicating whether the reset circuit 3 has worked, and 3 a selection memory circuit. A reset circuit supplies a reset signal for resetting the system to the reset storage circuit 2 and the memory control circuit 1 when the power of the entire station equipment is turned on. 4 controls a power switch that turns on and off the AC power input to the power supply circuit 9. 5 is a keyboard for inputting keys to turn on and off the power; 6 is a keyboard for constantly supplying power to the memory control circuit 1, the reset storage circuit 2, the reset circuit 3, and the power control circuit 4; Power supply circuit, 7
8 is a non-volatile memory that stores data so that it always matches the data of the memory control circuit 1, reads the memory data when the power is turned on, and stores the data to restore the state before the power is turned off; 8 is a non-volatile memory; 7, a deflection circuit of a television receiver that supplies negative power for reading and writing; 9, a power supply circuit for supplying power to the deflection circuit 8; 10, turning on and off the AC input to the power supply circuit 9; A second power switch 11 is a first power switch that turns on and off the AC input to the power circuit 6 and the power switch 10.

次に回路の動作を説明する。まず最初に、電源
スイツチ11をオンにすると、電源回路6が動作
し、メモリ制御回路1、リセツト記憶回路2、リ
セツト回路3、電源制御回路4に電源が供給され
る。この時、リセツト回路3の働きにより電源オ
ンが検出され、システムを初期状態にリセツトす
るためのリセツト信号が、リセツト記憶回路2お
よびメモリ制御回路1に供給され、リセツト記憶
回路2にはリセツト動作が行なわれたことが記憶
される。また、リセツト動作により電源制御回路
4が電源スイツチ10をオフするように初期設定
され、電源オン待機状態となる。
Next, the operation of the circuit will be explained. First, when the power switch 11 is turned on, the power supply circuit 6 operates, and power is supplied to the memory control circuit 1, reset storage circuit 2, reset circuit 3, and power supply control circuit 4. At this time, power-on is detected by the function of the reset circuit 3, and a reset signal for resetting the system to the initial state is supplied to the reset memory circuit 2 and the memory control circuit 1, and the reset memory circuit 2 is configured to perform a reset operation. What has been done is remembered. Further, by the reset operation, the power supply control circuit 4 is initially set to turn off the power switch 10, and enters a power-on standby state.

次に、キーボード5により電源オンするための
キー入力を行なうと、電源スイツチ10がオンす
るように電源制御回路4が働き、電源回路9に
AC電源が供給され、偏向回路8にも電源が供給
されて動作を開始し、偏向回路8内のFBTの2
次巻線より取り出した負電圧が不揮発性メモリ7
に供給される。メモリ制御回路1は、負電圧が立
上つて安定になるまである一定時間(約300ms)
待機し、その後電源オフ直前のデータにするため
不揮発性メモリ7よりデータの読み出しを行な
う。また、メモリ内容を読み出した後は、メモリ
制御回路1内のデータを書き換えるたびに、この
内容と不揮発性メモリ7の内容を常に一致するよ
うにメモリ内容の書き換えを行なう。
Next, when a key is input on the keyboard 5 to turn on the power, the power control circuit 4 operates to turn on the power switch 10, and the power supply circuit 9 is activated.
AC power is supplied, power is also supplied to the deflection circuit 8, the operation starts, and two of the FBTs in the deflection circuit 8 are
The negative voltage taken out from the next winding is the non-volatile memory 7.
is supplied to Memory control circuit 1 takes a certain period of time (approximately 300ms) until the negative voltage rises and becomes stable.
After waiting, data is read from the non-volatile memory 7 in order to obtain the data immediately before the power is turned off. Further, after reading the memory contents, each time the data in the memory control circuit 1 is rewritten, the memory contents are rewritten so that the contents always match the contents of the nonvolatile memory 7.

次に、キー入力により電源をオフした場合を考
えると、電源オン状態ではメモリ制御回路1内の
データと不揮発性メモリ7内のデータは常に一致
しているため、電源をオフにしても再び電源を入
れた時は、不揮発性メモリ7のデータを読み出せ
ば、電源オフ直前のデータが再び得られることに
なる。
Next, considering the case where the power is turned off by key input, the data in the memory control circuit 1 and the data in the non-volatile memory 7 always match when the power is on, so even if the power is turned off, the power is turned off again. When the power is turned on, by reading the data in the nonvolatile memory 7, the data immediately before the power was turned off can be obtained again.

ここで、電源オンするたびに不揮発性メモリ7
のデータ読み出しを行なつていたのでは、負電源
電圧の安定化待ちのための無駄な時間が必要とな
るため、本発明は、電源オン時にリセツト記憶回
路2の状態を検知し、リセツト動作が行なわれて
いない内容であれば不揮発性メモリ7からのメモ
リ読み出しを不要とし、リセツト動作が行なわれ
た内容であれば、メモリ読み出しを行なうもので
ある。
Here, each time the power is turned on, the non-volatile memory 7
If the data is read out, it would be wasted time waiting for the negative power supply voltage to stabilize. Therefore, the present invention detects the state of the reset memory circuit 2 when the power is turned on, and performs the reset operation. If the content has not been performed yet, there is no need to read the memory from the nonvolatile memory 7, and if the content has been reset, the memory read is performed.

以上述べたように、本発明によればメモリ読み
出し時間を短縮でき効率のよい動作を行なうこと
ができる。
As described above, according to the present invention, memory read time can be shortened and efficient operation can be performed.

【図面の簡単な説明】[Brief explanation of drawings]

図は、本発明による選局装置の一実施例を示す
回路図である。 1……メモリ制御回路、2……リセツト記憶回
路、3……リセツト回路、4……電源制御回路、
5……キーボード、6……外部電源回路、7……
不揮発性メモリ、8……水平偏向回路、9……水
平偏向回路用電源回路。
The figure is a circuit diagram showing an embodiment of a channel selection device according to the present invention. 1...Memory control circuit, 2...Reset storage circuit, 3...Reset circuit, 4...Power control circuit,
5...Keyboard, 6...External power supply circuit, 7...
Non-volatile memory, 8... horizontal deflection circuit, 9... power supply circuit for the horizontal deflection circuit.

Claims (1)

【特許請求の範囲】 1 テレビ受信機に使用される不揮発性メモリを
用いた選局装置において、 前記不揮発性メモリの電源用として前記テレビ
受信機の水平偏向回路より供給されるメモリ用電
源回路8と、 前記不揮発性メモリを制御し、メモリ内容の読
み出し、書き込みを行なうメモリ制御回路1と、 前記メモリ制御回路を初期状態に設定するリセ
ツト回路3と、 以前にリセツト回路3が働いたかどうかリセツ
ト状態を記憶するリセツト記憶回路2と、 前記メモリ制御回路1、リセツト回路3及びリ
セツト記憶回路2に電源を供給する外部電源回路
6と、 この外部電源回路への電源供給のオン・オフを
する第1のスイツチ11と、 前記テレビ受信機の水平偏向回路を駆動するた
めの電源を制御する電源制御回路9と、 この電源制御回路9への電源供給のオン・オフ
をする第2のスイツチ10と、 この電源制御回路9を働かすためのキー入力回
路5からなり、 上記第1のスイツチ11をオンとしてリセツト
回路3が働いた場合、そのリセツト状態を検知保
持し、リセツト動作後、最初にキー入力により電
源制御回路4を動作させ、第2のスイツチ10を
オンとして電源を入れた時は、メモリ電源回路8
の電圧が安定になるまである一定時間メモリ読み
出しを遅延させた後、メモリ読み出しを行ない、 それ以降に、キー入力により第2のスイツチ1
0をオンとして電源を入れた時は、メモリ読み出
しを行なわず、メモリ電源が安定になるまで待つ
ことなく選局することを特徴とした選局装置。
[Scope of Claims] 1. A channel selection device using nonvolatile memory used in a television receiver, comprising: a memory power supply circuit 8 supplied from a horizontal deflection circuit of the television receiver as a power source for the nonvolatile memory. a memory control circuit 1 that controls the nonvolatile memory and reads and writes memory contents; a reset circuit 3 that sets the memory control circuit to an initial state; and a reset state as to whether the reset circuit 3 has worked previously. an external power supply circuit 6 that supplies power to the memory control circuit 1, the reset circuit 3, and the reset memory circuit 2; and a first circuit that turns on and off the power supply to the external power supply circuit. a power supply control circuit 9 that controls the power supply for driving the horizontal deflection circuit of the television receiver; and a second switch 10 that turns on and off the power supply to the power supply control circuit 9. It consists of a key input circuit 5 for operating this power supply control circuit 9, and when the first switch 11 is turned on and the reset circuit 3 is operated, the reset state is detected and held, and after the reset operation, the first key input is performed. When the power supply control circuit 4 is operated and the second switch 10 is turned on to turn on the power, the memory power supply circuit 8
After delaying memory reading for a certain period of time until the voltage of
This channel selection device is characterized in that when the power is turned on with 0 turned on, it does not read out the memory and selects a channel without waiting until the memory power becomes stable.
JP597282A 1982-01-20 1982-01-20 Channel selecting device Granted JPS58124319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP597282A JPS58124319A (en) 1982-01-20 1982-01-20 Channel selecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP597282A JPS58124319A (en) 1982-01-20 1982-01-20 Channel selecting device

Publications (2)

Publication Number Publication Date
JPS58124319A JPS58124319A (en) 1983-07-23
JPH0374048B2 true JPH0374048B2 (en) 1991-11-25

Family

ID=11625764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP597282A Granted JPS58124319A (en) 1982-01-20 1982-01-20 Channel selecting device

Country Status (1)

Country Link
JP (1) JPS58124319A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6035634U (en) * 1983-08-18 1985-03-12 三洋電機株式会社 Channel selection device

Also Published As

Publication number Publication date
JPS58124319A (en) 1983-07-23

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