JPH0374971B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a comparison circuit, and more specifically, to a comparison circuit using field effect transistors.

[Conventional technology]

FIG. 4 shows an example of a conventionally well-known comparison circuit. 401 is a first power supply terminal, 402 is a second power supply terminal, 403 is a first input terminal, 404 is a second input terminal, 405 is an output terminal, 406 is a first
A conductive field effect transistor (hereinafter abbreviated as FFT) 407 is an inverting amplifier 4 along with a FET 406.
08 is a second conductivity type FET, 409 is an addition capacitor, and 410 and 411 are for connecting the input from the first input terminal 403 and the input from the second input terminal 404 to the addition capacitor 409 alternately. The switch 412 is a switch for connecting the input and output of the inverting amplifier.

Next, the operation of the circuit shown in FIG. 4 will be explained.
The circuit shown in Fig. 4 belongs to a type of comparison circuit called a self-calibration type comparison circuit, and its operation repeats two modes: φ in calibration mode and comparison mode. 40
3 and the potential of the input terminal 404 and output the result to the output terminal 405.

First, in the calibration mode φ, the switch 41
0,412 is closed and switch 411 is opened. At this time, the threshold potential of the inverting amplifier is applied to the inverting amplifier 408 side of the summing capacitor 409, and the potential of the input terminal 403 is applied to the opposite side. Charge is accumulated.

Next, due to this state, a transition is made to the comparison mode. In comparison mode, switches 410, 412
is opened and switch 411 is closed. At this time, the potential of the input terminal 404 is applied to the input side of the summing capacitor 409, and since the summing capacitor 409 itself holds the charge accumulated during the calibration mode φ, the potential of the input terminal 404 is applied to the input side of the summing capacitor 409. If the potential of the inverting amplifier 408 is even slightly larger (smaller) than the potential of the input terminal 403, the input of the inverting amplifier 408 rises (falls) below its threshold value. A comparison of the potentials at terminal 404 is accomplished.

Since the circuit of this conventional example is of a self-calibration type, it has the advantage that the precision required for the device is less strict.

[Problem that the invention seeks to solve]

By the way, in the operation of the conventional comparison circuit mentioned above, one of the causes of malfunction is the calibration mode φ.
Another example is the variation of the threshold value of the inverting amplifier 408 in the comparison mode. This is because if the threshold of the inverting amplifier 408 is lowered (increased) in the comparison mode than in the calibration mode φ, even if the potentials of the input terminals 403 and 404 are equal, the summing capacitor 40
As a result of the charge being accumulated at the input terminal 404 assuming the threshold value in the calibration mode φ, the input terminal 404
This is because the potential of 403 appears higher (lower) than the potential of 403. For this reason, the threshold fluctuation of the inverting amplifier 408 becomes a big problem in this conventional example, but in the circuit of this conventional example, the inverting amplifier 408 is
06 and 407, fluctuations in the power supply voltage (difference between the potential of the first power supply terminal and the potential of the second power supply terminal) significantly affect the threshold value of the inverting amplifier 408. Therefore, the circuit of this conventional example has the disadvantage of being extremely susceptible to power supply voltage fluctuations.

The present invention has been made in view of the above points, and
The purpose of this invention is to provide a self-calibrating comparison circuit that is resistant to fluctuations in power supply voltage, especially a comparison circuit using FETs.

[Means for solving problems]

According to the present invention, the first power terminal, the second power terminal, the first input terminal, the second input terminal, the output terminal, the first power terminal and the second power terminal a first FET of a first type and a second FET of a second type connected in series between
A third FET of the first type and a fourth FET of the second type are connected in series between the first power terminal and the second power terminal to form a bias circuit.
FET, a first capacitive element whose one end is connected to the input of the above-mentioned inverting amplifier, and a first capacitive element placed between the remaining one end of the first capacitive element and the first input terminal and the second input terminal, respectively. the first and second switch elements, a third switch element placed between the input and output of the inverting amplifier, a second capacitor element whose one end is connected to the second power supply terminal, and a second capacitor element. A fourth switch element placed between the remaining end of the element and the output of the aforementioned bias circuit, a potential at a connection point between the fourth switch element and the second capacitive element, and a potential at the output of the bias circuit. a differential amplifier circuit that compares and amplifies the signals; a fifth switch element with one end connected to the output of the differential amplifier; one end connected to the output of the bias circuit; and the other end connected to the remaining one end of the fifth switch element. The source and drain are connected in parallel between the connected sixth switch element and the output of the above-mentioned inverting amplifier and the first or second power supply element, and a gate is connected at the connection point between the fifth and sixth switch. The connected fifth FET and
The source and drain are connected in parallel between the output of the bias circuit and the first or second power supply element, and the fifth
and a sixth FET whose gate is connected to the connection point of the sixth switch, and whose output terminal is connected to the output of the inverting amplifier.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the circuit of the present invention. 10
1 is a first power supply terminal, 102 is a second power supply terminal,
103 is a first input terminal, 104 is a second input terminal, 105 is an output terminal, 106 is a first FET of the first conductivity type, and 107 is a second FET of the second conductivity type.
Together, they constitute an inverting amplifier 108. 1
A third FET 09 of the first conductivity type forms a bias circuit 111 together with a fourth FET 110 of the second conductivity type. 112 is an inverting amplifier 10
8 is a first capacitive element (hereinafter referred to as an addition capacitor) that transmits a signal to the input, and 113 and 114 are first and second capacitors that alternately connect inputs coming from input terminals 103 and 104 to the addition capacitor. A switch element 115 is a third switch element 115 for shorting the input and output of the inverting amplifier 108.
6 is a second capacitive element (hereinafter referred to as a hold capacitor), 117 is a fourth switch element for short-circuiting the output of the bias circuit 111 and the hold capacitor 116, and 118 is a hold capacitor 116
121 is a differential amplifier circuit for comparing and amplifying the potential of the output potential of the bias circuit 111 and the output potential of the bias circuit 111;
FET 122 is a sixth FET of the second conductivity type for controlling the output of the bias circuit 111, 119,
120 is a switch element for switching the potential applied to the gates of FET 121 and FET 122 to the output of differential amplifier 118 or the output of bias circuit 111. In this example, FET106 and
FET109, FET107 and FET110, FET1
It is assumed that FET 21 and FET 122 are similar and well-matched.

The operation of the circuit shown in FIG. 1 consists of two modes: a calibration mode φ and a comparison mode.

First, in the calibration mode φ, the switch 11
3, 115, 117, 120 are closed and switches 114, 119 are opened. In this state, first, the output of the bias circuit 111 is determined by adding the drain and gate of the FET 122 connected between the output of the bias circuit 111 and the second power supply terminal 102. This output is stored in the hold capacitor 116 through the switch 117 and is also applied to the gate of the FET 121 at the same time. At this time, switch 115 is closed, so both FETs 106 and 107 have their drains and gates shorted, and now FETs 106 and 109, FETs 107 and 110, FETs 121 and 1
22 are well matched, the threshold value of the inverting amplifier 108 is the same as that of the bias circuit 1.
11, and its potential is applied to one end of the summing capacitor 112. Addition capacitor 11
Since the potential of the input terminal 103 is applied to the other end of the summing capacitor 112 via the switch 113, a charge equal to the potential difference between the potential of the input terminal 103 and the threshold of the inverting amplifier 108 is stored in the summing capacitor 112.
Next, from this state, the mode shifts to comparison mode. In comparison mode, switches 113, 115, 1
17,120 is opened, switch 114,119
is closed.

If there is no power supply fluctuation between the calibration mode φ and the comparison mode, the differential amplifier 118
The output of the hold capacitor 116 and the output of the bias circuit 111 are operated to match each other, and eventually settle to the same potential as the output of the bias circuit in the calibration mode. This output is also applied to the gate of FET 121 and affects the threshold of inverting amplifier 108, but in this case, since the gate potential of FET 121 does not change from that in the calibration mode, inverting amplifier 108
The threshold value of 08 also does not change. Therefore, the rest of the operation is the same as the conventional example shown in Figure 4, and switch 1
14 is higher (lower) than the input terminal 103, the input of the inverting amplifier 108 is higher (lower) than its threshold.
As an output, the potential of the output terminal 105 decreases (increases) and the comparison operation is completed.

Also, if we consider the case where there is a power supply fluctuation between the calibration mode φ and the comparison mode, what if the power supply voltage was larger (smaller and smaller) during the comparison mode than during the calibration mode φ? Ta)
Then, first, the output of the bias circuit 111 rises (drops), so the differential amplifier 118 detects this and raises (drops) its output potential, and the rise (drop) in potential is passed through the FET 122 to the bias circuit. Decrease (increase) the output of 111. Then, the differential amplifier 11
The output of 8 will rise (fall). Since the output of the differential amplifier 118 is also applied to the gate of the FET 121, a rise (fall) in this output causes a fall (increase) in the threshold of the inverting amplifier 108. However, at this time, the power supply voltage of the inverting amplifier 108 is also increasing (decreasing) in the same way as the bias circuit 111, so its threshold value has increased (decreased) from that in the calibration mode φ, and the decrease in the threshold value due to this FET 121 ( It can be seen that the threshold value of the inverting amplifier eventually becomes constant without being affected by fluctuations in the power supply voltage. The operation after this is the same as when there is no power fluctuation, and the input terminals 103 and 10
It is clear that a comparison of 4 potentials is achieved.

FIG. 2 shows a different embodiment of the invention. The embodiment shown in Fig. 1 was a circuit with a so-called CMOS (complementary MOS) configuration, but the embodiment shown in Fig. 2 is an E/D
MOS (Enhancement/Debrission MOS)
This is an example of a circuit called . The circuit configuration and operation are basically the same as the embodiment shown in FIG.

FIG. 3 shows yet another embodiment of the invention. In the embodiment shown in Fig. 3, two or more blocks each consisting of an inverting amplifier, a summing capacitor, and an input switch are arranged for one block consisting of a bias circuit, a hold capacitor, and a differential amplifier (in this example, there are four blocks each). ) is an example. It will be understood that this arrangement allows the present invention to be utilized even in a circuit in which a large number of comparison circuits are used (for example, a parallel analog-to-digital converter) without significantly increasing the number of elements.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a self-calibrating comparison circuit that is resistant to fluctuations in power supply voltage.

Since the circuit of the present invention is composed of a FET, a capacitive element, and a switch element, it is easy to use an IC (integrated circuit ), and by combining it with conventional digital technology in MOSIC, it can be applied to fields that are growing in the future, such as analog-digital mixed ICs. As described above, the present invention has a wide range of applications, and the practical benefits thereof are considerable.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is a circuit diagram of a different embodiment of the present invention, Fig. 3 is a circuit diagram of a further different embodiment of the present invention, and Fig. 4 is a conventional comparison. FIG. 2 is a circuit diagram of an example of a circuit. 101...First power supply terminal, 102...Second power supply terminal, 103, 104...Input terminal, 105
... Output terminal, 106, 109 ... First conductivity type
FET, 107, 110, 121, 122...FET of second conductivity type, 108...Inverting amplifier, 11
1... Bias circuit, 112, 116... Capacitive element, 113, 114, 115, 117, 119,
120... Switch element, 118... Differential amplifier, 201... First power supply terminal, 202... Second
power supply terminals, 203, 204...input terminals, 20
5... Output terminal, 206, 209... FET of first conductivity type, 207, 210, 221, 222...
FET of second conductivity type, 208...Inverting amplifier, 2
11... Bias circuit, 212, 216... Capacitive element, 213, 214, 215, 217, 21
9, 220... Switch element, 218... Differential amplifier, 301... First power supply element, 302... Second power supply terminal, 303a-d, 304a-d...
Input terminals, 305a-d...Output terminals, 306a
~d, 309...FET of first conductivity type, 307a
~d, 310, 321a-d, 322...FET of second conductivity type, 312a-d, 316... Capacitive element, 313a-d, 314a-d, 315a-
d, 317, 319, 320... switch element,
318... Differential amplifier, 401... First power supply element, 402... Second power supply terminal, 403, 404
...Input terminal, 405...Output terminal, 406...
FET of the first conductivity type, 407... of the second conductivity type
FET, 408...inverting amplifier, 409...capacitive element, 410, 411, 412... switch element.

Claims (1)

[Claims] 1. A first power terminal, a second power terminal, and a first power terminal.
an input terminal, a second input terminal, an inverting amplifier connected between the first power supply terminal and the second power supply terminal, and between the first power supply terminal and the second power supply terminal. a bias circuit connected to the inverting amplifier, a first capacitive element having one end connected to the input of the inverting amplifier, and a first capacitive element connected between the other end of the first capacitive element and the first input terminal. a switch element, a second switch element connected between the other end of the first capacitive element and the second input terminal, and a third switch element connected between the input and output of the inverting amplifier. a second capacitive element having one end connected to the second power supply terminal, and a fourth switch element connected to the other end of the second capacitive element between the output of the bias circuit; a differential amplifier circuit that compares and amplifies the potential at the other end of the second capacitive element and the potential at the output of the bias circuit; a fifth switch element having one end connected to the output of the differential amplifier circuit; a sixth switch element connected between the output of the bias circuit and the other end of the fifth switch element;
a first field effect transistor having a source-drain current path connected between the output of the inverting amplifier and the first or second power supply terminal and a gate connected to the other end of the fifth switch element; a second field effect transistor having a source-drain current path connected between the output of the bias circuit and the first or second power supply terminal and a gate connected to the other end of the fifth switch element; an output terminal connected to the output of the amplifier, wherein in a first mode the first, third, fourth and sixth switch elements are closed and the second and fifth switch elements are open. , and in the second mode, the first, third, fourth and sixth switch elements are opened and the second and fifth switch elements are closed. 2. The comparison circuit according to claim 1, wherein the inverting amplifier and the bias circuit have the same configuration, and the other end of the second capacitive element is connected to the input of the bias circuit. .