JPH0375911B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram type input/output control device, and when a fixed sequence in the form of a channel interface is executed by a logic circuit, the combination of logic circuits and processing speed are controlled by a microprogram. This invention relates to a control method for the logic circuit of an input/output control device.

Creating a logical circuit with a fixed sequence in the form of a channel interface is effective in shortening the command chain time, for example, making it possible to shorten the gap in a magnetic disk device, increasing the data recording area of the medium, and improving usage efficiency. effective. However, conventional logic circuits are created for each individual sequence, and creating logic circuits for several sequences or sequences with different processing speeds requires a large number of logic circuits, making it complex and expensive. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a simple and inexpensive method for controlling the logic circuits of an input/output control device in which the processing speed of a combination of logic circuits can be varied by a microprogram through a decoder, in order to eliminate the above-mentioned drawbacks.

In order to achieve the above object, the present invention provides a microprogram type input/output control device that uses tag-in and tag-out lines between channels to connect a plurality of sequences in a defined channel interface format to a logic circuit. When executing, the plurality of sequences are divided into common minimum sequences, and the logic circuits corresponding to the divided sequences and the combination of logic circuits corresponding to the plurality of sequences are specified. It is equipped with a decoder that outputs signals to the logic circuit, and by specifying the type of sequence to the decoder using a microprogram, the combination of the logic circuits can be changed using the output of the decoder, and the processing speed can be varied using the microprogram. This is a control method for a logic circuit of an input/output control device, which is characterized by the following features:

An embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a system diagram showing the relationship between the input/output control device and channel channels, Figure 2 is a time chart showing an example of a sequence, and Figure 3 is a logic circuit that uses flip-flops to implement the sequence in Figure 2. can also be constructed using counters, memories, and logic arrays.

In the figure, 1 is a processor, 2 is a channel, 3 is an input/output control device, 4 is an input/output device, 5 is a tag-out line, 6 is a D-in line, 7, 8, 9, 10, and 11 are flip-flops (hereinafter referred to as FF). ), 12,1
3, 14, 15 are AND circuits, 16, 17 are NOT circuits, A, B, C, D, H, H, T, CH, L,
Nu is an explanatory symbol and corresponds in FIGS. 2 and 3.

The response relationship of the channel interface is communicated by the D-in line 6 from the input/output control device 3 to the channel 2 and the tag-out line 5 from the channel 2 to the input/output control device 3, and the combination of this communication has a unique meaning as a sequence. ing.

In the case of FIGS. 2 and 3, the operation of the tag sequencer in the channel interface control circuit, which is separate from the microprocessor in the input/output control device 3, is explained. Tag-in 1 Tag-out 1 signal communication using the signal line, then Tag-in 2 and Tag-out 2
An example of a sequence for communicating tag-in 2 and tag-out 2 signals using the signal line is shown.
To explain this, first, the microprogram inputs a start signal A to start the tag-in 1 signal to the FF7. Then, the signal ``L'' of the tag-in 1 (output of the FF7) rises and is sent through the signal line of the tag-in 1, and the channel channel 2 detects this and raises the signal ``d'' of the tag-out 1. Then, the input/output control device 3 receives this through the tag-out 1 signal line, inputs it to the FF 7, and lowers the tag-in 1 signal. Channel 2 detects this through the tag-in 1 signal line and lowers the tag-out 1 signal. As the tagout 1 signal falls, the output of the NOT circuit 16 becomes "1" and FF9 becomes "1".
The signal is input to the tag-in 2 signal line, causing the tag-in 2 signal to rise. Channel 2 detects this through the tag-in 2 signal line and raises the tag-out 2 signal. The input/output control device 3 detects this through the tag-out 2 signal line, inputs it to the FF9, and lowers the tag-in 2 signal. Channel 2 detects this through the tag-in 2 signal line and lowers the tag-out 2 signal line. The input/output control device 3 detects this through the signal line of the tagout 2, outputs a signal of "1" from the NOT circuit 17, inputs a signal of "1" to the FF 11, outputs a completion signal from the FF 11, and terminates the communication.

However, the sequence is communication of tag-in 1 signal and tag-out 1 signal, communication of tag-in 2 and tag-out 2 signals, tag-in N and tag-out N
communication or a combination thereof.

The present invention divides a fixed sequence in a channel interface format into a common minimum sequence, has logic circuits corresponding to the divided sequences, and changes the combinations and processing speed of the logic circuits using a microcomputer. As an example, a case where logic circuits of three divided sequences are combined and a case where the processing speed is varied will be explained with reference to the block diagram of FIG.

In the figure, 18 and 19 are registers, 20 and 21 are decoders, 22 is a frequency divider, 23, 24, and 25 are logic circuits with a common minimum sequence, 26 to 39 are AND circuits, and 40 is a logic circuit combination circuit. be.

To change the processing speed, a timing setting signal is input and stored in the register 19 using a microprogram, and the decoder 20 divides the basic clock supplied to the AND circuit 26 or the basic clock supplied to the AND circuit 27. The frequency-divided clock is selected by the circuit 22 and supplied to the logic circuit combination circuit 40, and the clock pulses of the logic circuits 23, 24, 25 are changed to vary the processing speed.

When changing the combination of the logic circuits 23, 24, and 25, it is possible to set a desired sequence using a microprogram, input and store this signal in the register 18, and send a predetermined signal to the logic circuit combination circuit 40 by the decoder 21. . For example, as shown in the frame of the diagram of the decoder 21, the logic circuit 25 (S ₂ )
In the case of a sequence that uses the logic circuit 23 (S ₀ ) next, when the signals 100, 000, 001, 100 are sent, the start signal is sent to the logic circuit 25 via the AND circuit 34.
When the sequence of the logic circuit 25 (S _{2 )} is completed, the logic circuit 23 (S ₀ ) is started via the AND circuit 30, and when the sequence of the logic circuit 23 (S ₀ ) is completed, the AND circuit A completion signal is sent to the microprocessor via 37 to complete. Other examples of combinations are possible as well, such as those shown within the frame of the diagram of the decoder 21.

As a result, what conventionally required a logic circuit for each sequence can be realized by combining logic circuits, and the processing speed can also be varied.

This can also be applied to the case where a well-defined sequence between input/output control devices and between an input/output control device and an input/output device is converted into a logic circuit.

As explained in detail above, according to the present invention, many sequences can be converted into logic circuits by combining a small number of logic circuits, and the ability of microprograms is not lowered than before, so it is particularly effective for command chains, etc. Since the processing speed can also be varied, interface control with low-speed channels can be implemented as a logic circuit using the same input/output control device, and various sequences can be easily implemented as logic circuits at low cost.

[Brief explanation of drawings]

Figure 1 is a system diagram showing the relationship between the input/output control device and channels, Figure 2 is a time chart showing an example of a sequence, Figure 3 is a logic circuit configured with the sequence in Figure 2 using flip-flops, and Figure 4 1 is a block diagram in which combinations of logic circuits and processing speed are made variable in a microprogram according to an embodiment of the present invention. In the figure, 1 is a processor, 2 is a channel, 3 is an input/output control device, 4 is an input/output device, 5 is a tag-out line, 6 is a tag-in line, 7 to 11 are FFs, and 12 to 1
5, 26 to 39 are AND circuits, 16, 17 are NOT circuits, 18, 19 are registers, 20, 21 are decoders, 22 is a frequency divider, 23, 24, 25 are common minimum sequence logic circuits, Reference numeral 40 indicates a logic circuit combination circuit, and numerals 1 to 2 indicate explanatory symbols.

Claims (1)

[Claims] 1. In a microprogram type input/output control device, when multiple sequences with a fixed channel interface format are executed in a logic circuit using tag-in and tag-out lines between channels, the multiple sequences are Common items are divided into common minimum sequences, have logic circuits corresponding to the divided sequences, and have a decoder that outputs a signal specifying a combination of logic circuits corresponding to multiple sequences to the logic circuit. , an input/output control characterized in that, by specifying a sequence type to the decoder in a microprogram, the combination of the logic circuits is changed by the output of the decoder to execute a predetermined sequence. A control method for the device's logic circuit.